[people/ms/u-boot.git] / drivers / spi / rk_spi.c

/*
 * spi driver for rockchip
 *
 * (C) Copyright 2015 Google, Inc
 *
 * (C) Copyright 2008-2013 Rockchip Electronics
 * Peter, Software Engineering, <superpeter.cai@gmail.com>.
 *
 * SPDX-License-Identifier:     GPL-2.0+
 */

#include <common.h>
#include <clk.h>
#include <dm.h>
#include <errno.h>
#include <spi.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/periph.h>
#include <dm/pinctrl.h>
#include "rk_spi.h"

DECLARE_GLOBAL_DATA_PTR;

/* Change to 1 to output registers at the start of each transaction */
#define DEBUG_RK_SPI	0

struct rockchip_spi_platdata {
	s32 frequency;		/* Default clock frequency, -1 for none */
	fdt_addr_t base;
	uint deactivate_delay_us;	/* Delay to wait after deactivate */
	uint activate_delay_us;		/* Delay to wait after activate */
};

struct rockchip_spi_priv {
	struct rockchip_spi *regs;
	struct clk clk;
	unsigned int max_freq;
	unsigned int mode;
	ulong last_transaction_us;	/* Time of last transaction end */
	u8 bits_per_word;		/* max 16 bits per word */
	u8 n_bytes;
	unsigned int speed_hz;
	unsigned int last_speed_hz;
	unsigned int tmode;
	uint input_rate;
};

#define SPI_FIFO_DEPTH		32

static void rkspi_dump_regs(struct rockchip_spi *regs)
{
	debug("ctrl0: \t\t0x%08x\n", readl(&regs->ctrlr0));
	debug("ctrl1: \t\t0x%08x\n", readl(&regs->ctrlr1));
	debug("ssienr: \t\t0x%08x\n", readl(&regs->enr));
	debug("ser: \t\t0x%08x\n", readl(&regs->ser));
	debug("baudr: \t\t0x%08x\n", readl(&regs->baudr));
	debug("txftlr: \t\t0x%08x\n", readl(&regs->txftlr));
	debug("rxftlr: \t\t0x%08x\n", readl(&regs->rxftlr));
	debug("txflr: \t\t0x%08x\n", readl(&regs->txflr));
	debug("rxflr: \t\t0x%08x\n", readl(&regs->rxflr));
	debug("sr: \t\t0x%08x\n", readl(&regs->sr));
	debug("imr: \t\t0x%08x\n", readl(&regs->imr));
	debug("isr: \t\t0x%08x\n", readl(&regs->isr));
	debug("dmacr: \t\t0x%08x\n", readl(&regs->dmacr));
	debug("dmatdlr: \t0x%08x\n", readl(&regs->dmatdlr));
	debug("dmardlr: \t0x%08x\n", readl(&regs->dmardlr));
}

static void rkspi_enable_chip(struct rockchip_spi *regs, bool enable)
{
	writel(enable ? 1 : 0, &regs->enr);
}

static void rkspi_set_clk(struct rockchip_spi_priv *priv, uint speed)
{
	uint clk_div;

	clk_div = clk_get_divisor(priv->input_rate, speed);
	debug("spi speed %u, div %u\n", speed, clk_div);

	writel(clk_div, &priv->regs->baudr);
	priv->last_speed_hz = speed;
}

static int rkspi_wait_till_not_busy(struct rockchip_spi *regs)
{
	unsigned long start;

	start = get_timer(0);
	while (readl(&regs->sr) & SR_BUSY) {
		if (get_timer(start) > ROCKCHIP_SPI_TIMEOUT_MS) {
			debug("RK SPI: Status keeps busy for 1000us after a read/write!\n");
			return -ETIMEDOUT;
		}
	}

	return 0;
}

static void spi_cs_activate(struct udevice *dev, uint cs)
{
	struct udevice *bus = dev->parent;
	struct rockchip_spi_platdata *plat = bus->platdata;
	struct rockchip_spi_priv *priv = dev_get_priv(bus);
	struct rockchip_spi *regs = priv->regs;

	debug("activate cs%u\n", cs);
	writel(1 << cs, &regs->ser);
	if (plat->activate_delay_us)
		udelay(plat->activate_delay_us);
}

static void spi_cs_deactivate(struct udevice *dev, uint cs)
{
	struct udevice *bus = dev->parent;
	struct rockchip_spi_platdata *plat = bus->platdata;
	struct rockchip_spi_priv *priv = dev_get_priv(bus);
	struct rockchip_spi *regs = priv->regs;

	debug("deactivate cs%u\n", cs);
	writel(0, &regs->ser);

	/* Remember time of this transaction so we can honour the bus delay */
	if (plat->deactivate_delay_us)
		priv->last_transaction_us = timer_get_us();
}

static int rockchip_spi_ofdata_to_platdata(struct udevice *bus)
{
	struct rockchip_spi_platdata *plat = bus->platdata;
	struct rockchip_spi_priv *priv = dev_get_priv(bus);
	const void *blob = gd->fdt_blob;
	int node = bus->of_offset;
	int ret;

	plat->base = dev_get_addr(bus);

	ret = clk_get_by_index(bus, 0, &priv->clk);
	if (ret < 0) {
		debug("%s: Could not get clock for %s: %d\n", __func__,
		      bus->name, ret);
		return ret;
	}

	plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
					 50000000);
	plat->deactivate_delay_us = fdtdec_get_int(blob, node,
					"spi-deactivate-delay", 0);
	plat->activate_delay_us = fdtdec_get_int(blob, node,
						 "spi-activate-delay", 0);
	debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d\n",
	      __func__, (uint)plat->base, plat->frequency,
	      plat->deactivate_delay_us);

	return 0;
}

static int rockchip_spi_probe(struct udevice *bus)
{
	struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
	struct rockchip_spi_priv *priv = dev_get_priv(bus);
	int ret;

	debug("%s: probe\n", __func__);
	priv->regs = (struct rockchip_spi *)plat->base;

	priv->last_transaction_us = timer_get_us();
	priv->max_freq = plat->frequency;

	/*
	 * Use 99 MHz as our clock since it divides nicely into 594 MHz which
	 * is the assumed speed for CLK_GENERAL.
	 */
	ret = clk_set_rate(&priv->clk, 99000000);
	if (ret < 0) {
		debug("%s: Failed to set clock: %d\n", __func__, ret);
		return ret;
	}
	priv->input_rate = ret;
	debug("%s: rate = %u\n", __func__, priv->input_rate);
	priv->bits_per_word = 8;
	priv->tmode = TMOD_TR; /* Tx & Rx */

	return 0;
}

static int rockchip_spi_claim_bus(struct udevice *dev)
{
	struct udevice *bus = dev->parent;
	struct rockchip_spi_priv *priv = dev_get_priv(bus);
	struct rockchip_spi *regs = priv->regs;
	u8 spi_dfs, spi_tf;
	uint ctrlr0;

	/* Disable the SPI hardware */
	rkspi_enable_chip(regs, 0);

	switch (priv->bits_per_word) {
	case 8:
		priv->n_bytes = 1;
		spi_dfs = DFS_8BIT;
		spi_tf = HALF_WORD_OFF;
		break;
	case 16:
		priv->n_bytes = 2;
		spi_dfs = DFS_16BIT;
		spi_tf = HALF_WORD_ON;
		break;
	default:
		debug("%s: unsupported bits: %dbits\n", __func__,
		      priv->bits_per_word);
		return -EPROTONOSUPPORT;
	}

	if (priv->speed_hz != priv->last_speed_hz)
		rkspi_set_clk(priv, priv->speed_hz);

	/* Operation Mode */
	ctrlr0 = OMOD_MASTER << OMOD_SHIFT;

	/* Data Frame Size */
	ctrlr0 |= spi_dfs << DFS_SHIFT;

	/* set SPI mode 0..3 */
	if (priv->mode & SPI_CPOL)
		ctrlr0 |= SCOL_HIGH << SCOL_SHIFT;
	if (priv->mode & SPI_CPHA)
		ctrlr0 |= SCPH_TOGSTA << SCPH_SHIFT;

	/* Chip Select Mode */
	ctrlr0 |= CSM_KEEP << CSM_SHIFT;

	/* SSN to Sclk_out delay */
	ctrlr0 |= SSN_DELAY_ONE << SSN_DELAY_SHIFT;

	/* Serial Endian Mode */
	ctrlr0 |= SEM_LITTLE << SEM_SHIFT;

	/* First Bit Mode */
	ctrlr0 |= FBM_MSB << FBM_SHIFT;

	/* Byte and Halfword Transform */
	ctrlr0 |= spi_tf << HALF_WORD_TX_SHIFT;

	/* Rxd Sample Delay */
	ctrlr0 |= 0 << RXDSD_SHIFT;

	/* Frame Format */
	ctrlr0 |= FRF_SPI << FRF_SHIFT;

	/* Tx and Rx mode */
	ctrlr0 |= (priv->tmode & TMOD_MASK) << TMOD_SHIFT;

	writel(ctrlr0, &regs->ctrlr0);

	return 0;
}

static int rockchip_spi_release_bus(struct udevice *dev)
{
	struct udevice *bus = dev->parent;
	struct rockchip_spi_priv *priv = dev_get_priv(bus);

	rkspi_enable_chip(priv->regs, false);

	return 0;
}

static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen,
			   const void *dout, void *din, unsigned long flags)
{
	struct udevice *bus = dev->parent;
	struct rockchip_spi_priv *priv = dev_get_priv(bus);
	struct rockchip_spi *regs = priv->regs;
	struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
	int len = bitlen >> 3;
	const u8 *out = dout;
	u8 *in = din;
	int toread, towrite;
	int ret;

	debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__, dout, din,
	      len, flags);
	if (DEBUG_RK_SPI)
		rkspi_dump_regs(regs);

	/* Assert CS before transfer */
	if (flags & SPI_XFER_BEGIN)
		spi_cs_activate(dev, slave_plat->cs);

	while (len > 0) {
		int todo = min(len, 0xffff);

		rkspi_enable_chip(regs, false);
		writel(todo - 1, &regs->ctrlr1);
		rkspi_enable_chip(regs, true);

		toread = todo;
		towrite = todo;
		while (toread || towrite) {
			u32 status = readl(&regs->sr);

			if (towrite && !(status & SR_TF_FULL)) {
				writel(out ? *out++ : 0, regs->txdr);
				towrite--;
			}
			if (toread && !(status & SR_RF_EMPT)) {
				u32 byte = readl(regs->rxdr);

				if (in)
					*in++ = byte;
				toread--;
			}
		}
		ret = rkspi_wait_till_not_busy(regs);
		if (ret)
			break;
		len -= todo;
	}

	/* Deassert CS after transfer */
	if (flags & SPI_XFER_END)
		spi_cs_deactivate(dev, slave_plat->cs);

	rkspi_enable_chip(regs, false);

	return ret;
}

static int rockchip_spi_set_speed(struct udevice *bus, uint speed)
{
	struct rockchip_spi_priv *priv = dev_get_priv(bus);

	if (speed > ROCKCHIP_SPI_MAX_RATE)
		return -EINVAL;
	if (speed > priv->max_freq)
		speed = priv->max_freq;
	priv->speed_hz = speed;

	return 0;
}

static int rockchip_spi_set_mode(struct udevice *bus, uint mode)
{
	struct rockchip_spi_priv *priv = dev_get_priv(bus);

	priv->mode = mode;

	return 0;
}

static const struct dm_spi_ops rockchip_spi_ops = {
	.claim_bus	= rockchip_spi_claim_bus,
	.release_bus	= rockchip_spi_release_bus,
	.xfer		= rockchip_spi_xfer,
	.set_speed	= rockchip_spi_set_speed,
	.set_mode	= rockchip_spi_set_mode,
	/*
	 * cs_info is not needed, since we require all chip selects to be
	 * in the device tree explicitly
	 */
};

static const struct udevice_id rockchip_spi_ids[] = {
	{ .compatible = "rockchip,rk3288-spi" },
	{ }
};

U_BOOT_DRIVER(rockchip_spi) = {
	.name	= "rockchip_spi",
	.id	= UCLASS_SPI,
	.of_match = rockchip_spi_ids,
	.ops	= &rockchip_spi_ops,
	.ofdata_to_platdata = rockchip_spi_ofdata_to_platdata,
	.platdata_auto_alloc_size = sizeof(struct rockchip_spi_platdata),
	.priv_auto_alloc_size = sizeof(struct rockchip_spi_priv),
	.probe	= rockchip_spi_probe,
};
Commit	Line	Data
1b2fd5bf SG	1	/*
	2	* spi driver for rockchip
	3	*
	4	* (C) Copyright 2015 Google, Inc
	5	*
	6	* (C) Copyright 2008-2013 Rockchip Electronics
	7	* Peter, Software Engineering, <superpeter.cai@gmail.com>.
	8	*
	9	* SPDX-License-Identifier: GPL-2.0+
	10	*/
	11
	12	#include <common.h>
	13	#include <clk.h>
	14	#include <dm.h>
	15	#include <errno.h>
	16	#include <spi.h>
	17	#include <asm/errno.h>
	18	#include <asm/io.h>
	19	#include <asm/arch/clock.h>
	20	#include <asm/arch/periph.h>
	21	#include <dm/pinctrl.h>
	22	#include "rk_spi.h"
	23
	24	DECLARE_GLOBAL_DATA_PTR;
	25
	26	/* Change to 1 to output registers at the start of each transaction */
	27	#define DEBUG_RK_SPI 0
	28
	29	struct rockchip_spi_platdata {
1b2fd5bf SG	30	s32 frequency; /* Default clock frequency, -1 for none */
	31	fdt_addr_t base;
	32	uint deactivate_delay_us; /* Delay to wait after deactivate */
183a3a0f	33	uint activate_delay_us; /* Delay to wait after activate */
1b2fd5bf SG	34	};
	35
	36	struct rockchip_spi_priv {
	37	struct rockchip_spi *regs;
135aa950	38	struct clk clk;
1b2fd5bf SG	39	unsigned int max_freq;
1b2fd5bf SG	40	unsigned int mode;
1b2fd5bf SG	41	ulong last_transaction_us; /* Time of last transaction end */
	42	u8 bits_per_word; /* max 16 bits per word */
	43	u8 n_bytes;
	44	unsigned int speed_hz;
28a943c1	45	unsigned int last_speed_hz;
1b2fd5bf SG	46	unsigned int tmode;
	47	uint input_rate;
	48	};
	49
	50	#define SPI_FIFO_DEPTH 32
	51
	52	static void rkspi_dump_regs(struct rockchip_spi *regs)
	53	{
	54	debug("ctrl0: \t\t0x%08x\n", readl(&regs->ctrlr0));
	55	debug("ctrl1: \t\t0x%08x\n", readl(&regs->ctrlr1));
	56	debug("ssienr: \t\t0x%08x\n", readl(&regs->enr));
	57	debug("ser: \t\t0x%08x\n", readl(&regs->ser));
	58	debug("baudr: \t\t0x%08x\n", readl(&regs->baudr));
	59	debug("txftlr: \t\t0x%08x\n", readl(&regs->txftlr));
	60	debug("rxftlr: \t\t0x%08x\n", readl(&regs->rxftlr));
	61	debug("txflr: \t\t0x%08x\n", readl(&regs->txflr));
	62	debug("rxflr: \t\t0x%08x\n", readl(&regs->rxflr));
	63	debug("sr: \t\t0x%08x\n", readl(&regs->sr));
	64	debug("imr: \t\t0x%08x\n", readl(&regs->imr));
	65	debug("isr: \t\t0x%08x\n", readl(&regs->isr));
	66	debug("dmacr: \t\t0x%08x\n", readl(&regs->dmacr));
	67	debug("dmatdlr: \t0x%08x\n", readl(&regs->dmatdlr));
	68	debug("dmardlr: \t0x%08x\n", readl(&regs->dmardlr));
	69	}
	70
	71	static void rkspi_enable_chip(struct rockchip_spi *regs, bool enable)
	72	{
	73	writel(enable ? 1 : 0, &regs->enr);
	74	}
	75
	76	static void rkspi_set_clk(struct rockchip_spi_priv *priv, uint speed)
	77	{
	78	uint clk_div;
	79
	80	clk_div = clk_get_divisor(priv->input_rate, speed);
	81	debug("spi speed %u, div %u\n", speed, clk_div);
	82
	83	writel(clk_div, &priv->regs->baudr);
28a943c1	84	priv->last_speed_hz = speed;
1b2fd5bf SG	85	}
	86
	87	static int rkspi_wait_till_not_busy(struct rockchip_spi *regs)
	88	{
	89	unsigned long start;
	90
	91	start = get_timer(0);
	92	while (readl(&regs->sr) & SR_BUSY) {
	93	if (get_timer(start) > ROCKCHIP_SPI_TIMEOUT_MS) {
	94	debug("RK SPI: Status keeps busy for 1000us after a read/write!\n");
	95	return -ETIMEDOUT;
	96	}
	97	}
	98
	99	return 0;
	100	}
	101
183a3a0f	102	static void spi_cs_activate(struct udevice *dev, uint cs)
1b2fd5bf	103	{
183a3a0f SG	104	struct udevice *bus = dev->parent;
	105	struct rockchip_spi_platdata *plat = bus->platdata;
	106	struct rockchip_spi_priv *priv = dev_get_priv(bus);
	107	struct rockchip_spi *regs = priv->regs;
	108
1b2fd5bf SG	109	debug("activate cs%u\n", cs);
1b2fd5bf SG	110	writel(1 << cs, &regs->ser);
183a3a0f SG	111	if (plat->activate_delay_us)
183a3a0f SG	112	udelay(plat->activate_delay_us);
1b2fd5bf SG	113	}
1b2fd5bf SG	114
183a3a0f	115	static void spi_cs_deactivate(struct udevice *dev, uint cs)
1b2fd5bf	116	{
183a3a0f SG	117	struct udevice *bus = dev->parent;
	118	struct rockchip_spi_platdata *plat = bus->platdata;
	119	struct rockchip_spi_priv *priv = dev_get_priv(bus);
	120	struct rockchip_spi *regs = priv->regs;
	121
1b2fd5bf SG	122	debug("deactivate cs%u\n", cs);
1b2fd5bf SG	123	writel(0, &regs->ser);
183a3a0f SG	124
	125	/* Remember time of this transaction so we can honour the bus delay */
	126	if (plat->deactivate_delay_us)
	127	priv->last_transaction_us = timer_get_us();
1b2fd5bf SG	128	}
	129
	130	static int rockchip_spi_ofdata_to_platdata(struct udevice *bus)
	131	{
	132	struct rockchip_spi_platdata *plat = bus->platdata;
71037d1c	133	struct rockchip_spi_priv *priv = dev_get_priv(bus);
1b2fd5bf SG	134	const void *blob = gd->fdt_blob;
	135	int node = bus->of_offset;
	136	int ret;
	137
	138	plat->base = dev_get_addr(bus);
1b2fd5bf	139
71037d1c SG	140	ret = clk_get_by_index(bus, 0, &priv->clk);
	141	if (ret < 0) {
	142	debug("%s: Could not get clock for %s: %d\n", __func__,
	143	bus->name, ret);
	144	return ret;
	145	}
1b2fd5bf SG	146
1b2fd5bf SG	147	plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
71037d1c	148	50000000);
1b2fd5bf SG	149	plat->deactivate_delay_us = fdtdec_get_int(blob, node,
1b2fd5bf SG	150	"spi-deactivate-delay", 0);
183a3a0f SG	151	plat->activate_delay_us = fdtdec_get_int(blob, node,
183a3a0f SG	152	"spi-activate-delay", 0);
90a28470 SG	153	debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d\n",
90a28470 SG	154	__func__, (uint)plat->base, plat->frequency,
1b2fd5bf SG	155	plat->deactivate_delay_us);
	156
	157	return 0;
	158	}
	159
	160	static int rockchip_spi_probe(struct udevice *bus)
	161	{
	162	struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
	163	struct rockchip_spi_priv *priv = dev_get_priv(bus);
	164	int ret;
	165
	166	debug("%s: probe\n", __func__);
	167	priv->regs = (struct rockchip_spi *)plat->base;
	168
	169	priv->last_transaction_us = timer_get_us();
	170	priv->max_freq = plat->frequency;
1b2fd5bf SG	171
	172	/*
	173	* Use 99 MHz as our clock since it divides nicely into 594 MHz which
	174	* is the assumed speed for CLK_GENERAL.
	175	*/
135aa950	176	ret = clk_set_rate(&priv->clk, 99000000);
1b2fd5bf SG	177	if (ret < 0) {
	178	debug("%s: Failed to set clock: %d\n", __func__, ret);
	179	return ret;
	180	}
	181	priv->input_rate = ret;
	182	debug("%s: rate = %u\n", __func__, priv->input_rate);
	183	priv->bits_per_word = 8;
	184	priv->tmode = TMOD_TR; /* Tx & Rx */
	185
	186	return 0;
	187	}
	188
	189	static int rockchip_spi_claim_bus(struct udevice *dev)
	190	{
	191	struct udevice *bus = dev->parent;
1b2fd5bf SG	192	struct rockchip_spi_priv *priv = dev_get_priv(bus);
1b2fd5bf SG	193	struct rockchip_spi *regs = priv->regs;
1b2fd5bf SG	194	u8 spi_dfs, spi_tf;
1b2fd5bf SG	195	uint ctrlr0;
1b2fd5bf SG	196
	197	/* Disable the SPI hardware */
	198	rkspi_enable_chip(regs, 0);
	199
	200	switch (priv->bits_per_word) {
	201	case 8:
	202	priv->n_bytes = 1;
	203	spi_dfs = DFS_8BIT;
	204	spi_tf = HALF_WORD_OFF;
	205	break;
	206	case 16:
	207	priv->n_bytes = 2;
	208	spi_dfs = DFS_16BIT;
	209	spi_tf = HALF_WORD_ON;
	210	break;
	211	default:
	212	debug("%s: unsupported bits: %dbits\n", __func__,
	213	priv->bits_per_word);
	214	return -EPROTONOSUPPORT;
	215	}
	216
28a943c1 SG	217	if (priv->speed_hz != priv->last_speed_hz)
28a943c1 SG	218	rkspi_set_clk(priv, priv->speed_hz);
1b2fd5bf SG	219
	220	/* Operation Mode */
	221	ctrlr0 = OMOD_MASTER << OMOD_SHIFT;
	222
	223	/* Data Frame Size */
2b9fe111	224	ctrlr0 \|= spi_dfs << DFS_SHIFT;
1b2fd5bf SG	225
	226	/* set SPI mode 0..3 */
	227	if (priv->mode & SPI_CPOL)
	228	ctrlr0 \|= SCOL_HIGH << SCOL_SHIFT;
	229	if (priv->mode & SPI_CPHA)
	230	ctrlr0 \|= SCPH_TOGSTA << SCPH_SHIFT;
	231
	232	/* Chip Select Mode */
	233	ctrlr0 \|= CSM_KEEP << CSM_SHIFT;
	234
	235	/* SSN to Sclk_out delay */
	236	ctrlr0 \|= SSN_DELAY_ONE << SSN_DELAY_SHIFT;
	237
	238	/* Serial Endian Mode */
	239	ctrlr0 \|= SEM_LITTLE << SEM_SHIFT;
	240
	241	/* First Bit Mode */
	242	ctrlr0 \|= FBM_MSB << FBM_SHIFT;
	243
	244	/* Byte and Halfword Transform */
2b9fe111	245	ctrlr0 \|= spi_tf << HALF_WORD_TX_SHIFT;
1b2fd5bf SG	246
	247	/* Rxd Sample Delay */
	248	ctrlr0 \|= 0 << RXDSD_SHIFT;
	249
	250	/* Frame Format */
	251	ctrlr0 \|= FRF_SPI << FRF_SHIFT;
	252
	253	/* Tx and Rx mode */
	254	ctrlr0 \|= (priv->tmode & TMOD_MASK) << TMOD_SHIFT;
	255
	256	writel(ctrlr0, &regs->ctrlr0);
1b2fd5bf SG	257
	258	return 0;
	259	}
	260
	261	static int rockchip_spi_release_bus(struct udevice *dev)
	262	{
e15af8e2 SG	263	struct udevice *bus = dev->parent;
	264	struct rockchip_spi_priv *priv = dev_get_priv(bus);
	265
	266	rkspi_enable_chip(priv->regs, false);
	267
1b2fd5bf SG	268	return 0;
	269	}
	270
	271	static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen,
	272	const void dout, void din, unsigned long flags)
	273	{
	274	struct udevice *bus = dev->parent;
	275	struct rockchip_spi_priv *priv = dev_get_priv(bus);
	276	struct rockchip_spi *regs = priv->regs;
	277	struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
	278	int len = bitlen >> 3;
	279	const u8 *out = dout;
	280	u8 *in = din;
	281	int toread, towrite;
	282	int ret;
	283
	284	debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__, dout, din,
	285	len, flags);
	286	if (DEBUG_RK_SPI)
	287	rkspi_dump_regs(regs);
	288
	289	/* Assert CS before transfer */
	290	if (flags & SPI_XFER_BEGIN)
183a3a0f	291	spi_cs_activate(dev, slave_plat->cs);
1b2fd5bf SG	292
	293	while (len > 0) {
	294	int todo = min(len, 0xffff);
	295
e15af8e2	296	rkspi_enable_chip(regs, false);
1b2fd5bf SG	297	writel(todo - 1, &regs->ctrlr1);
	298	rkspi_enable_chip(regs, true);
	299
	300	toread = todo;
	301	towrite = todo;
	302	while (toread \|\| towrite) {
	303	u32 status = readl(&regs->sr);
	304
	305	if (towrite && !(status & SR_TF_FULL)) {
	306	writel(out ? *out++ : 0, regs->txdr);
	307	towrite--;
	308	}
	309	if (toread && !(status & SR_RF_EMPT)) {
	310	u32 byte = readl(regs->rxdr);
	311
	312	if (in)
	313	*in++ = byte;
	314	toread--;
	315	}
	316	}
	317	ret = rkspi_wait_till_not_busy(regs);
	318	if (ret)
	319	break;
	320	len -= todo;
	321	}
	322
	323	/* Deassert CS after transfer */
	324	if (flags & SPI_XFER_END)
183a3a0f	325	spi_cs_deactivate(dev, slave_plat->cs);
1b2fd5bf SG	326
	327	rkspi_enable_chip(regs, false);
	328
	329	return ret;
	330	}
	331
	332	static int rockchip_spi_set_speed(struct udevice *bus, uint speed)
	333	{
	334	struct rockchip_spi_priv *priv = dev_get_priv(bus);
	335
	336	if (speed > ROCKCHIP_SPI_MAX_RATE)
	337	return -EINVAL;
	338	if (speed > priv->max_freq)
	339	speed = priv->max_freq;
	340	priv->speed_hz = speed;
	341
	342	return 0;
	343	}
	344
	345	static int rockchip_spi_set_mode(struct udevice *bus, uint mode)
	346	{
	347	struct rockchip_spi_priv *priv = dev_get_priv(bus);
	348
	349	priv->mode = mode;
	350
	351	return 0;
	352	}
	353
	354	static const struct dm_spi_ops rockchip_spi_ops = {
	355	.claim_bus = rockchip_spi_claim_bus,
	356	.release_bus = rockchip_spi_release_bus,
	357	.xfer = rockchip_spi_xfer,
	358	.set_speed = rockchip_spi_set_speed,
	359	.set_mode = rockchip_spi_set_mode,
	360	/*
	361	* cs_info is not needed, since we require all chip selects to be
	362	* in the device tree explicitly
	363	*/
	364	};
	365
	366	static const struct udevice_id rockchip_spi_ids[] = {
	367	{ .compatible = "rockchip,rk3288-spi" },
	368	{ }
	369	};
	370
	371	U_BOOT_DRIVER(rockchip_spi) = {
	372	.name = "rockchip_spi",
	373	.id = UCLASS_SPI,
	374	.of_match = rockchip_spi_ids,
	375	.ops = &rockchip_spi_ops,
	376	.ofdata_to_platdata = rockchip_spi_ofdata_to_platdata,
	377	.platdata_auto_alloc_size = sizeof(struct rockchip_spi_platdata),
	378	.priv_auto_alloc_size = sizeof(struct rockchip_spi_priv),
	379	.probe = rockchip_spi_probe,
	380	};