[people/ms/u-boot.git] / drivers / spi / tegra20_slink.c

/*
 * NVIDIA Tegra SPI-SLINK controller
 *
 * Copyright (c) 2010-2013 NVIDIA Corporation
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <malloc.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/clock.h>
#include <asm/arch-tegra/clk_rst.h>
#include <asm/arch-tegra20/tegra20_slink.h>
#include <spi.h>
#include <fdtdec.h>

DECLARE_GLOBAL_DATA_PTR;

/* COMMAND */
#define SLINK_CMD_ENB			(1 << 31)
#define SLINK_CMD_GO			(1 << 30)
#define SLINK_CMD_M_S			(1 << 28)
#define SLINK_CMD_CK_SDA		(1 << 21)
#define SLINK_CMD_CS_POL		(1 << 13)
#define SLINK_CMD_CS_VAL		(1 << 12)
#define SLINK_CMD_CS_SOFT		(1 << 11)
#define SLINK_CMD_BIT_LENGTH		(1 << 4)
#define SLINK_CMD_BIT_LENGTH_MASK	0x0000001F
/* COMMAND2 */
#define SLINK_CMD2_TXEN			(1 << 30)
#define SLINK_CMD2_RXEN			(1 << 31)
#define SLINK_CMD2_SS_EN		(1 << 18)
#define SLINK_CMD2_SS_EN_SHIFT		18
#define SLINK_CMD2_SS_EN_MASK		0x000C0000
#define SLINK_CMD2_CS_ACTIVE_BETWEEN	(1 << 17)
/* STATUS */
#define SLINK_STAT_BSY			(1 << 31)
#define SLINK_STAT_RDY			(1 << 30)
#define SLINK_STAT_ERR			(1 << 29)
#define SLINK_STAT_RXF_FLUSH		(1 << 27)
#define SLINK_STAT_TXF_FLUSH		(1 << 26)
#define SLINK_STAT_RXF_OVF		(1 << 25)
#define SLINK_STAT_TXF_UNR		(1 << 24)
#define SLINK_STAT_RXF_EMPTY		(1 << 23)
#define SLINK_STAT_RXF_FULL		(1 << 22)
#define SLINK_STAT_TXF_EMPTY		(1 << 21)
#define SLINK_STAT_TXF_FULL		(1 << 20)
#define SLINK_STAT_TXF_OVF		(1 << 19)
#define SLINK_STAT_RXF_UNR		(1 << 18)
#define SLINK_STAT_CUR_BLKCNT		(1 << 15)
/* STATUS2 */
#define SLINK_STAT2_RXF_FULL_CNT	(1 << 16)
#define SLINK_STAT2_TXF_FULL_CNT	(1 << 0)

#define SPI_TIMEOUT		1000
#define TEGRA_SPI_MAX_FREQ	52000000

struct spi_regs {
	u32 command;	/* SLINK_COMMAND_0 register  */
	u32 command2;	/* SLINK_COMMAND2_0 reg */
	u32 status;	/* SLINK_STATUS_0 register */
	u32 reserved;	/* Reserved offset 0C */
	u32 mas_data;	/* SLINK_MAS_DATA_0 reg */
	u32 slav_data;	/* SLINK_SLAVE_DATA_0 reg */
	u32 dma_ctl;	/* SLINK_DMA_CTL_0 register */
	u32 status2;	/* SLINK_STATUS2_0 reg */
	u32 rsvd[56];	/* 0x20 to 0xFF reserved */
	u32 tx_fifo;	/* SLINK_TX_FIFO_0 reg off 100h */
	u32 rsvd2[31];	/* 0x104 to 0x17F reserved */
	u32 rx_fifo;	/* SLINK_RX_FIFO_0 reg off 180h */
};

struct tegra_spi_ctrl {
	struct spi_regs *regs;
	unsigned int freq;
	unsigned int mode;
	int periph_id;
	int valid;
};

struct tegra_spi_slave {
	struct spi_slave slave;
	struct tegra_spi_ctrl *ctrl;
};

static struct tegra_spi_ctrl spi_ctrls[CONFIG_TEGRA_SLINK_CTRLS];

static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave)
{
	return container_of(slave, struct tegra_spi_slave, slave);
}

int tegra30_spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
	if (bus >= CONFIG_TEGRA_SLINK_CTRLS || cs > 3 || !spi_ctrls[bus].valid)
		return 0;
	else
		return 1;
}

struct spi_slave *tegra30_spi_setup_slave(unsigned int bus, unsigned int cs,
		unsigned int max_hz, unsigned int mode)
{
	struct tegra_spi_slave *spi;

	debug("%s: bus: %u, cs: %u, max_hz: %u, mode: %u\n", __func__,
		bus, cs, max_hz, mode);

	if (!spi_cs_is_valid(bus, cs)) {
		printf("SPI error: unsupported bus %d / chip select %d\n",
		       bus, cs);
		return NULL;
	}

	if (max_hz > TEGRA_SPI_MAX_FREQ) {
		printf("SPI error: unsupported frequency %d Hz. Max frequency"
			" is %d Hz\n", max_hz, TEGRA_SPI_MAX_FREQ);
		return NULL;
	}

	spi = spi_alloc_slave(struct tegra_spi_slave, bus, cs);
	if (!spi) {
		printf("SPI error: malloc of SPI structure failed\n");
		return NULL;
	}
	spi->ctrl = &spi_ctrls[bus];
	if (!spi->ctrl) {
		printf("SPI error: could not find controller for bus %d\n",
		       bus);
		return NULL;
	}

	if (max_hz < spi->ctrl->freq) {
		debug("%s: limiting frequency from %u to %u\n", __func__,
		      spi->ctrl->freq, max_hz);
		spi->ctrl->freq = max_hz;
	}
	spi->ctrl->mode = mode;

	return &spi->slave;
}

void tegra30_spi_free_slave(struct spi_slave *slave)
{
	struct tegra_spi_slave *spi = to_tegra_spi(slave);

	free(spi);
}

int tegra30_spi_init(int *node_list, int count)
{
	struct tegra_spi_ctrl *ctrl;
	int i;
	int node = 0;
	int found = 0;

	for (i = 0; i < count; i++) {
		ctrl = &spi_ctrls[i];
		node = node_list[i];

		ctrl->regs = (struct spi_regs *)fdtdec_get_addr(gd->fdt_blob,
								node, "reg");
		if ((fdt_addr_t)ctrl->regs == FDT_ADDR_T_NONE) {
			debug("%s: no slink register found\n", __func__);
			continue;
		}
		ctrl->freq = fdtdec_get_int(gd->fdt_blob, node,
					    "spi-max-frequency", 0);
		if (!ctrl->freq) {
			debug("%s: no slink max frequency found\n", __func__);
			continue;
		}

		ctrl->periph_id = clock_decode_periph_id(gd->fdt_blob, node);
		if (ctrl->periph_id == PERIPH_ID_NONE) {
			debug("%s: could not decode periph id\n", __func__);
			continue;
		}
		ctrl->valid = 1;
		found = 1;

		debug("%s: found controller at %p, freq = %u, periph_id = %d\n",
		      __func__, ctrl->regs, ctrl->freq, ctrl->periph_id);
	}
	return !found;
}

int tegra30_spi_claim_bus(struct spi_slave *slave)
{
	struct tegra_spi_slave *spi = to_tegra_spi(slave);
	struct spi_regs *regs = spi->ctrl->regs;
	u32 reg;

	/* Change SPI clock to correct frequency, PLLP_OUT0 source */
	clock_start_periph_pll(spi->ctrl->periph_id, CLOCK_ID_PERIPH,
			       spi->ctrl->freq);

	/* Clear stale status here */
	reg = SLINK_STAT_RDY | SLINK_STAT_RXF_FLUSH | SLINK_STAT_TXF_FLUSH | \
		SLINK_STAT_RXF_UNR | SLINK_STAT_TXF_OVF;
	writel(reg, &regs->status);
	debug("%s: STATUS = %08x\n", __func__, readl(&regs->status));

	/* Set master mode and sw controlled CS */
	reg = readl(&regs->command);
	reg |= SLINK_CMD_M_S | SLINK_CMD_CS_SOFT;
	writel(reg, &regs->command);
	debug("%s: COMMAND = %08x\n", __func__, readl(&regs->command));

	return 0;
}

void tegra30_spi_cs_activate(struct spi_slave *slave)
{
	struct tegra_spi_slave *spi = to_tegra_spi(slave);
	struct spi_regs *regs = spi->ctrl->regs;

	/* CS is negated on Tegra, so drive a 1 to get a 0 */
	setbits_le32(&regs->command, SLINK_CMD_CS_VAL);
}

void tegra30_spi_cs_deactivate(struct spi_slave *slave)
{
	struct tegra_spi_slave *spi = to_tegra_spi(slave);
	struct spi_regs *regs = spi->ctrl->regs;

	/* CS is negated on Tegra, so drive a 0 to get a 1 */
	clrbits_le32(&regs->command, SLINK_CMD_CS_VAL);
}

int tegra30_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
		const void *data_out, void *data_in, unsigned long flags)
{
	struct tegra_spi_slave *spi = to_tegra_spi(slave);
	struct spi_regs *regs = spi->ctrl->regs;
	u32 reg, tmpdout, tmpdin = 0;
	const u8 *dout = data_out;
	u8 *din = data_in;
	int num_bytes;
	int ret;

	debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
	      __func__, slave->bus, slave->cs, dout, din, bitlen);
	if (bitlen % 8)
		return -1;
	num_bytes = bitlen / 8;

	ret = 0;

	reg = readl(&regs->status);
	writel(reg, &regs->status);	/* Clear all SPI events via R/W */
	debug("%s entry: STATUS = %08x\n", __func__, reg);

	reg = readl(&regs->status2);
	writel(reg, &regs->status2);	/* Clear all STATUS2 events via R/W */
	debug("%s entry: STATUS2 = %08x\n", __func__, reg);

	debug("%s entry: COMMAND = %08x\n", __func__, readl(&regs->command));

	clrsetbits_le32(&regs->command2, SLINK_CMD2_SS_EN_MASK,
			SLINK_CMD2_TXEN | SLINK_CMD2_RXEN |
			(slave->cs << SLINK_CMD2_SS_EN_SHIFT));
	debug("%s entry: COMMAND2 = %08x\n", __func__, readl(&regs->command2));

	if (flags & SPI_XFER_BEGIN)
		spi_cs_activate(slave);

	/* handle data in 32-bit chunks */
	while (num_bytes > 0) {
		int bytes;
		int is_read = 0;
		int tm, i;

		tmpdout = 0;
		bytes = (num_bytes > 4) ?  4 : num_bytes;

		if (dout != NULL) {
			for (i = 0; i < bytes; ++i)
				tmpdout = (tmpdout << 8) | dout[i];
			dout += bytes;
		}

		num_bytes -= bytes;

		clrsetbits_le32(&regs->command, SLINK_CMD_BIT_LENGTH_MASK,
				bytes * 8 - 1);
		writel(tmpdout, &regs->tx_fifo);
		setbits_le32(&regs->command, SLINK_CMD_GO);

		/*
		 * Wait for SPI transmit FIFO to empty, or to time out.
		 * The RX FIFO status will be read and cleared last
		 */
		for (tm = 0, is_read = 0; tm < SPI_TIMEOUT; ++tm) {
			u32 status;

			status = readl(&regs->status);

			/* We can exit when we've had both RX and TX activity */
			if (is_read && (status & SLINK_STAT_TXF_EMPTY))
				break;

			if ((status & (SLINK_STAT_BSY | SLINK_STAT_RDY)) !=
					SLINK_STAT_RDY)
				tm++;

			else if (!(status & SLINK_STAT_RXF_EMPTY)) {
				tmpdin = readl(&regs->rx_fifo);
				is_read = 1;

				/* swap bytes read in */
				if (din != NULL) {
					for (i = bytes - 1; i >= 0; --i) {
						din[i] = tmpdin & 0xff;
						tmpdin >>= 8;
					}
					din += bytes;
				}
			}
		}

		if (tm >= SPI_TIMEOUT)
			ret = tm;

		/* clear ACK RDY, etc. bits */
		writel(readl(&regs->status), &regs->status);
	}

	if (flags & SPI_XFER_END)
		spi_cs_deactivate(slave);

	debug("%s: transfer ended. Value=%08x, status = %08x\n",
	      __func__, tmpdin, readl(&regs->status));

	if (ret) {
		printf("%s: timeout during SPI transfer, tm %d\n",
		       __func__, ret);
		return -1;
	}

	return 0;
}
Commit	Line	Data
b19f5749 AM	1	/*
	2	* NVIDIA Tegra SPI-SLINK controller
	3	*
	4	* Copyright (c) 2010-2013 NVIDIA Corporation
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This software is licensed under the terms of the GNU General Public
	10	* License version 2, as published by the Free Software Foundation, and
	11	* may be copied, distributed, and modified under those terms.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <common.h>
	25	#include <malloc.h>
	26	#include <asm/io.h>
	27	#include <asm/gpio.h>
	28	#include <asm/arch/clock.h>
	29	#include <asm/arch-tegra/clk_rst.h>
ff1da6fb	30	#include <asm/arch-tegra20/tegra20_slink.h>
b19f5749 AM	31	#include <spi.h>
	32	#include <fdtdec.h>
	33
	34	DECLARE_GLOBAL_DATA_PTR;
	35
7a49ba6e AM	36	/* COMMAND */
	37	#define SLINK_CMD_ENB (1 << 31)
	38	#define SLINK_CMD_GO (1 << 30)
	39	#define SLINK_CMD_M_S (1 << 28)
	40	#define SLINK_CMD_CK_SDA (1 << 21)
	41	#define SLINK_CMD_CS_POL (1 << 13)
	42	#define SLINK_CMD_CS_VAL (1 << 12)
	43	#define SLINK_CMD_CS_SOFT (1 << 11)
	44	#define SLINK_CMD_BIT_LENGTH (1 << 4)
	45	#define SLINK_CMD_BIT_LENGTH_MASK 0x0000001F
	46	/* COMMAND2 */
	47	#define SLINK_CMD2_TXEN (1 << 30)
	48	#define SLINK_CMD2_RXEN (1 << 31)
	49	#define SLINK_CMD2_SS_EN (1 << 18)
	50	#define SLINK_CMD2_SS_EN_SHIFT 18
	51	#define SLINK_CMD2_SS_EN_MASK 0x000C0000
	52	#define SLINK_CMD2_CS_ACTIVE_BETWEEN (1 << 17)
	53	/* STATUS */
	54	#define SLINK_STAT_BSY (1 << 31)
	55	#define SLINK_STAT_RDY (1 << 30)
	56	#define SLINK_STAT_ERR (1 << 29)
	57	#define SLINK_STAT_RXF_FLUSH (1 << 27)
	58	#define SLINK_STAT_TXF_FLUSH (1 << 26)
	59	#define SLINK_STAT_RXF_OVF (1 << 25)
	60	#define SLINK_STAT_TXF_UNR (1 << 24)
	61	#define SLINK_STAT_RXF_EMPTY (1 << 23)
	62	#define SLINK_STAT_RXF_FULL (1 << 22)
	63	#define SLINK_STAT_TXF_EMPTY (1 << 21)
	64	#define SLINK_STAT_TXF_FULL (1 << 20)
	65	#define SLINK_STAT_TXF_OVF (1 << 19)
	66	#define SLINK_STAT_RXF_UNR (1 << 18)
	67	#define SLINK_STAT_CUR_BLKCNT (1 << 15)
	68	/* STATUS2 */
	69	#define SLINK_STAT2_RXF_FULL_CNT (1 << 16)
	70	#define SLINK_STAT2_TXF_FULL_CNT (1 << 0)
	71
	72	#define SPI_TIMEOUT 1000
	73	#define TEGRA_SPI_MAX_FREQ 52000000
	74
	75	struct spi_regs {
	76	u32 command; /* SLINK_COMMAND_0 register */
	77	u32 command2; /* SLINK_COMMAND2_0 reg */
	78	u32 status; /* SLINK_STATUS_0 register */
	79	u32 reserved; /* Reserved offset 0C */
	80	u32 mas_data; /* SLINK_MAS_DATA_0 reg */
	81	u32 slav_data; /* SLINK_SLAVE_DATA_0 reg */
	82	u32 dma_ctl; /* SLINK_DMA_CTL_0 register */
	83	u32 status2; /* SLINK_STATUS2_0 reg */
	84	u32 rsvd[56]; /* 0x20 to 0xFF reserved */
	85	u32 tx_fifo; /* SLINK_TX_FIFO_0 reg off 100h */
	86	u32 rsvd2[31]; /* 0x104 to 0x17F reserved */
	87	u32 rx_fifo; /* SLINK_RX_FIFO_0 reg off 180h */
	88	};
	89
b19f5749	90	struct tegra_spi_ctrl {
7a49ba6e	91	struct spi_regs *regs;
b19f5749 AM	92	unsigned int freq;
	93	unsigned int mode;
	94	int periph_id;
	95	int valid;
	96	};
	97
	98	struct tegra_spi_slave {
	99	struct spi_slave slave;
	100	struct tegra_spi_ctrl *ctrl;
	101	};
	102
	103	static struct tegra_spi_ctrl spi_ctrls[CONFIG_TEGRA_SLINK_CTRLS];
	104
	105	static inline struct tegra_spi_slave to_tegra_spi(struct spi_slave slave)
	106	{
	107	return container_of(slave, struct tegra_spi_slave, slave);
	108	}
	109
78f47b73	110	int tegra30_spi_cs_is_valid(unsigned int bus, unsigned int cs)
b19f5749 AM	111	{
	112	if (bus >= CONFIG_TEGRA_SLINK_CTRLS \|\| cs > 3 \|\| !spi_ctrls[bus].valid)
	113	return 0;
	114	else
	115	return 1;
	116	}
	117
78f47b73	118	struct spi_slave *tegra30_spi_setup_slave(unsigned int bus, unsigned int cs,
b19f5749 AM	119	unsigned int max_hz, unsigned int mode)
	120	{
	121	struct tegra_spi_slave *spi;
	122
	123	debug("%s: bus: %u, cs: %u, max_hz: %u, mode: %u\n", __func__,
	124	bus, cs, max_hz, mode);
	125
	126	if (!spi_cs_is_valid(bus, cs)) {
	127	printf("SPI error: unsupported bus %d / chip select %d\n",
	128	bus, cs);
	129	return NULL;
	130	}
	131
	132	if (max_hz > TEGRA_SPI_MAX_FREQ) {
	133	printf("SPI error: unsupported frequency %d Hz. Max frequency"
	134	" is %d Hz\n", max_hz, TEGRA_SPI_MAX_FREQ);
	135	return NULL;
	136	}
	137
d3504fee	138	spi = spi_alloc_slave(struct tegra_spi_slave, bus, cs);
b19f5749 AM	139	if (!spi) {
	140	printf("SPI error: malloc of SPI structure failed\n");
	141	return NULL;
	142	}
b19f5749 AM	143	spi->ctrl = &spi_ctrls[bus];
	144	if (!spi->ctrl) {
	145	printf("SPI error: could not find controller for bus %d\n",
	146	bus);
	147	return NULL;
	148	}
	149
	150	if (max_hz < spi->ctrl->freq) {
	151	debug("%s: limiting frequency from %u to %u\n", __func__,
	152	spi->ctrl->freq, max_hz);
	153	spi->ctrl->freq = max_hz;
	154	}
	155	spi->ctrl->mode = mode;
	156
	157	return &spi->slave;
	158	}
	159
78f47b73	160	void tegra30_spi_free_slave(struct spi_slave *slave)
b19f5749 AM	161	{
	162	struct tegra_spi_slave *spi = to_tegra_spi(slave);
	163
	164	free(spi);
	165	}
	166
78f47b73	167	int tegra30_spi_init(int *node_list, int count)
b19f5749 AM	168	{
	169	struct tegra_spi_ctrl *ctrl;
	170	int i;
b19f5749	171	int node = 0;
78f47b73	172	int found = 0;
b19f5749	173
b19f5749 AM	174	for (i = 0; i < count; i++) {
	175	ctrl = &spi_ctrls[i];
	176	node = node_list[i];
	177
7a49ba6e AM	178	ctrl->regs = (struct spi_regs *)fdtdec_get_addr(gd->fdt_blob,
7a49ba6e AM	179	node, "reg");
b19f5749 AM	180	if ((fdt_addr_t)ctrl->regs == FDT_ADDR_T_NONE) {
	181	debug("%s: no slink register found\n", __func__);
	182	continue;
	183	}
	184	ctrl->freq = fdtdec_get_int(gd->fdt_blob, node,
	185	"spi-max-frequency", 0);
	186	if (!ctrl->freq) {
	187	debug("%s: no slink max frequency found\n", __func__);
	188	continue;
	189	}
	190
	191	ctrl->periph_id = clock_decode_periph_id(gd->fdt_blob, node);
	192	if (ctrl->periph_id == PERIPH_ID_NONE) {
	193	debug("%s: could not decode periph id\n", __func__);
	194	continue;
	195	}
	196	ctrl->valid = 1;
78f47b73	197	found = 1;
b19f5749 AM	198
	199	debug("%s: found controller at %p, freq = %u, periph_id = %d\n",
	200	__func__, ctrl->regs, ctrl->freq, ctrl->periph_id);
	201	}
78f47b73	202	return !found;
b19f5749 AM	203	}
b19f5749 AM	204
78f47b73	205	int tegra30_spi_claim_bus(struct spi_slave *slave)
b19f5749 AM	206	{
b19f5749 AM	207	struct tegra_spi_slave *spi = to_tegra_spi(slave);
7a49ba6e	208	struct spi_regs *regs = spi->ctrl->regs;
b19f5749 AM	209	u32 reg;
	210
	211	/* Change SPI clock to correct frequency, PLLP_OUT0 source */
	212	clock_start_periph_pll(spi->ctrl->periph_id, CLOCK_ID_PERIPH,
	213	spi->ctrl->freq);
	214
	215	/* Clear stale status here */
	216	reg = SLINK_STAT_RDY \| SLINK_STAT_RXF_FLUSH \| SLINK_STAT_TXF_FLUSH \| \
	217	SLINK_STAT_RXF_UNR \| SLINK_STAT_TXF_OVF;
	218	writel(reg, &regs->status);
	219	debug("%s: STATUS = %08x\n", __func__, readl(&regs->status));
	220
	221	/* Set master mode and sw controlled CS */
	222	reg = readl(&regs->command);
	223	reg \|= SLINK_CMD_M_S \| SLINK_CMD_CS_SOFT;
	224	writel(reg, &regs->command);
	225	debug("%s: COMMAND = %08x\n", __func__, readl(&regs->command));
	226
	227	return 0;
	228	}
	229
78f47b73	230	void tegra30_spi_cs_activate(struct spi_slave *slave)
b19f5749 AM	231	{
b19f5749 AM	232	struct tegra_spi_slave *spi = to_tegra_spi(slave);
7a49ba6e	233	struct spi_regs *regs = spi->ctrl->regs;
b19f5749 AM	234
	235	/* CS is negated on Tegra, so drive a 1 to get a 0 */
	236	setbits_le32(&regs->command, SLINK_CMD_CS_VAL);
	237	}
	238
78f47b73	239	void tegra30_spi_cs_deactivate(struct spi_slave *slave)
b19f5749 AM	240	{
b19f5749 AM	241	struct tegra_spi_slave *spi = to_tegra_spi(slave);
7a49ba6e	242	struct spi_regs *regs = spi->ctrl->regs;
b19f5749 AM	243
	244	/* CS is negated on Tegra, so drive a 0 to get a 1 */
	245	clrbits_le32(&regs->command, SLINK_CMD_CS_VAL);
	246	}
	247
78f47b73	248	int tegra30_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
b19f5749 AM	249	const void data_out, void data_in, unsigned long flags)
	250	{
	251	struct tegra_spi_slave *spi = to_tegra_spi(slave);
7a49ba6e	252	struct spi_regs *regs = spi->ctrl->regs;
b19f5749 AM	253	u32 reg, tmpdout, tmpdin = 0;
	254	const u8 *dout = data_out;
	255	u8 *din = data_in;
	256	int num_bytes;
	257	int ret;
	258
	259	debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
	260	__func__, slave->bus, slave->cs, dout, din, bitlen);
	261	if (bitlen % 8)
	262	return -1;
	263	num_bytes = bitlen / 8;
	264
	265	ret = 0;
	266
	267	reg = readl(&regs->status);
	268	writel(reg, &regs->status); /* Clear all SPI events via R/W */
	269	debug("%s entry: STATUS = %08x\n", __func__, reg);
	270
	271	reg = readl(&regs->status2);
	272	writel(reg, &regs->status2); /* Clear all STATUS2 events via R/W */
	273	debug("%s entry: STATUS2 = %08x\n", __func__, reg);
	274
	275	debug("%s entry: COMMAND = %08x\n", __func__, readl(&regs->command));
	276
	277	clrsetbits_le32(&regs->command2, SLINK_CMD2_SS_EN_MASK,
	278	SLINK_CMD2_TXEN \| SLINK_CMD2_RXEN \|
	279	(slave->cs << SLINK_CMD2_SS_EN_SHIFT));
	280	debug("%s entry: COMMAND2 = %08x\n", __func__, readl(&regs->command2));
	281
	282	if (flags & SPI_XFER_BEGIN)
	283	spi_cs_activate(slave);
	284
	285	/* handle data in 32-bit chunks */
	286	while (num_bytes > 0) {
	287	int bytes;
	288	int is_read = 0;
	289	int tm, i;
	290
	291	tmpdout = 0;
	292	bytes = (num_bytes > 4) ? 4 : num_bytes;
	293
	294	if (dout != NULL) {
	295	for (i = 0; i < bytes; ++i)
	296	tmpdout = (tmpdout << 8) \| dout[i];
	297	dout += bytes;
	298	}
	299
	300	num_bytes -= bytes;
	301
	302	clrsetbits_le32(&regs->command, SLINK_CMD_BIT_LENGTH_MASK,
	303	bytes * 8 - 1);
	304	writel(tmpdout, &regs->tx_fifo);
	305	setbits_le32(&regs->command, SLINK_CMD_GO);
	306
	307	/*
	308	* Wait for SPI transmit FIFO to empty, or to time out.
	309	* The RX FIFO status will be read and cleared last
	310	*/
	311	for (tm = 0, is_read = 0; tm < SPI_TIMEOUT; ++tm) {
	312	u32 status;
	313
	314	status = readl(&regs->status);
	315
	316	/* We can exit when we've had both RX and TX activity */
317	if (is_read && (status & SLINK_STAT_TXF_EMPTY))
318	break;
319
320	if ((status & (SLINK_STAT_BSY \| SLINK_STAT_RDY)) !=
321	SLINK_STAT_RDY)
322	tm++;
323
324	else if (!(status & SLINK_STAT_RXF_EMPTY)) {
325	tmpdin = readl(&regs->rx_fifo);
326	is_read = 1;
327
328	/* swap bytes read in */
329	if (din != NULL) {
330	for (i = bytes - 1; i >= 0; --i) {
331	din[i] = tmpdin & 0xff;
332	tmpdin >>= 8;
333	}
334	din += bytes;
335	}
336	}
337	}
338
339	if (tm >= SPI_TIMEOUT)
340	ret = tm;
341
342	/* clear ACK RDY, etc. bits */
343	writel(readl(&regs->status), &regs->status);
344	}
345
346	if (flags & SPI_XFER_END)
347	spi_cs_deactivate(slave);
348
349	debug("%s: transfer ended. Value=%08x, status = %08x\n",
350	__func__, tmpdin, readl(&regs->status));
351
352	if (ret) {
353	printf("%s: timeout during SPI transfer, tm %d\n",
354	__func__, ret);
355	return -1;
356	}
357
358	return 0;
359	}