[people/ms/u-boot.git] / drivers / timer / atcpit100_timer.c

/*
 * Andestech ATCPIT100 timer driver
 *
 * (C) Copyright 2016
 * Rick Chen, NDS32 Software Engineering, rick@andestech.com
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <timer.h>
#include <linux/io.h>

DECLARE_GLOBAL_DATA_PTR;

#define REG32_TMR(x)	(*(u32 *)	((plat->regs) + (x>>2)))

/*
 * Definition of register offsets
 */

/* ID and Revision Register */
#define ID_REV		0x0

/* Configuration Register */
#define CFG		0x10

/* Interrupt Enable Register */
#define INT_EN		0x14
#define CH_INT_EN(c , i)	((1<<i)<<(4*c))

/* Interrupt Status Register */
#define INT_STA		0x18
#define CH_INT_STA(c , i)	((1<<i)<<(4*c))

/* Channel Enable Register */
#define CH_EN		0x1C
#define CH_TMR_EN(c , t)	((1<<t)<<(4*c))

/* Ch n Control REgister */
#define CH_CTL(n)	(0x20+0x10*n)
/* Channel clock source , bit 3 , 0:External clock , 1:APB clock */
#define APB_CLK		(1<<3)
/* Channel mode , bit 0~2 */
#define TMR_32		1
#define TMR_16		2
#define TMR_8		3
#define PWM		4

#define CH_REL(n)	(0x24+0x10*n)
#define CH_CNT(n)	(0x28+0x10*n)

struct atctmr_timer_regs {
	u32	id_rev;		/* 0x00 */
	u32	reservd[3];	/* 0x04 ~ 0x0c */
	u32	cfg;		/* 0x10 */
	u32	int_en;		/* 0x14 */
	u32	int_st;		/* 0x18 */
	u32	ch_en;		/* 0x1c */
	u32	ch0_ctrl;	/* 0x20 */
	u32	ch0_reload;	/* 0x24 */
	u32	ch0_cntr;	/* 0x28 */
	u32	reservd1;	/* 0x2c */
	u32	ch1_ctrl;	/* 0x30 */
	u32	ch1_reload;	/* 0x34 */
	u32	int_mask;	/* 0x38 */
};

struct atcpit_timer_platdata {
	u32 *regs;
};

static int atcpit_timer_get_count(struct udevice *dev, u64 *count)
{
	struct atcpit_timer_platdata *plat = dev_get_platdata(dev);
	u32 val;
	val = ~(REG32_TMR(CH_CNT(1))+0xffffffff);
	*count = timer_conv_64(val);
	return 0;
}

static int atcpit_timer_probe(struct udevice *dev)
{
	struct atcpit_timer_platdata *plat = dev_get_platdata(dev);
	REG32_TMR(CH_REL(1)) = 0xffffffff;
	REG32_TMR(CH_CTL(1)) = APB_CLK|TMR_32;
	REG32_TMR(CH_EN) |= CH_TMR_EN(1 , 0);
	return 0;
}

static int atcpit_timer_ofdata_to_platdata(struct udevice *dev)
{
	struct atcpit_timer_platdata *plat = dev_get_platdata(dev);
	plat->regs = map_physmem(devfdt_get_addr(dev) , 0x100 , MAP_NOCACHE);
	return 0;
}

static const struct timer_ops atcpit_timer_ops = {
	.get_count = atcpit_timer_get_count,
};

static const struct udevice_id atcpit_timer_ids[] = {
	{ .compatible = "andestech,atcpit100" },
	{}
};

U_BOOT_DRIVER(atcpit100_timer) = {
	.name	= "atcpit100_timer",
	.id	= UCLASS_TIMER,
	.of_match = atcpit_timer_ids,
	.ofdata_to_platdata = atcpit_timer_ofdata_to_platdata,
	.platdata_auto_alloc_size = sizeof(struct atcpit_timer_platdata),
	.probe = atcpit_timer_probe,
	.ops	= &atcpit_timer_ops,
	.flags = DM_FLAG_PRE_RELOC,
};
Commit	Line	Data
b841b6e9	1	/*
	2	* Andestech ATCPIT100 timer driver
	3	*
	4	* (C) Copyright 2016
	5	* Rick Chen, NDS32 Software Engineering, rick@andestech.com
	6	*
	7	* SPDX-License-Identifier: GPL-2.0+
	8	*/
	9	#include <common.h>
	10	#include <dm.h>
	11	#include <errno.h>
	12	#include <timer.h>
	13	#include <linux/io.h>
	14
	15	DECLARE_GLOBAL_DATA_PTR;
	16
0e920ef0	17	#define REG32_TMR(x) ((u32 ) ((plat->regs) + (x>>2)))
b841b6e9	18
	19	/*
	20	* Definition of register offsets
	21	*/
	22
	23	/* ID and Revision Register */
	24	#define ID_REV 0x0
	25
	26	/* Configuration Register */
	27	#define CFG 0x10
	28
	29	/* Interrupt Enable Register */
	30	#define INT_EN 0x14
	31	#define CH_INT_EN(c , i) ((1<<i)<<(4*c))
	32
	33	/* Interrupt Status Register */
	34	#define INT_STA 0x18
	35	#define CH_INT_STA(c , i) ((1<<i)<<(4*c))
	36
	37	/* Channel Enable Register */
	38	#define CH_EN 0x1C
	39	#define CH_TMR_EN(c , t) ((1<<t)<<(4*c))
	40
	41	/* Ch n Control REgister */
	42	#define CH_CTL(n) (0x20+0x10*n)
	43	/* Channel clock source , bit 3 , 0:External clock , 1:APB clock */
	44	#define APB_CLK (1<<3)
	45	/* Channel mode , bit 0~2 */
	46	#define TMR_32 1
	47	#define TMR_16 2
	48	#define TMR_8 3
	49	#define PWM 4
	50
	51	#define CH_REL(n) (0x24+0x10*n)
	52	#define CH_CNT(n) (0x28+0x10*n)
	53
	54	struct atctmr_timer_regs {
	55	u32 id_rev; /* 0x00 */
	56	u32 reservd[3]; /* 0x04 ~ 0x0c */
	57	u32 cfg; /* 0x10 */
	58	u32 int_en; /* 0x14 */
	59	u32 int_st; /* 0x18 */
	60	u32 ch_en; /* 0x1c */
	61	u32 ch0_ctrl; /* 0x20 */
	62	u32 ch0_reload; /* 0x24 */
	63	u32 ch0_cntr; /* 0x28 */
	64	u32 reservd1; /* 0x2c */
	65	u32 ch1_ctrl; /* 0x30 */
	66	u32 ch1_reload; /* 0x34 */
	67	u32 int_mask; /* 0x38 */
	68	};
	69
033d4081	70	struct atcpit_timer_platdata {
0e920ef0	71	u32 *regs;
b841b6e9	72	};
b841b6e9	73
033d4081	74	static int atcpit_timer_get_count(struct udevice dev, u64 count)
b841b6e9	75	{
c6c85dc8	76	struct atcpit_timer_platdata *plat = dev_get_platdata(dev);
b841b6e9	77	u32 val;
	78	val = ~(REG32_TMR(CH_CNT(1))+0xffffffff);
	79	*count = timer_conv_64(val);
	80	return 0;
	81	}
	82
033d4081	83	static int atcpit_timer_probe(struct udevice *dev)
b841b6e9	84	{
c6c85dc8	85	struct atcpit_timer_platdata *plat = dev_get_platdata(dev);
b841b6e9	86	REG32_TMR(CH_REL(1)) = 0xffffffff;
	87	REG32_TMR(CH_CTL(1)) = APB_CLK\|TMR_32;
	88	REG32_TMR(CH_EN) \|= CH_TMR_EN(1 , 0);
	89	return 0;
	90	}
	91
033d4081	92	static int atcpit_timer_ofdata_to_platdata(struct udevice *dev)
b841b6e9	93	{
033d4081	94	struct atcpit_timer_platdata *plat = dev_get_platdata(dev);
a821c4af	95	plat->regs = map_physmem(devfdt_get_addr(dev) , 0x100 , MAP_NOCACHE);
b841b6e9	96	return 0;
	97	}
	98
033d4081 RC	99	static const struct timer_ops atcpit_timer_ops = {
033d4081 RC	100	.get_count = atcpit_timer_get_count,
b841b6e9	101	};
b841b6e9	102
033d4081	103	static const struct udevice_id atcpit_timer_ids[] = {
b841b6e9	104	{ .compatible = "andestech,atcpit100" },
	105	{}
	106	};
	107
033d4081 RC	108	U_BOOT_DRIVER(atcpit100_timer) = {
033d4081 RC	109	.name = "atcpit100_timer",
b841b6e9	110	.id = UCLASS_TIMER,
033d4081 RC	111	.of_match = atcpit_timer_ids,
	112	.ofdata_to_platdata = atcpit_timer_ofdata_to_platdata,
	113	.platdata_auto_alloc_size = sizeof(struct atcpit_timer_platdata),
	114	.probe = atcpit_timer_probe,
	115	.ops = &atcpit_timer_ops,
b841b6e9	116	.flags = DM_FLAG_PRE_RELOC,
b841b6e9	117	};