[people/ms/u-boot.git] / drivers / tsec.h

/*
 *  tsec.h
 *
 *  Driver for the Motorola Triple Speed Ethernet Controller
 *
 *  This software may be used and distributed according to the
 *  terms of the GNU Public License, Version 2, incorporated
 *  herein by reference.
 *
 * Copyright 2004 Freescale Semiconductor.
 * (C) Copyright 2003, Motorola, Inc.
 * maintained by Xianghua Xiao (x.xiao@motorola.com)
 * author Andy Fleming
 *
 */

#ifndef __TSEC_H
#define __TSEC_H

#include <net.h>
#include <config.h>

#ifndef CFG_TSEC1_OFFSET
    #define CFG_TSEC1_OFFSET	(0x24000)
#endif

#define TSEC_SIZE	0x01000

/* FIXME:  Should these be pushed back to 83xx and 85xx config files? */
#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
    #define TSEC_BASE_ADDR	(CFG_IMMR + CFG_TSEC1_OFFSET)
#elif defined(CONFIG_MPC83XX)
    #define TSEC_BASE_ADDR	(CFG_IMMR + CFG_TSEC1_OFFSET)
#endif


#define MAC_ADDR_LEN 6

/* #define TSEC_TIMEOUT 	1000000 */
#define TSEC_TIMEOUT 1000
#define TOUT_LOOP 	1000000

#define PHY_AUTONEGOTIATE_TIMEOUT	5000 /* in ms */

/* MAC register bits */
#define MACCFG1_SOFT_RESET	0x80000000
#define MACCFG1_RESET_RX_MC	0x00080000
#define MACCFG1_RESET_TX_MC	0x00040000
#define MACCFG1_RESET_RX_FUN	0x00020000
#define	MACCFG1_RESET_TX_FUN	0x00010000
#define MACCFG1_LOOPBACK	0x00000100
#define MACCFG1_RX_FLOW		0x00000020
#define MACCFG1_TX_FLOW		0x00000010
#define MACCFG1_SYNCD_RX_EN	0x00000008
#define MACCFG1_RX_EN		0x00000004
#define MACCFG1_SYNCD_TX_EN	0x00000002
#define MACCFG1_TX_EN		0x00000001

#define MACCFG2_INIT_SETTINGS	0x00007205
#define MACCFG2_FULL_DUPLEX	0x00000001
#define MACCFG2_IF              0x00000300
#define MACCFG2_GMII		0x00000200
#define MACCFG2_MII             0x00000100

#define ECNTRL_INIT_SETTINGS	0x00001000
#define ECNTRL_TBI_MODE         0x00000020
#define ECNTRL_R100		0x00000008

#define miim_end -2
#define miim_read -1

#define TBIPA_VALUE		0x1f
#define MIIMCFG_INIT_VALUE	0x00000003
#define MIIMCFG_RESET		0x80000000

#define MIIMIND_BUSY            0x00000001
#define MIIMIND_NOTVALID        0x00000004

#define MIIM_CONTROL            0x00
#define MIIM_CONTROL_RESET	0x00009140
#define MIIM_CONTROL_INIT       0x00001140
#define MIIM_CONTROL_RESTART    0x00001340
#define MIIM_ANEN               0x00001000

#define MIIM_CR                 0x00
#define MIIM_CR_RST		0x00008000
#define MIIM_CR_INIT	        0x00001000

#define MIIM_STATUS		0x1
#define MIIM_STATUS_AN_DONE 	0x00000020
#define MIIM_STATUS_LINK	0x0004
#define PHY_BMSR_AUTN_ABLE	0x0008
#define PHY_BMSR_AUTN_COMP	0x0020

#define MIIM_PHYIR1		0x2
#define MIIM_PHYIR2		0x3

#define MIIM_ANAR		0x4
#define MIIM_ANAR_INIT		0x1e1

#define MIIM_TBI_ANLPBPA	0x5
#define MIIM_TBI_ANLPBPA_HALF	0x00000040
#define MIIM_TBI_ANLPBPA_FULL	0x00000020

#define MIIM_TBI_ANEX		0x6
#define MIIM_TBI_ANEX_NP	0x00000004
#define MIIM_TBI_ANEX_PRX	0x00000002

#define MIIM_GBIT_CONTROL	0x9
#define MIIM_GBIT_CONTROL_INIT	0xe00

/* Broadcom BCM54xx -- taken from linux sungem_phy */
#define MIIM_BCM54xx_AUXSTATUS			0x19
#define MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK	0x0700
#define MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT	8

/* Cicada Auxiliary Control/Status Register */
#define MIIM_CIS8201_AUX_CONSTAT        0x1c
#define MIIM_CIS8201_AUXCONSTAT_INIT    0x0004
#define MIIM_CIS8201_AUXCONSTAT_DUPLEX  0x0020
#define MIIM_CIS8201_AUXCONSTAT_SPEED   0x0018
#define MIIM_CIS8201_AUXCONSTAT_GBIT    0x0010
#define MIIM_CIS8201_AUXCONSTAT_100     0x0008

/* Cicada Extended Control Register 1 */
#define MIIM_CIS8201_EXT_CON1           0x17
#define MIIM_CIS8201_EXTCON1_INIT       0x0000

/* Cicada 8204 Extended PHY Control Register 1 */
#define MIIM_CIS8204_EPHY_CON		0x17
#define MIIM_CIS8204_EPHYCON_INIT	0x0006
#define MIIM_CIS8204_EPHYCON_RGMII	0x1100

/* Cicada 8204 Serial LED Control Register */
#define MIIM_CIS8204_SLED_CON		0x1b
#define MIIM_CIS8204_SLEDCON_INIT	0x1115

#define MIIM_GBIT_CON		0x09
#define MIIM_GBIT_CON_ADVERT	0x0e00

/* Entry for Vitesse VSC8244 regs starts here */
/* Vitesse VSC8244 Auxiliary Control/Status Register */
#define MIIM_VSC8244_AUX_CONSTAT        0x1c
#define MIIM_VSC8244_AUXCONSTAT_INIT    0x0000
#define MIIM_VSC8244_AUXCONSTAT_DUPLEX  0x0020
#define MIIM_VSC8244_AUXCONSTAT_SPEED   0x0018
#define MIIM_VSC8244_AUXCONSTAT_GBIT    0x0010
#define MIIM_VSC8244_AUXCONSTAT_100     0x0008
#define MIIM_CONTROL_INIT_LOOPBACK      0x4000

/* Vitesse VSC8244 Extended PHY Control Register 1 */
#define MIIM_VSC8244_EPHY_CON           0x17
#define MIIM_VSC8244_EPHYCON_INIT       0x0006

/* Vitesse VSC8244 Serial LED Control Register */
#define MIIM_VSC8244_LED_CON            0x1b
#define MIIM_VSC8244_LEDCON_INIT        0xF011

/* 88E1011 PHY Status Register */
#define MIIM_88E1011_PHY_STATUS         0x11
#define MIIM_88E1011_PHYSTAT_SPEED      0xc000
#define MIIM_88E1011_PHYSTAT_GBIT       0x8000
#define MIIM_88E1011_PHYSTAT_100        0x4000
#define MIIM_88E1011_PHYSTAT_DUPLEX     0x2000
#define MIIM_88E1011_PHYSTAT_SPDDONE	0x0800
#define MIIM_88E1011_PHYSTAT_LINK	0x0400

#define MIIM_88E1011_PHY_SCR		0x10
#define MIIM_88E1011_PHY_MDI_X_AUTO	0x0060

/* 88E1111 PHY LED Control Register */
#define MIIM_88E1111_PHY_LED_CONTROL   24
#define MIIM_88E1111_PHY_LED_DIRECT    0x4100
#define MIIM_88E1111_PHY_LED_COMBINE   0x411C

/* 88E1145 Extended PHY Specific Control Register */
#define MIIM_88E1145_PHY_EXT_CR 20
#define MIIM_M88E1145_RGMII_RX_DELAY	0x0080
#define MIIM_M88E1145_RGMII_TX_DELAY	0x0002

#define MIIM_88E1145_PHY_PAGE   29
#define MIIM_88E1145_PHY_CAL_OV 30


/* DM9161 Control register values */
#define MIIM_DM9161_CR_STOP	0x0400
#define MIIM_DM9161_CR_RSTAN	0x1200

#define MIIM_DM9161_SCR		0x10
#define MIIM_DM9161_SCR_INIT	0x0610

/* DM9161 Specified Configuration and Status Register */
#define MIIM_DM9161_SCSR	0x11
#define MIIM_DM9161_SCSR_100F	0x8000
#define MIIM_DM9161_SCSR_100H	0x4000
#define MIIM_DM9161_SCSR_10F	0x2000
#define MIIM_DM9161_SCSR_10H	0x1000

/* DM9161 10BT Configuration/Status */
#define MIIM_DM9161_10BTCSR	0x12
#define MIIM_DM9161_10BTCSR_INIT	0x7800

/* LXT971 Status 2 registers */
#define MIIM_LXT971_SR2              0x11  /* Status Register 2  */
#define MIIM_LXT971_SR2_SPEED_MASK 0x4200
#define MIIM_LXT971_SR2_10HDX      0x0000  /*  10 Mbit half duplex selected */
#define MIIM_LXT971_SR2_10FDX      0x0200  /*  10 Mbit full duplex selected */
#define MIIM_LXT971_SR2_100HDX     0x4000  /* 100 Mbit half duplex selected */
#define MIIM_LXT971_SR2_100FDX     0x4200  /* 100 Mbit full duplex selected */

/* DP83865 Control register values */
#define MIIM_DP83865_CR_INIT	0x9200

/* DP83865 Link and Auto-Neg Status Register */
#define MIIM_DP83865_LANR	0x11
#define MIIM_DP83865_SPD_MASK	0x0018
#define MIIM_DP83865_SPD_1000	0x0010
#define MIIM_DP83865_SPD_100	0x0008
#define MIIM_DP83865_DPX_FULL	0x0002

#define MIIM_READ_COMMAND       0x00000001

#define MRBLR_INIT_SETTINGS	PKTSIZE_ALIGN

#define MINFLR_INIT_SETTINGS	0x00000040

#define DMACTRL_INIT_SETTINGS   0x000000c3
#define DMACTRL_GRS             0x00000010
#define DMACTRL_GTS             0x00000008

#define TSTAT_CLEAR_THALT       0x80000000
#define RSTAT_CLEAR_RHALT       0x00800000


#define IEVENT_INIT_CLEAR	0xffffffff
#define IEVENT_BABR		0x80000000
#define IEVENT_RXC		0x40000000
#define IEVENT_BSY		0x20000000
#define IEVENT_EBERR		0x10000000
#define IEVENT_MSRO		0x04000000
#define IEVENT_GTSC		0x02000000
#define IEVENT_BABT		0x01000000
#define IEVENT_TXC		0x00800000
#define IEVENT_TXE		0x00400000
#define IEVENT_TXB		0x00200000
#define IEVENT_TXF		0x00100000
#define IEVENT_IE		0x00080000
#define IEVENT_LC		0x00040000
#define IEVENT_CRL		0x00020000
#define IEVENT_XFUN		0x00010000
#define IEVENT_RXB0		0x00008000
#define IEVENT_GRSC		0x00000100
#define IEVENT_RXF0		0x00000080

#define IMASK_INIT_CLEAR	0x00000000
#define IMASK_TXEEN		0x00400000
#define IMASK_TXBEN		0x00200000
#define IMASK_TXFEN             0x00100000
#define IMASK_RXFEN0		0x00000080


/* Default Attribute fields */
#define ATTR_INIT_SETTINGS     0x000000c0
#define ATTRELI_INIT_SETTINGS  0x00000000


/* TxBD status field bits */
#define TXBD_READY		0x8000
#define TXBD_PADCRC		0x4000
#define TXBD_WRAP		0x2000
#define TXBD_INTERRUPT		0x1000
#define TXBD_LAST		0x0800
#define TXBD_CRC		0x0400
#define TXBD_DEF		0x0200
#define TXBD_HUGEFRAME		0x0080
#define TXBD_LATECOLLISION	0x0080
#define TXBD_RETRYLIMIT		0x0040
#define	TXBD_RETRYCOUNTMASK	0x003c
#define TXBD_UNDERRUN		0x0002
#define TXBD_STATS              0x03ff

/* RxBD status field bits */
#define RXBD_EMPTY		0x8000
#define RXBD_RO1		0x4000
#define RXBD_WRAP		0x2000
#define RXBD_INTERRUPT		0x1000
#define RXBD_LAST		0x0800
#define RXBD_FIRST		0x0400
#define RXBD_MISS		0x0100
#define RXBD_BROADCAST		0x0080
#define RXBD_MULTICAST		0x0040
#define RXBD_LARGE		0x0020
#define RXBD_NONOCTET		0x0010
#define RXBD_SHORT		0x0008
#define RXBD_CRCERR		0x0004
#define RXBD_OVERRUN		0x0002
#define RXBD_TRUNCATED		0x0001
#define RXBD_STATS		0x003f

typedef struct txbd8
{
	ushort       status;         /* Status Fields */
	ushort       length;         /* Buffer length */
	uint         bufPtr;         /* Buffer Pointer */
} txbd8_t;

typedef struct rxbd8
{
	ushort       status;         /* Status Fields */
	ushort       length;         /* Buffer Length */
	uint         bufPtr;         /* Buffer Pointer */
} rxbd8_t;

typedef struct rmon_mib
{
	/* Transmit and Receive Counters */
	uint	tr64;		/* Transmit and Receive 64-byte Frame Counter */
	uint	tr127;		/* Transmit and Receive 65-127 byte Frame Counter */
	uint	tr255;		/* Transmit and Receive 128-255 byte Frame Counter */
	uint	tr511;		/* Transmit and Receive 256-511 byte Frame Counter */
	uint	tr1k;		/* Transmit and Receive 512-1023 byte Frame Counter */
	uint	trmax;		/* Transmit and Receive 1024-1518 byte Frame Counter */
	uint	trmgv;		/* Transmit and Receive 1519-1522 byte Good VLAN Frame */
	/* Receive Counters */
	uint	rbyt;		/* Receive Byte Counter */
	uint	rpkt;		/* Receive Packet Counter */
	uint	rfcs;		/* Receive FCS Error Counter */
	uint	rmca;		/* Receive Multicast Packet (Counter) */
	uint	rbca;		/* Receive Broadcast Packet */
	uint	rxcf;		/* Receive Control Frame Packet */
	uint	rxpf;		/* Receive Pause Frame Packet */
	uint	rxuo;		/* Receive Unknown OP Code */
	uint	raln;		/* Receive Alignment Error */
	uint	rflr;		/* Receive Frame Length Error */
	uint	rcde;		/* Receive Code Error */
	uint	rcse;		/* Receive Carrier Sense Error */
	uint	rund;		/* Receive Undersize Packet */
	uint	rovr;		/* Receive Oversize Packet */
	uint	rfrg;		/* Receive Fragments */
	uint	rjbr;		/* Receive Jabber */
	uint	rdrp;		/* Receive Drop */
	/* Transmit Counters */
	uint	tbyt;		/* Transmit Byte Counter */
	uint	tpkt;		/* Transmit Packet */
	uint	tmca;		/* Transmit Multicast Packet */
	uint	tbca;		/* Transmit Broadcast Packet */
	uint	txpf;		/* Transmit Pause Control Frame */
	uint	tdfr;		/* Transmit Deferral Packet */
	uint	tedf;		/* Transmit Excessive Deferral Packet */
	uint	tscl;		/* Transmit Single Collision Packet */
	/* (0x2_n700) */
	uint	tmcl;		/* Transmit Multiple Collision Packet */
	uint	tlcl;		/* Transmit Late Collision Packet */
	uint	txcl;		/* Transmit Excessive Collision Packet */
	uint	tncl;		/* Transmit Total Collision */

	uint	res2;

	uint	tdrp;		/* Transmit Drop Frame */
	uint	tjbr;		/* Transmit Jabber Frame */
	uint	tfcs;		/* Transmit FCS Error */
	uint	txcf;		/* Transmit Control Frame */
	uint	tovr;		/* Transmit Oversize Frame */
	uint	tund;		/* Transmit Undersize Frame */
	uint	tfrg;		/* Transmit Fragments Frame */
	/* General Registers */
	uint	car1;		/* Carry Register One */
	uint	car2;		/* Carry Register Two */
	uint	cam1;		/* Carry Register One Mask */
	uint	cam2;		/* Carry Register Two Mask */
} rmon_mib_t;

typedef struct tsec_hash_regs
{
	uint	iaddr0;		/* Individual Address Register 0 */
	uint	iaddr1;		/* Individual Address Register 1 */
	uint	iaddr2;		/* Individual Address Register 2 */
	uint	iaddr3;		/* Individual Address Register 3 */
	uint	iaddr4;		/* Individual Address Register 4 */
	uint	iaddr5;		/* Individual Address Register 5 */
	uint	iaddr6;		/* Individual Address Register 6 */
	uint	iaddr7;		/* Individual Address Register 7 */
	uint	res1[24];
	uint	gaddr0;		/* Group Address Register 0 */
	uint	gaddr1;		/* Group Address Register 1 */
	uint	gaddr2;		/* Group Address Register 2 */
	uint	gaddr3;		/* Group Address Register 3 */
	uint	gaddr4;		/* Group Address Register 4 */
	uint	gaddr5;		/* Group Address Register 5 */
	uint	gaddr6;		/* Group Address Register 6 */
	uint	gaddr7;		/* Group Address Register 7 */
	uint	res2[24];
} tsec_hash_t;

typedef struct tsec
{
	/* General Control and Status Registers (0x2_n000) */
	uint	res000[4];

	uint	ievent;		/* Interrupt Event */
	uint	imask;		/* Interrupt Mask */
	uint	edis;		/* Error Disabled */
	uint	res01c;
	uint	ecntrl;		/* Ethernet Control */
	uint	minflr;		/* Minimum Frame Length */
	uint	ptv;		/* Pause Time Value */
	uint	dmactrl;	/* DMA Control */
	uint	tbipa;		/* TBI PHY Address */

	uint	res034[3];
	uint	res040[48];

	/* Transmit Control and Status Registers (0x2_n100) */
	uint	tctrl;		/* Transmit Control */
	uint 	tstat;		/* Transmit Status */
	uint	res108;
	uint	tbdlen;		/* Tx BD Data Length */
	uint	res110[5];
	uint	ctbptr;	        /* Current TxBD Pointer */
	uint	res128[23];
	uint	tbptr;		/* TxBD Pointer */
	uint	res188[30];
	/* (0x2_n200) */
	uint        res200;
	uint	tbase;		/* TxBD Base Address */
	uint	res208[42];
	uint	ostbd;		/* Out of Sequence TxBD */
	uint	ostbdp;		/* Out of Sequence Tx Data Buffer Pointer */
	uint        res2b8[18];

	/* Receive Control and Status Registers (0x2_n300) */
	uint	rctrl;		/* Receive Control */
	uint	rstat;		/* Receive Status */
	uint	res308;
	uint	rbdlen;		/* RxBD Data Length */
	uint	res310[4];
	uint        res320;
	uint	crbptr; 	/* Current Receive Buffer Pointer */
	uint	res328[6];
	uint	mrblr;  	/* Maximum Receive Buffer Length */
	uint	res344[16];
	uint	rbptr;   	/* RxBD Pointer */
	uint        res388[30];
	/* (0x2_n400) */
	uint        res400;
	uint	rbase;  	/* RxBD Base Address */
	uint        res408[62];

	/* MAC Registers (0x2_n500) */
	uint	maccfg1;	/* MAC Configuration #1 */
	uint	maccfg2;	/* MAC Configuration #2 */
	uint	ipgifg;		/* Inter Packet Gap/Inter Frame Gap */
	uint	hafdup;		/* Half-duplex */
	uint	maxfrm;		/* Maximum Frame */
	uint	res514;
	uint	res518;

	uint	res51c;

	uint	miimcfg;	/* MII Management: Configuration */
	uint	miimcom;	/* MII Management: Command */
	uint	miimadd;	/* MII Management: Address */
	uint	miimcon;	/* MII Management: Control */
	uint	miimstat;	/* MII Management: Status */
	uint	miimind;	/* MII Management: Indicators */

	uint	res538;

	uint	ifstat;		/* Interface Status */
	uint	macstnaddr1;	/* Station Address, part 1 */
	uint	macstnaddr2;	/* Station Address, part 2 */
	uint	res548[46];

	/* (0x2_n600) */
	uint	res600[32];

	/* RMON MIB Registers (0x2_n680-0x2_n73c) */
	rmon_mib_t	rmon;
	uint	res740[48];

	/* Hash Function Registers (0x2_n800) */
	tsec_hash_t	hash;

	uint        res900[128];

	/* Pattern Registers (0x2_nb00) */
	uint        resb00[62];
	uint        attr;          /* Default Attribute Register */
	uint        attreli;       /* Default Attribute Extract Length and Index */

	/* TSEC Future Expansion Space (0x2_nc00-0x2_nffc) */
	uint	resc00[256];
} tsec_t;

#define TSEC_GIGABIT (1)

/* This flag currently only has
 * meaning if we're using the eTSEC */
#define TSEC_REDUCED (1 << 1)

struct tsec_private {
	volatile tsec_t *regs;
	volatile tsec_t *phyregs;
	struct phy_info *phyinfo;
	uint phyaddr;
	u32 flags;
	uint link;
	uint duplexity;
	uint speed;
};


/*
 * struct phy_cmd:  A command for reading or writing a PHY register
 *
 * mii_reg:  The register to read or write
 *
 * mii_data:  For writes, the value to put in the register.
 * 	A value of -1 indicates this is a read.
 *
 * funct: A function pointer which is invoked for each command.
 * 	For reads, this function will be passed the value read
 *	from the PHY, and process it.
 *	For writes, the result of this function will be written
 *	to the PHY register
 */
struct phy_cmd {
    uint mii_reg;
    uint mii_data;
    uint (*funct) (uint mii_reg, struct tsec_private* priv);
};

/* struct phy_info: a structure which defines attributes for a PHY
 *
 * id will contain a number which represents the PHY.  During
 * startup, the driver will poll the PHY to find out what its
 * UID--as defined by registers 2 and 3--is.  The 32-bit result
 * gotten from the PHY will be shifted right by "shift" bits to
 * discard any bits which may change based on revision numbers
 * unimportant to functionality
 *
 * The struct phy_cmd entries represent pointers to an arrays of
 * commands which tell the driver what to do to the PHY.
 */
struct phy_info {
    uint id;
    char *name;
    uint shift;
    /* Called to configure the PHY, and modify the controller
     * based on the results */
    struct phy_cmd *config;

    /* Called when starting up the controller */
    struct phy_cmd *startup;

    /* Called when bringing down the controller */
    struct phy_cmd *shutdown;
};

#endif /* __TSEC_H */
Commit	Line	Data
42d1f039 WD	1	/*
	2	* tsec.h
	3	*
	4	* Driver for the Motorola Triple Speed Ethernet Controller
	5	*
	6	* This software may be used and distributed according to the
	7	* terms of the GNU Public License, Version 2, incorporated
	8	* herein by reference.
	9	*
97d80fc3	10	* Copyright 2004 Freescale Semiconductor.
42d1f039 WD	11	* (C) Copyright 2003, Motorola, Inc.
	12	* maintained by Xianghua Xiao (x.xiao@motorola.com)
	13	* author Andy Fleming
	14	*
	15	*/
	16
	17	#ifndef __TSEC_H
	18	#define __TSEC_H
	19
	20	#include <net.h>
f046ccd1 EL	21	#include <config.h>
	22
	23	#ifndef CFG_TSEC1_OFFSET
	24	#define CFG_TSEC1_OFFSET (0x24000)
	25	#endif
42d1f039	26
97d80fc3	27	#define TSEC_SIZE 0x01000
42d1f039	28
f046ccd1	29	/* FIXME: Should these be pushed back to 83xx and 85xx config files? */
debb7354	30	#if defined(CONFIG_MPC85xx) \|\| defined(CONFIG_MPC86xx)
f046ccd1 EL	31	#define TSEC_BASE_ADDR (CFG_IMMR + CFG_TSEC1_OFFSET)
f046ccd1 EL	32	#elif defined(CONFIG_MPC83XX)
d239d74b	33	#define TSEC_BASE_ADDR (CFG_IMMR + CFG_TSEC1_OFFSET)
f046ccd1 EL	34	#endif
	35
	36
42d1f039 WD	37	#define MAC_ADDR_LEN 6
42d1f039 WD	38
97d80fc3 WD	39	/* #define TSEC_TIMEOUT 1000000 */
97d80fc3 WD	40	#define TSEC_TIMEOUT 1000
42d1f039 WD	41	#define TOUT_LOOP 1000000
42d1f039 WD	42
5810dc3a SR	43	#define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* in ms */
5810dc3a SR	44
42d1f039 WD	45	/* MAC register bits */
	46	#define MACCFG1_SOFT_RESET 0x80000000
	47	#define MACCFG1_RESET_RX_MC 0x00080000
	48	#define MACCFG1_RESET_TX_MC 0x00040000
	49	#define MACCFG1_RESET_RX_FUN 0x00020000
	50	#define MACCFG1_RESET_TX_FUN 0x00010000
	51	#define MACCFG1_LOOPBACK 0x00000100
	52	#define MACCFG1_RX_FLOW 0x00000020
	53	#define MACCFG1_TX_FLOW 0x00000010
	54	#define MACCFG1_SYNCD_RX_EN 0x00000008
	55	#define MACCFG1_RX_EN 0x00000004
	56	#define MACCFG1_SYNCD_TX_EN 0x00000002
	57	#define MACCFG1_TX_EN 0x00000001
	58
	59	#define MACCFG2_INIT_SETTINGS 0x00007205
	60	#define MACCFG2_FULL_DUPLEX 0x00000001
	61	#define MACCFG2_IF 0x00000300
97d80fc3	62	#define MACCFG2_GMII 0x00000200
42d1f039 WD	63	#define MACCFG2_MII 0x00000100
	64
	65	#define ECNTRL_INIT_SETTINGS 0x00001000
	66	#define ECNTRL_TBI_MODE 0x00000020
d9b94f28	67	#define ECNTRL_R100 0x00000008
42d1f039	68
97d80fc3 WD	69	#define miim_end -2
	70	#define miim_read -1
	71
42d1f039 WD	72	#define TBIPA_VALUE 0x1f
	73	#define MIIMCFG_INIT_VALUE 0x00000003
	74	#define MIIMCFG_RESET 0x80000000
	75
	76	#define MIIMIND_BUSY 0x00000001
	77	#define MIIMIND_NOTVALID 0x00000004
	78
42d1f039	79	#define MIIM_CONTROL 0x00
97d80fc3	80	#define MIIM_CONTROL_RESET 0x00009140
42d1f039	81	#define MIIM_CONTROL_INIT 0x00001140
5810dc3a	82	#define MIIM_CONTROL_RESTART 0x00001340
42d1f039	83	#define MIIM_ANEN 0x00001000
97d80fc3 WD	84
	85	#define MIIM_CR 0x00
	86	#define MIIM_CR_RST 0x00008000
	87	#define MIIM_CR_INIT 0x00001000
7abf0c58 WD	88
	89	#define MIIM_STATUS 0x1
	90	#define MIIM_STATUS_AN_DONE 0x00000020
97d80fc3	91	#define MIIM_STATUS_LINK 0x0004
5810dc3a SR	92	#define PHY_BMSR_AUTN_ABLE 0x0008
5810dc3a SR	93	#define PHY_BMSR_AUTN_COMP 0x0020
42d1f039	94
97d80fc3 WD	95	#define MIIM_PHYIR1 0x2
97d80fc3 WD	96	#define MIIM_PHYIR2 0x3
42d1f039	97
97d80fc3 WD	98	#define MIIM_ANAR 0x4
97d80fc3 WD	99	#define MIIM_ANAR_INIT 0x1e1
42d1f039 WD	100
	101	#define MIIM_TBI_ANLPBPA 0x5
	102	#define MIIM_TBI_ANLPBPA_HALF 0x00000040
	103	#define MIIM_TBI_ANLPBPA_FULL 0x00000020
	104
97d80fc3 WD	105	#define MIIM_TBI_ANEX 0x6
	106	#define MIIM_TBI_ANEX_NP 0x00000004
	107	#define MIIM_TBI_ANEX_PRX 0x00000002
	108
	109	#define MIIM_GBIT_CONTROL 0x9
	110	#define MIIM_GBIT_CONTROL_INIT 0xe00
	111
91e25769 PG	112	/* Broadcom BCM54xx -- taken from linux sungem_phy */
	113	#define MIIM_BCM54xx_AUXSTATUS 0x19
	114	#define MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK 0x0700
	115	#define MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT 8
	116
97d80fc3 WD	117	/* Cicada Auxiliary Control/Status Register */
	118	#define MIIM_CIS8201_AUX_CONSTAT 0x1c
	119	#define MIIM_CIS8201_AUXCONSTAT_INIT 0x0004
	120	#define MIIM_CIS8201_AUXCONSTAT_DUPLEX 0x0020
	121	#define MIIM_CIS8201_AUXCONSTAT_SPEED 0x0018
	122	#define MIIM_CIS8201_AUXCONSTAT_GBIT 0x0010
	123	#define MIIM_CIS8201_AUXCONSTAT_100 0x0008
42d1f039	124
97d80fc3 WD	125	/* Cicada Extended Control Register 1 */
	126	#define MIIM_CIS8201_EXT_CON1 0x17
	127	#define MIIM_CIS8201_EXTCON1_INIT 0x0000
42d1f039	128
97d80fc3 WD	129	/* Cicada 8204 Extended PHY Control Register 1 */
	130	#define MIIM_CIS8204_EPHY_CON 0x17
	131	#define MIIM_CIS8204_EPHYCON_INIT 0x0006
03469832	132	#define MIIM_CIS8204_EPHYCON_RGMII 0x1100
42d1f039	133
97d80fc3 WD	134	/* Cicada 8204 Serial LED Control Register */
	135	#define MIIM_CIS8204_SLED_CON 0x1b
	136	#define MIIM_CIS8204_SLEDCON_INIT 0x1115
42d1f039 WD	137
42d1f039 WD	138	#define MIIM_GBIT_CON 0x09
7abf0c58	139	#define MIIM_GBIT_CON_ADVERT 0x0e00
42d1f039	140
debb7354 JL	141	/* Entry for Vitesse VSC8244 regs starts here */
	142	/* Vitesse VSC8244 Auxiliary Control/Status Register */
	143	#define MIIM_VSC8244_AUX_CONSTAT 0x1c
	144	#define MIIM_VSC8244_AUXCONSTAT_INIT 0x0000
	145	#define MIIM_VSC8244_AUXCONSTAT_DUPLEX 0x0020
	146	#define MIIM_VSC8244_AUXCONSTAT_SPEED 0x0018
	147	#define MIIM_VSC8244_AUXCONSTAT_GBIT 0x0010
	148	#define MIIM_VSC8244_AUXCONSTAT_100 0x0008
	149	#define MIIM_CONTROL_INIT_LOOPBACK 0x4000
	150
	151	/* Vitesse VSC8244 Extended PHY Control Register 1 */
	152	#define MIIM_VSC8244_EPHY_CON 0x17
	153	#define MIIM_VSC8244_EPHYCON_INIT 0x0006
	154
	155	/* Vitesse VSC8244 Serial LED Control Register */
	156	#define MIIM_VSC8244_LED_CON 0x1b
	157	#define MIIM_VSC8244_LEDCON_INIT 0xF011
	158
97d80fc3 WD	159	/* 88E1011 PHY Status Register */
	160	#define MIIM_88E1011_PHY_STATUS 0x11
	161	#define MIIM_88E1011_PHYSTAT_SPEED 0xc000
	162	#define MIIM_88E1011_PHYSTAT_GBIT 0x8000
	163	#define MIIM_88E1011_PHYSTAT_100 0x4000
	164	#define MIIM_88E1011_PHYSTAT_DUPLEX 0x2000
	165	#define MIIM_88E1011_PHYSTAT_SPDDONE 0x0800
	166	#define MIIM_88E1011_PHYSTAT_LINK 0x0400
	167
09f3e09e AF	168	#define MIIM_88E1011_PHY_SCR 0x10
	169	#define MIIM_88E1011_PHY_MDI_X_AUTO 0x0060
	170
	171	/* 88E1111 PHY LED Control Register */
	172	#define MIIM_88E1111_PHY_LED_CONTROL 24
	173	#define MIIM_88E1111_PHY_LED_DIRECT 0x4100
	174	#define MIIM_88E1111_PHY_LED_COMBINE 0x411C
	175
	176	/* 88E1145 Extended PHY Specific Control Register */
	177	#define MIIM_88E1145_PHY_EXT_CR 20
	178	#define MIIM_M88E1145_RGMII_RX_DELAY 0x0080
	179	#define MIIM_M88E1145_RGMII_TX_DELAY 0x0002
	180
	181	#define MIIM_88E1145_PHY_PAGE 29
	182	#define MIIM_88E1145_PHY_CAL_OV 30
	183
	184
97d80fc3 WD	185	/* DM9161 Control register values */
	186	#define MIIM_DM9161_CR_STOP 0x0400
	187	#define MIIM_DM9161_CR_RSTAN 0x1200
	188
	189	#define MIIM_DM9161_SCR 0x10
	190	#define MIIM_DM9161_SCR_INIT 0x0610
	191
	192	/* DM9161 Specified Configuration and Status Register */
	193	#define MIIM_DM9161_SCSR 0x11
	194	#define MIIM_DM9161_SCSR_100F 0x8000
	195	#define MIIM_DM9161_SCSR_100H 0x4000
	196	#define MIIM_DM9161_SCSR_10F 0x2000
	197	#define MIIM_DM9161_SCSR_10H 0x1000
	198
	199	/* DM9161 10BT Configuration/Status */
	200	#define MIIM_DM9161_10BTCSR 0x12
	201	#define MIIM_DM9161_10BTCSR_INIT 0x7800
42d1f039	202
3dd7f0f0	203	/* LXT971 Status 2 registers */
d8169c9f WD	204	#define MIIM_LXT971_SR2 0x11 /* Status Register 2 */
	205	#define MIIM_LXT971_SR2_SPEED_MASK 0x4200
	206	#define MIIM_LXT971_SR2_10HDX 0x0000 /* 10 Mbit half duplex selected */
	207	#define MIIM_LXT971_SR2_10FDX 0x0200 /* 10 Mbit full duplex selected */
	208	#define MIIM_LXT971_SR2_100HDX 0x4000 /* 100 Mbit half duplex selected */
	209	#define MIIM_LXT971_SR2_100FDX 0x4200 /* 100 Mbit full duplex selected */
3dd7f0f0	210
be5048f1 WD	211	/* DP83865 Control register values */
	212	#define MIIM_DP83865_CR_INIT 0x9200
	213
	214	/* DP83865 Link and Auto-Neg Status Register */
	215	#define MIIM_DP83865_LANR 0x11
	216	#define MIIM_DP83865_SPD_MASK 0x0018
	217	#define MIIM_DP83865_SPD_1000 0x0010
	218	#define MIIM_DP83865_SPD_100 0x0008
	219	#define MIIM_DP83865_DPX_FULL 0x0002
	220
42d1f039 WD	221	#define MIIM_READ_COMMAND 0x00000001
	222
	223	#define MRBLR_INIT_SETTINGS PKTSIZE_ALIGN
	224
	225	#define MINFLR_INIT_SETTINGS 0x00000040
	226
	227	#define DMACTRL_INIT_SETTINGS 0x000000c3
	228	#define DMACTRL_GRS 0x00000010
	229	#define DMACTRL_GTS 0x00000008
	230
	231	#define TSTAT_CLEAR_THALT 0x80000000
	232	#define RSTAT_CLEAR_RHALT 0x00800000
	233
7abf0c58	234
42d1f039 WD	235	#define IEVENT_INIT_CLEAR 0xffffffff
	236	#define IEVENT_BABR 0x80000000
	237	#define IEVENT_RXC 0x40000000
	238	#define IEVENT_BSY 0x20000000
	239	#define IEVENT_EBERR 0x10000000
	240	#define IEVENT_MSRO 0x04000000
	241	#define IEVENT_GTSC 0x02000000
	242	#define IEVENT_BABT 0x01000000
	243	#define IEVENT_TXC 0x00800000
	244	#define IEVENT_TXE 0x00400000
	245	#define IEVENT_TXB 0x00200000
	246	#define IEVENT_TXF 0x00100000
	247	#define IEVENT_IE 0x00080000
	248	#define IEVENT_LC 0x00040000
	249	#define IEVENT_CRL 0x00020000
	250	#define IEVENT_XFUN 0x00010000
	251	#define IEVENT_RXB0 0x00008000
	252	#define IEVENT_GRSC 0x00000100
	253	#define IEVENT_RXF0 0x00000080
	254
	255	#define IMASK_INIT_CLEAR 0x00000000
	256	#define IMASK_TXEEN 0x00400000
	257	#define IMASK_TXBEN 0x00200000
	258	#define IMASK_TXFEN 0x00100000
	259	#define IMASK_RXFEN0 0x00000080
	260
	261
	262	/* Default Attribute fields */
	263	#define ATTR_INIT_SETTINGS 0x000000c0
	264	#define ATTRELI_INIT_SETTINGS 0x00000000
	265
	266
	267	/* TxBD status field bits */
	268	#define TXBD_READY 0x8000
	269	#define TXBD_PADCRC 0x4000
	270	#define TXBD_WRAP 0x2000
	271	#define TXBD_INTERRUPT 0x1000
	272	#define TXBD_LAST 0x0800
	273	#define TXBD_CRC 0x0400
	274	#define TXBD_DEF 0x0200
	275	#define TXBD_HUGEFRAME 0x0080
	276	#define TXBD_LATECOLLISION 0x0080
	277	#define TXBD_RETRYLIMIT 0x0040
	278	#define TXBD_RETRYCOUNTMASK 0x003c
	279	#define TXBD_UNDERRUN 0x0002
	280	#define TXBD_STATS 0x03ff
	281
	282	/* RxBD status field bits */
	283	#define RXBD_EMPTY 0x8000
	284	#define RXBD_RO1 0x4000
	285	#define RXBD_WRAP 0x2000
	286	#define RXBD_INTERRUPT 0x1000
	287	#define RXBD_LAST 0x0800
	288	#define RXBD_FIRST 0x0400
	289	#define RXBD_MISS 0x0100
	290	#define RXBD_BROADCAST 0x0080
	291	#define RXBD_MULTICAST 0x0040
	292	#define RXBD_LARGE 0x0020
	293	#define RXBD_NONOCTET 0x0010
	294	#define RXBD_SHORT 0x0008
	295	#define RXBD_CRCERR 0x0004
	296	#define RXBD_OVERRUN 0x0002
	297	#define RXBD_TRUNCATED 0x0001
	298	#define RXBD_STATS 0x003f
299
300	typedef struct txbd8
301	{
302	ushort status; /* Status Fields */
303	ushort length; /* Buffer length */
304	uint bufPtr; /* Buffer Pointer */
305	} txbd8_t;
306
307	typedef struct rxbd8
308	{
309	ushort status; /* Status Fields */
310	ushort length; /* Buffer Length */
311	uint bufPtr; /* Buffer Pointer */
312	} rxbd8_t;
313
314	typedef struct rmon_mib
315	{
316	/* Transmit and Receive Counters */
317	uint tr64; /* Transmit and Receive 64-byte Frame Counter */
318	uint tr127; /* Transmit and Receive 65-127 byte Frame Counter */
319	uint tr255; /* Transmit and Receive 128-255 byte Frame Counter */
320	uint tr511; /* Transmit and Receive 256-511 byte Frame Counter */
321	uint tr1k; /* Transmit and Receive 512-1023 byte Frame Counter */
322	uint trmax; /* Transmit and Receive 1024-1518 byte Frame Counter */
323	uint trmgv; /* Transmit and Receive 1519-1522 byte Good VLAN Frame */
324	/* Receive Counters */
325	uint rbyt; /* Receive Byte Counter */
326	uint rpkt; /* Receive Packet Counter */
327	uint rfcs; /* Receive FCS Error Counter */
328	uint rmca; /* Receive Multicast Packet (Counter) */
329	uint rbca; /* Receive Broadcast Packet */
330	uint rxcf; /* Receive Control Frame Packet */
331	uint rxpf; /* Receive Pause Frame Packet */
332	uint rxuo; /* Receive Unknown OP Code */
333	uint raln; /* Receive Alignment Error */
334	uint rflr; /* Receive Frame Length Error */
335	uint rcde; /* Receive Code Error */
336	uint rcse; /* Receive Carrier Sense Error */
337	uint rund; /* Receive Undersize Packet */
338	uint rovr; /* Receive Oversize Packet */
339	uint rfrg; /* Receive Fragments */
340	uint rjbr; /* Receive Jabber */
341	uint rdrp; /* Receive Drop */
342	/* Transmit Counters */
343	uint tbyt; /* Transmit Byte Counter */
344	uint tpkt; /* Transmit Packet */
345	uint tmca; /* Transmit Multicast Packet */
346	uint tbca; /* Transmit Broadcast Packet */
347	uint txpf; /* Transmit Pause Control Frame */
348	uint tdfr; /* Transmit Deferral Packet */
349	uint tedf; /* Transmit Excessive Deferral Packet */
350	uint tscl; /* Transmit Single Collision Packet */
351	/* (0x2_n700) */
352	uint tmcl; /* Transmit Multiple Collision Packet */
353	uint tlcl; /* Transmit Late Collision Packet */
354	uint txcl; /* Transmit Excessive Collision Packet */
355	uint tncl; /* Transmit Total Collision */
356
357	uint res2;
358
359	uint tdrp; /* Transmit Drop Frame */
360	uint tjbr; /* Transmit Jabber Frame */
361	uint tfcs; /* Transmit FCS Error */
362	uint txcf; /* Transmit Control Frame */
363	uint tovr; /* Transmit Oversize Frame */
364	uint tund; /* Transmit Undersize Frame */
365	uint tfrg; /* Transmit Fragments Frame */
366	/* General Registers */
367	uint car1; /* Carry Register One */
368	uint car2; /* Carry Register Two */
369	uint cam1; /* Carry Register One Mask */
370	uint cam2; /* Carry Register Two Mask */
371	} rmon_mib_t;
372
373	typedef struct tsec_hash_regs
374	{
375	uint iaddr0; /* Individual Address Register 0 */
376	uint iaddr1; /* Individual Address Register 1 */
377	uint iaddr2; /* Individual Address Register 2 */
378	uint iaddr3; /* Individual Address Register 3 */
379	uint iaddr4; /* Individual Address Register 4 */
380	uint iaddr5; /* Individual Address Register 5 */
381	uint iaddr6; /* Individual Address Register 6 */
382	uint iaddr7; /* Individual Address Register 7 */
383	uint res1[24];
384	uint gaddr0; /* Group Address Register 0 */
385	uint gaddr1; /* Group Address Register 1 */
386	uint gaddr2; /* Group Address Register 2 */
387	uint gaddr3; /* Group Address Register 3 */
388	uint gaddr4; /* Group Address Register 4 */
389	uint gaddr5; /* Group Address Register 5 */
390	uint gaddr6; /* Group Address Register 6 */
391	uint gaddr7; /* Group Address Register 7 */
392	uint res2[24];
393	} tsec_hash_t;
394
395	typedef struct tsec
396	{
397	/* General Control and Status Registers (0x2_n000) */
398	uint res000[4];
399
400	uint ievent; /* Interrupt Event */
401	uint imask; /* Interrupt Mask */
402	uint edis; /* Error Disabled */
403	uint res01c;
404	uint ecntrl; /* Ethernet Control */
405	uint minflr; /* Minimum Frame Length */
406	uint ptv; /* Pause Time Value */
407	uint dmactrl; /* DMA Control */
408	uint tbipa; /* TBI PHY Address */
409
410	uint res034[3];
411	uint res040[48];
412
413	/* Transmit Control and Status Registers (0x2_n100) */
414	uint tctrl; /* Transmit Control */
415	uint tstat; /* Transmit Status */
416	uint res108;
417	uint tbdlen; /* Tx BD Data Length */
418	uint res110[5];
419	uint ctbptr; /* Current TxBD Pointer */
420	uint res128[23];
421	uint tbptr; /* TxBD Pointer */
422	uint res188[30];
423	/* (0x2_n200) */
424	uint res200;
425	uint tbase; /* TxBD Base Address */
426	uint res208[42];
427	uint ostbd; /* Out of Sequence TxBD */
428	uint ostbdp; /* Out of Sequence Tx Data Buffer Pointer */
429	uint res2b8[18];
430
431	/* Receive Control and Status Registers (0x2_n300) */
432	uint rctrl; /* Receive Control */
433	uint rstat; /* Receive Status */
434	uint res308;
435	uint rbdlen; /* RxBD Data Length */
436	uint res310[4];
437	uint res320;
438	uint crbptr; /* Current Receive Buffer Pointer */
439	uint res328[6];
440	uint mrblr; /* Maximum Receive Buffer Length */
441	uint res344[16];
442	uint rbptr; /* RxBD Pointer */
443	uint res388[30];
444	/* (0x2_n400) */
445	uint res400;
446	uint rbase; /* RxBD Base Address */
447	uint res408[62];
448
449	/* MAC Registers (0x2_n500) */
450	uint maccfg1; /* MAC Configuration #1 */
451	uint maccfg2; /* MAC Configuration #2 */
452	uint ipgifg; /* Inter Packet Gap/Inter Frame Gap */
453	uint hafdup; /* Half-duplex */
454	uint maxfrm; /* Maximum Frame */
455	uint res514;
456	uint res518;
457
458	uint res51c;
459
460	uint miimcfg; /* MII Management: Configuration */
461	uint miimcom; /* MII Management: Command */
462	uint miimadd; /* MII Management: Address */
463	uint miimcon; /* MII Management: Control */
464	uint miimstat; /* MII Management: Status */
465	uint miimind; /* MII Management: Indicators */
466
467	uint res538;
468
469	uint ifstat; /* Interface Status */
470	uint macstnaddr1; /* Station Address, part 1 */
471	uint macstnaddr2; /* Station Address, part 2 */
472	uint res548[46];
473
474	/* (0x2_n600) */
475	uint res600[32];
476
477	/* RMON MIB Registers (0x2_n680-0x2_n73c) */
478	rmon_mib_t rmon;
479	uint res740[48];
480
481	/* Hash Function Registers (0x2_n800) */
482	tsec_hash_t hash;
483
484	uint res900[128];
485
486	/* Pattern Registers (0x2_nb00) */
487	uint resb00[62];
488	uint attr; /* Default Attribute Register */
489	uint attreli; /* Default Attribute Extract Length and Index */
490
491	/* TSEC Future Expansion Space (0x2_nc00-0x2_nffc) */
492	uint resc00[256];
493	} tsec_t;
494
d9b94f28 JL	495	#define TSEC_GIGABIT (1)
	496
	497	/* This flag currently only has
	498	* meaning if we're using the eTSEC */
	499	#define TSEC_REDUCED (1 << 1)
	500
97d80fc3 WD	501	struct tsec_private {
	502	volatile tsec_t *regs;
	503	volatile tsec_t *phyregs;
	504	struct phy_info *phyinfo;
	505	uint phyaddr;
d9b94f28	506	u32 flags;
97d80fc3 WD	507	uint link;
	508	uint duplexity;
	509	uint speed;
	510	};
	511
	512
	513	/*
	514	* struct phy_cmd: A command for reading or writing a PHY register
	515	*
	516	* mii_reg: The register to read or write
	517	*
	518	* mii_data: For writes, the value to put in the register.
	519	* A value of -1 indicates this is a read.
	520	*
	521	* funct: A function pointer which is invoked for each command.
	522	* For reads, this function will be passed the value read
	523	* from the PHY, and process it.
	524	* For writes, the result of this function will be written
	525	* to the PHY register
	526	*/
	527	struct phy_cmd {
	528	uint mii_reg;
	529	uint mii_data;
	530	uint (funct) (uint mii_reg, struct tsec_private priv);
	531	};
	532
	533	/* struct phy_info: a structure which defines attributes for a PHY
	534	*
	535	* id will contain a number which represents the PHY. During
	536	* startup, the driver will poll the PHY to find out what its
	537	* UID--as defined by registers 2 and 3--is. The 32-bit result
	538	* gotten from the PHY will be shifted right by "shift" bits to
	539	* discard any bits which may change based on revision numbers
	540	* unimportant to functionality
	541	*
	542	* The struct phy_cmd entries represent pointers to an arrays of
	543	* commands which tell the driver what to do to the PHY.
	544	*/
	545	struct phy_info {
	546	uint id;
	547	char *name;
	548	uint shift;
	549	/* Called to configure the PHY, and modify the controller
	550	* based on the results */
	551	struct phy_cmd *config;
	552
	553	/* Called when starting up the controller */
	554	struct phy_cmd *startup;
	555
	556	/* Called when bringing down the controller */
	557	struct phy_cmd *shutdown;
	558	};
	559
42d1f039	560	#endif /* __TSEC_H */