[people/ms/u-boot.git] / drivers / usb / gadget / bcm_udc_otg_phy.c

/*
 * Copyright 2015 Broadcom Corporation.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <config.h>
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sysmap.h>
#include <asm/kona-common/clk.h>

#include "dwc2_udc_otg_priv.h"
#include "bcm_udc_otg.h"

void otg_phy_init(struct dwc2_udc *dev)
{
	/* turn on the USB OTG clocks */
	clk_usb_otg_enable((void *)HSOTG_BASE_ADDR);

	/* set Phy to driving mode */
	wfld_clear(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET,
		   HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK);

	udelay(100);

	/* clear Soft Disconnect */
	wfld_clear(HSOTG_BASE_ADDR + HSOTG_DCTL_OFFSET,
		   HSOTG_DCTL_SFTDISCON_MASK);

	/* invoke Reset (active low) */
	wfld_clear(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET,
		   HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK);

	/* Reset needs to be asserted for 2ms */
	udelay(2000);

	/* release Reset */
	wfld_set(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET,
		 HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK,
		 HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK);
}

void otg_phy_off(struct dwc2_udc *dev)
{
	/* Soft Disconnect */
	wfld_set(HSOTG_BASE_ADDR + HSOTG_DCTL_OFFSET,
		 HSOTG_DCTL_SFTDISCON_MASK,
		 HSOTG_DCTL_SFTDISCON_MASK);

	/* set Phy to non-driving (reset) mode */
	wfld_set(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET,
		 HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK,
		 HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK);
}
Commit	Line	Data
854cbd29 JZ	1	/*
	2	* Copyright 2015 Broadcom Corporation.
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#include <config.h>
	8	#include <common.h>
	9	#include <asm/io.h>
	10	#include <asm/arch/sysmap.h>
cf125473	11	#include <asm/kona-common/clk.h>
854cbd29	12
f4d9bd06	13	#include "dwc2_udc_otg_priv.h"
854cbd29 JZ	14	#include "bcm_udc_otg.h"
854cbd29 JZ	15
b4d5cf0b	16	void otg_phy_init(struct dwc2_udc *dev)
854cbd29	17	{
cf125473 SR	18	/* turn on the USB OTG clocks */
	19	clk_usb_otg_enable((void *)HSOTG_BASE_ADDR);
	20
854cbd29 JZ	21	/* set Phy to driving mode */
	22	wfld_clear(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET,
	23	HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK);
	24
	25	udelay(100);
	26
	27	/* clear Soft Disconnect */
	28	wfld_clear(HSOTG_BASE_ADDR + HSOTG_DCTL_OFFSET,
	29	HSOTG_DCTL_SFTDISCON_MASK);
	30
	31	/* invoke Reset (active low) */
	32	wfld_clear(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET,
	33	HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK);
	34
	35	/* Reset needs to be asserted for 2ms */
	36	udelay(2000);
	37
	38	/* release Reset */
	39	wfld_set(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET,
	40	HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK,
	41	HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK);
	42	}
	43
b4d5cf0b	44	void otg_phy_off(struct dwc2_udc *dev)
854cbd29 JZ	45	{
	46	/* Soft Disconnect */
	47	wfld_set(HSOTG_BASE_ADDR + HSOTG_DCTL_OFFSET,
	48	HSOTG_DCTL_SFTDISCON_MASK,
	49	HSOTG_DCTL_SFTDISCON_MASK);
	50
	51	/* set Phy to non-driving (reset) mode */
	52	wfld_set(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET,
	53	HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK,
	54	HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK);
	55	}