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Commit | Line | Data |
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38517a78 | 1 | /* |
be5e4bdc | 2 | * drivers/usb/gadget/dwc2_udc_otg.c |
e179cedd | 3 | * Designware DWC2 on-chip full/high speed USB OTG 2.0 device controllers |
38517a78 ŁM |
4 | * |
5 | * Copyright (C) 2008 for Samsung Electronics | |
6 | * | |
7 | * BSP Support for Samsung's UDC driver | |
8 | * available at: | |
9 | * git://git.kernel.org/pub/scm/linux/kernel/git/kki_ap/linux-2.6-samsung.git | |
10 | * | |
11 | * State machine bugfixes: | |
12 | * Marek Szyprowski <m.szyprowski@samsung.com> | |
13 | * | |
14 | * Ported to u-boot: | |
15 | * Marek Szyprowski <m.szyprowski@samsung.com> | |
16 | * Lukasz Majewski <l.majewski@samsumg.com> | |
17 | * | |
1a459660 | 18 | * SPDX-License-Identifier: GPL-2.0+ |
38517a78 | 19 | */ |
6734b6b2 | 20 | #undef DEBUG |
38517a78 | 21 | #include <common.h> |
1221ce45 | 22 | #include <linux/errno.h> |
38517a78 ŁM |
23 | #include <linux/list.h> |
24 | #include <malloc.h> | |
25 | ||
26 | #include <linux/usb/ch9.h> | |
27 | #include <linux/usb/gadget.h> | |
28 | ||
29 | #include <asm/byteorder.h> | |
b2fb47f1 | 30 | #include <asm/unaligned.h> |
38517a78 ŁM |
31 | #include <asm/io.h> |
32 | ||
33 | #include <asm/mach-types.h> | |
38517a78 | 34 | |
f4d9bd06 MV |
35 | #include "dwc2_udc_otg_regs.h" |
36 | #include "dwc2_udc_otg_priv.h" | |
38517a78 ŁM |
37 | #include <usb/lin_gadget_compat.h> |
38 | ||
39 | /***********************************************************/ | |
40 | ||
41 | #define OTG_DMA_MODE 1 | |
42 | ||
f3b05ca5 ŁM |
43 | #define DEBUG_SETUP 0 |
44 | #define DEBUG_EP0 0 | |
45 | #define DEBUG_ISR 0 | |
46 | #define DEBUG_OUT_EP 0 | |
47 | #define DEBUG_IN_EP 0 | |
38517a78 | 48 | |
5d5716ee | 49 | #include <usb/dwc2_udc.h> |
38517a78 ŁM |
50 | |
51 | #define EP0_CON 0 | |
52 | #define EP_MASK 0xF | |
53 | ||
38517a78 ŁM |
54 | static char *state_names[] = { |
55 | "WAIT_FOR_SETUP", | |
56 | "DATA_STATE_XMIT", | |
57 | "DATA_STATE_NEED_ZLP", | |
58 | "WAIT_FOR_OUT_STATUS", | |
59 | "DATA_STATE_RECV", | |
60 | "WAIT_FOR_COMPLETE", | |
61 | "WAIT_FOR_OUT_COMPLETE", | |
62 | "WAIT_FOR_IN_COMPLETE", | |
63 | "WAIT_FOR_NULL_COMPLETE", | |
64 | }; | |
38517a78 | 65 | |
38517a78 ŁM |
66 | #define DRIVER_VERSION "15 March 2009" |
67 | ||
b4d5cf0b | 68 | struct dwc2_udc *the_controller; |
38517a78 | 69 | |
06cb6ccd | 70 | static const char driver_name[] = "dwc2-udc"; |
38517a78 ŁM |
71 | static const char ep0name[] = "ep0-control"; |
72 | ||
73 | /* Max packet size*/ | |
74 | static unsigned int ep0_fifo_size = 64; | |
75 | static unsigned int ep_fifo_size = 512; | |
76 | static unsigned int ep_fifo_size2 = 1024; | |
77 | static int reset_available = 1; | |
78 | ||
79 | static struct usb_ctrlrequest *usb_ctrl; | |
80 | static dma_addr_t usb_ctrl_dma_addr; | |
81 | ||
82 | /* | |
83 | Local declarations. | |
84 | */ | |
ae1f2f0c | 85 | static int dwc2_ep_enable(struct usb_ep *ep, |
38517a78 | 86 | const struct usb_endpoint_descriptor *); |
ae1f2f0c | 87 | static int dwc2_ep_disable(struct usb_ep *ep); |
155e740f | 88 | static struct usb_request *dwc2_alloc_request(struct usb_ep *ep, |
38517a78 | 89 | gfp_t gfp_flags); |
155e740f | 90 | static void dwc2_free_request(struct usb_ep *ep, struct usb_request *); |
38517a78 | 91 | |
155e740f MV |
92 | static int dwc2_queue(struct usb_ep *ep, struct usb_request *, gfp_t gfp_flags); |
93 | static int dwc2_dequeue(struct usb_ep *ep, struct usb_request *); | |
94 | static int dwc2_fifo_status(struct usb_ep *ep); | |
95 | static void dwc2_fifo_flush(struct usb_ep *ep); | |
28b97748 MV |
96 | static void dwc2_ep0_read(struct dwc2_udc *dev); |
97 | static void dwc2_ep0_kick(struct dwc2_udc *dev, struct dwc2_ep *ep); | |
155e740f | 98 | static void dwc2_handle_ep0(struct dwc2_udc *dev); |
28b97748 | 99 | static int dwc2_ep0_write(struct dwc2_udc *dev); |
c056c52b MV |
100 | static int write_fifo_ep0(struct dwc2_ep *ep, struct dwc2_request *req); |
101 | static void done(struct dwc2_ep *ep, struct dwc2_request *req, int status); | |
b4d5cf0b | 102 | static void stop_activity(struct dwc2_udc *dev, |
38517a78 | 103 | struct usb_gadget_driver *driver); |
b4d5cf0b MV |
104 | static int udc_enable(struct dwc2_udc *dev); |
105 | static void udc_set_address(struct dwc2_udc *dev, unsigned char address); | |
106 | static void reconfig_usbd(struct dwc2_udc *dev); | |
107 | static void set_max_pktsize(struct dwc2_udc *dev, enum usb_device_speed speed); | |
627d9298 | 108 | static void nuke(struct dwc2_ep *ep, int status); |
f52dd802 MV |
109 | static int dwc2_udc_set_halt(struct usb_ep *_ep, int value); |
110 | static void dwc2_udc_set_nak(struct dwc2_ep *ep); | |
38517a78 | 111 | |
6734b6b2 ŁM |
112 | void set_udc_gadget_private_data(void *p) |
113 | { | |
114 | debug_cond(DEBUG_SETUP != 0, | |
115 | "%s: the_controller: 0x%p, p: 0x%p\n", __func__, | |
116 | the_controller, p); | |
117 | the_controller->gadget.dev.device_data = p; | |
118 | } | |
119 | ||
120 | void *get_udc_gadget_private_data(struct usb_gadget *gadget) | |
121 | { | |
122 | return gadget->dev.device_data; | |
123 | } | |
124 | ||
ae1f2f0c MV |
125 | static struct usb_ep_ops dwc2_ep_ops = { |
126 | .enable = dwc2_ep_enable, | |
127 | .disable = dwc2_ep_disable, | |
38517a78 | 128 | |
155e740f MV |
129 | .alloc_request = dwc2_alloc_request, |
130 | .free_request = dwc2_free_request, | |
38517a78 | 131 | |
155e740f MV |
132 | .queue = dwc2_queue, |
133 | .dequeue = dwc2_dequeue, | |
38517a78 | 134 | |
f52dd802 | 135 | .set_halt = dwc2_udc_set_halt, |
155e740f MV |
136 | .fifo_status = dwc2_fifo_status, |
137 | .fifo_flush = dwc2_fifo_flush, | |
38517a78 ŁM |
138 | }; |
139 | ||
140 | #define create_proc_files() do {} while (0) | |
141 | #define remove_proc_files() do {} while (0) | |
142 | ||
143 | /***********************************************************/ | |
144 | ||
145 | void __iomem *regs_otg; | |
01472813 | 146 | struct dwc2_usbotg_reg *reg; |
38517a78 | 147 | |
f2ec4e34 ŁM |
148 | bool dfu_usb_get_reset(void) |
149 | { | |
150 | return !!(readl(®->gintsts) & INT_RESET); | |
151 | } | |
152 | ||
b4d5cf0b MV |
153 | __weak void otg_phy_init(struct dwc2_udc *dev) {} |
154 | __weak void otg_phy_off(struct dwc2_udc *dev) {} | |
38517a78 ŁM |
155 | |
156 | /***********************************************************/ | |
157 | ||
be5e4bdc | 158 | #include "dwc2_udc_otg_xfer_dma.c" |
38517a78 ŁM |
159 | |
160 | /* | |
161 | * udc_disable - disable USB device controller | |
162 | */ | |
b4d5cf0b | 163 | static void udc_disable(struct dwc2_udc *dev) |
38517a78 | 164 | { |
f3b05ca5 | 165 | debug_cond(DEBUG_SETUP != 0, "%s: %p\n", __func__, dev); |
38517a78 ŁM |
166 | |
167 | udc_set_address(dev, 0); | |
168 | ||
169 | dev->ep0state = WAIT_FOR_SETUP; | |
170 | dev->gadget.speed = USB_SPEED_UNKNOWN; | |
171 | dev->usb_address = 0; | |
172 | ||
173 | otg_phy_off(dev); | |
174 | } | |
175 | ||
176 | /* | |
177 | * udc_reinit - initialize software state | |
178 | */ | |
b4d5cf0b | 179 | static void udc_reinit(struct dwc2_udc *dev) |
38517a78 ŁM |
180 | { |
181 | unsigned int i; | |
182 | ||
f3b05ca5 | 183 | debug_cond(DEBUG_SETUP != 0, "%s: %p\n", __func__, dev); |
38517a78 ŁM |
184 | |
185 | /* device/ep0 records init */ | |
186 | INIT_LIST_HEAD(&dev->gadget.ep_list); | |
187 | INIT_LIST_HEAD(&dev->gadget.ep0->ep_list); | |
188 | dev->ep0state = WAIT_FOR_SETUP; | |
189 | ||
190 | /* basic endpoint records init */ | |
507e677b | 191 | for (i = 0; i < DWC2_MAX_ENDPOINTS; i++) { |
627d9298 | 192 | struct dwc2_ep *ep = &dev->ep[i]; |
38517a78 ŁM |
193 | |
194 | if (i != 0) | |
195 | list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list); | |
196 | ||
197 | ep->desc = 0; | |
198 | ep->stopped = 0; | |
199 | INIT_LIST_HEAD(&ep->queue); | |
200 | ep->pio_irqs = 0; | |
201 | } | |
202 | ||
203 | /* the rest was statically initialized, and is read-only */ | |
204 | } | |
205 | ||
206 | #define BYTES2MAXP(x) (x / 8) | |
207 | #define MAXP2BYTES(x) (x * 8) | |
208 | ||
209 | /* until it's enabled, this UDC should be completely invisible | |
210 | * to any USB host. | |
211 | */ | |
b4d5cf0b | 212 | static int udc_enable(struct dwc2_udc *dev) |
38517a78 | 213 | { |
f3b05ca5 | 214 | debug_cond(DEBUG_SETUP != 0, "%s: %p\n", __func__, dev); |
38517a78 ŁM |
215 | |
216 | otg_phy_init(dev); | |
481a11c5 | 217 | reconfig_usbd(dev); |
38517a78 | 218 | |
f3b05ca5 | 219 | debug_cond(DEBUG_SETUP != 0, |
06cb6ccd | 220 | "DWC2 USB 2.0 OTG Controller Core Initialized : 0x%x\n", |
38517a78 ŁM |
221 | readl(®->gintmsk)); |
222 | ||
223 | dev->gadget.speed = USB_SPEED_UNKNOWN; | |
224 | ||
225 | return 0; | |
226 | } | |
227 | ||
228 | /* | |
229 | Register entry point for the peripheral controller driver. | |
230 | */ | |
231 | int usb_gadget_register_driver(struct usb_gadget_driver *driver) | |
232 | { | |
b4d5cf0b | 233 | struct dwc2_udc *dev = the_controller; |
38517a78 | 234 | int retval = 0; |
06fa91cd | 235 | unsigned long flags = 0; |
38517a78 | 236 | |
f3b05ca5 | 237 | debug_cond(DEBUG_SETUP != 0, "%s: %s\n", __func__, "no name"); |
38517a78 ŁM |
238 | |
239 | if (!driver | |
240 | || (driver->speed != USB_SPEED_FULL | |
241 | && driver->speed != USB_SPEED_HIGH) | |
242 | || !driver->bind || !driver->disconnect || !driver->setup) | |
243 | return -EINVAL; | |
244 | if (!dev) | |
245 | return -ENODEV; | |
246 | if (dev->driver) | |
247 | return -EBUSY; | |
248 | ||
249 | spin_lock_irqsave(&dev->lock, flags); | |
250 | /* first hook up the driver ... */ | |
251 | dev->driver = driver; | |
252 | spin_unlock_irqrestore(&dev->lock, flags); | |
253 | ||
254 | if (retval) { /* TODO */ | |
255 | printf("target device_add failed, error %d\n", retval); | |
256 | return retval; | |
257 | } | |
258 | ||
259 | retval = driver->bind(&dev->gadget); | |
260 | if (retval) { | |
f3b05ca5 ŁM |
261 | debug_cond(DEBUG_SETUP != 0, |
262 | "%s: bind to driver --> error %d\n", | |
38517a78 ŁM |
263 | dev->gadget.name, retval); |
264 | dev->driver = 0; | |
265 | return retval; | |
266 | } | |
267 | ||
268 | enable_irq(IRQ_OTG); | |
269 | ||
f3b05ca5 ŁM |
270 | debug_cond(DEBUG_SETUP != 0, |
271 | "Registered gadget driver %s\n", dev->gadget.name); | |
38517a78 ŁM |
272 | udc_enable(dev); |
273 | ||
274 | return 0; | |
275 | } | |
276 | ||
277 | /* | |
278 | * Unregister entry point for the peripheral controller driver. | |
279 | */ | |
280 | int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) | |
281 | { | |
b4d5cf0b | 282 | struct dwc2_udc *dev = the_controller; |
06fa91cd | 283 | unsigned long flags = 0; |
38517a78 ŁM |
284 | |
285 | if (!dev) | |
286 | return -ENODEV; | |
287 | if (!driver || driver != dev->driver) | |
288 | return -EINVAL; | |
289 | ||
290 | spin_lock_irqsave(&dev->lock, flags); | |
291 | dev->driver = 0; | |
292 | stop_activity(dev, driver); | |
293 | spin_unlock_irqrestore(&dev->lock, flags); | |
294 | ||
295 | driver->unbind(&dev->gadget); | |
296 | ||
297 | disable_irq(IRQ_OTG); | |
298 | ||
299 | udc_disable(dev); | |
300 | return 0; | |
301 | } | |
302 | ||
303 | /* | |
304 | * done - retire a request; caller blocked irqs | |
305 | */ | |
c056c52b | 306 | static void done(struct dwc2_ep *ep, struct dwc2_request *req, int status) |
38517a78 ŁM |
307 | { |
308 | unsigned int stopped = ep->stopped; | |
309 | ||
ea2d9159 | 310 | debug("%s: %s %p, req = %p, stopped = %d\n", |
38517a78 ŁM |
311 | __func__, ep->ep.name, ep, &req->req, stopped); |
312 | ||
313 | list_del_init(&req->queue); | |
314 | ||
315 | if (likely(req->req.status == -EINPROGRESS)) | |
316 | req->req.status = status; | |
317 | else | |
318 | status = req->req.status; | |
319 | ||
320 | if (status && status != -ESHUTDOWN) { | |
ea2d9159 | 321 | debug("complete %s req %p stat %d len %u/%u\n", |
38517a78 ŁM |
322 | ep->ep.name, &req->req, status, |
323 | req->req.actual, req->req.length); | |
324 | } | |
325 | ||
326 | /* don't modify queue heads during completion callback */ | |
327 | ep->stopped = 1; | |
328 | ||
f3b05ca5 | 329 | #ifdef DEBUG |
38517a78 ŁM |
330 | printf("calling complete callback\n"); |
331 | { | |
332 | int i, len = req->req.length; | |
333 | ||
334 | printf("pkt[%d] = ", req->req.length); | |
335 | if (len > 64) | |
336 | len = 64; | |
337 | for (i = 0; i < len; i++) { | |
338 | printf("%02x", ((u8 *)req->req.buf)[i]); | |
339 | if ((i & 7) == 7) | |
340 | printf(" "); | |
341 | } | |
342 | printf("\n"); | |
343 | } | |
344 | #endif | |
345 | spin_unlock(&ep->dev->lock); | |
346 | req->req.complete(&ep->ep, &req->req); | |
347 | spin_lock(&ep->dev->lock); | |
348 | ||
ea2d9159 | 349 | debug("callback completed\n"); |
38517a78 ŁM |
350 | |
351 | ep->stopped = stopped; | |
352 | } | |
353 | ||
354 | /* | |
355 | * nuke - dequeue ALL requests | |
356 | */ | |
627d9298 | 357 | static void nuke(struct dwc2_ep *ep, int status) |
38517a78 | 358 | { |
c056c52b | 359 | struct dwc2_request *req; |
38517a78 | 360 | |
ea2d9159 | 361 | debug("%s: %s %p\n", __func__, ep->ep.name, ep); |
38517a78 ŁM |
362 | |
363 | /* called with irqs blocked */ | |
364 | while (!list_empty(&ep->queue)) { | |
c056c52b | 365 | req = list_entry(ep->queue.next, struct dwc2_request, queue); |
38517a78 ŁM |
366 | done(ep, req, status); |
367 | } | |
368 | } | |
369 | ||
b4d5cf0b | 370 | static void stop_activity(struct dwc2_udc *dev, |
38517a78 ŁM |
371 | struct usb_gadget_driver *driver) |
372 | { | |
373 | int i; | |
374 | ||
375 | /* don't disconnect drivers more than once */ | |
376 | if (dev->gadget.speed == USB_SPEED_UNKNOWN) | |
377 | driver = 0; | |
378 | dev->gadget.speed = USB_SPEED_UNKNOWN; | |
379 | ||
380 | /* prevent new request submissions, kill any outstanding requests */ | |
507e677b | 381 | for (i = 0; i < DWC2_MAX_ENDPOINTS; i++) { |
627d9298 | 382 | struct dwc2_ep *ep = &dev->ep[i]; |
38517a78 ŁM |
383 | ep->stopped = 1; |
384 | nuke(ep, -ESHUTDOWN); | |
385 | } | |
386 | ||
387 | /* report disconnect; the driver is already quiesced */ | |
388 | if (driver) { | |
389 | spin_unlock(&dev->lock); | |
390 | driver->disconnect(&dev->gadget); | |
391 | spin_lock(&dev->lock); | |
392 | } | |
393 | ||
394 | /* re-init driver-visible data structures */ | |
395 | udc_reinit(dev); | |
396 | } | |
397 | ||
b4d5cf0b | 398 | static void reconfig_usbd(struct dwc2_udc *dev) |
38517a78 ŁM |
399 | { |
400 | /* 2. Soft-reset OTG Core and then unreset again. */ | |
401 | int i; | |
402 | unsigned int uTemp = writel(CORE_SOFT_RESET, ®->grstctl); | |
481a11c5 | 403 | uint32_t dflt_gusbcfg; |
47117882 | 404 | uint32_t rx_fifo_sz, tx_fifo_sz, np_tx_fifo_sz; |
38517a78 | 405 | |
ea2d9159 | 406 | debug("Reseting OTG controller\n"); |
38517a78 | 407 | |
481a11c5 MV |
408 | dflt_gusbcfg = |
409 | 0<<15 /* PHY Low Power Clock sel*/ | |
38517a78 ŁM |
410 | |1<<14 /* Non-Periodic TxFIFO Rewind Enable*/ |
411 | |0x5<<10 /* Turnaround time*/ | |
412 | |0<<9 | 0<<8 /* [0:HNP disable,1:HNP enable][ 0:SRP disable*/ | |
413 | /* 1:SRP enable] H1= 1,1*/ | |
414 | |0<<7 /* Ulpi DDR sel*/ | |
415 | |0<<6 /* 0: high speed utmi+, 1: full speed serial*/ | |
416 | |0<<4 /* 0: utmi+, 1:ulpi*/ | |
f221db0e SR |
417 | #ifdef CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8 |
418 | |0<<3 /* phy i/f 0:8bit, 1:16bit*/ | |
419 | #else | |
38517a78 | 420 | |1<<3 /* phy i/f 0:8bit, 1:16bit*/ |
f221db0e | 421 | #endif |
481a11c5 MV |
422 | |0x7<<0; /* HS/FS Timeout**/ |
423 | ||
424 | if (dev->pdata->usb_gusbcfg) | |
425 | dflt_gusbcfg = dev->pdata->usb_gusbcfg; | |
426 | ||
427 | writel(dflt_gusbcfg, ®->gusbcfg); | |
38517a78 ŁM |
428 | |
429 | /* 3. Put the OTG device core in the disconnected state.*/ | |
430 | uTemp = readl(®->dctl); | |
431 | uTemp |= SOFT_DISCONNECT; | |
432 | writel(uTemp, ®->dctl); | |
433 | ||
434 | udelay(20); | |
435 | ||
436 | /* 4. Make the OTG device core exit from the disconnected state.*/ | |
437 | uTemp = readl(®->dctl); | |
438 | uTemp = uTemp & ~SOFT_DISCONNECT; | |
439 | writel(uTemp, ®->dctl); | |
440 | ||
441 | /* 5. Configure OTG Core to initial settings of device mode.*/ | |
442 | /* [][1: full speed(30Mhz) 0:high speed]*/ | |
443 | writel(EP_MISS_CNT(1) | DEV_SPEED_HIGH_SPEED_20, ®->dcfg); | |
444 | ||
445 | mdelay(1); | |
446 | ||
447 | /* 6. Unmask the core interrupts*/ | |
448 | writel(GINTMSK_INIT, ®->gintmsk); | |
449 | ||
450 | /* 7. Set NAK bit of EP0, EP1, EP2*/ | |
451 | writel(DEPCTL_EPDIS|DEPCTL_SNAK, ®->out_endp[EP0_CON].doepctl); | |
452 | writel(DEPCTL_EPDIS|DEPCTL_SNAK, ®->in_endp[EP0_CON].diepctl); | |
453 | ||
507e677b | 454 | for (i = 1; i < DWC2_MAX_ENDPOINTS; i++) { |
38517a78 ŁM |
455 | writel(DEPCTL_EPDIS|DEPCTL_SNAK, ®->out_endp[i].doepctl); |
456 | writel(DEPCTL_EPDIS|DEPCTL_SNAK, ®->in_endp[i].diepctl); | |
457 | } | |
458 | ||
459 | /* 8. Unmask EPO interrupts*/ | |
460 | writel(((1 << EP0_CON) << DAINT_OUT_BIT) | |
461 | | (1 << EP0_CON), ®->daintmsk); | |
462 | ||
463 | /* 9. Unmask device OUT EP common interrupts*/ | |
464 | writel(DOEPMSK_INIT, ®->doepmsk); | |
465 | ||
466 | /* 10. Unmask device IN EP common interrupts*/ | |
467 | writel(DIEPMSK_INIT, ®->diepmsk); | |
468 | ||
47117882 XZ |
469 | rx_fifo_sz = RX_FIFO_SIZE; |
470 | np_tx_fifo_sz = NPTX_FIFO_SIZE; | |
471 | tx_fifo_sz = PTX_FIFO_SIZE; | |
472 | ||
473 | if (dev->pdata->rx_fifo_sz) | |
474 | rx_fifo_sz = dev->pdata->rx_fifo_sz; | |
475 | if (dev->pdata->np_tx_fifo_sz) | |
476 | np_tx_fifo_sz = dev->pdata->np_tx_fifo_sz; | |
477 | if (dev->pdata->tx_fifo_sz) | |
478 | tx_fifo_sz = dev->pdata->tx_fifo_sz; | |
479 | ||
38517a78 | 480 | /* 11. Set Rx FIFO Size (in 32-bit words) */ |
47117882 | 481 | writel(rx_fifo_sz, ®->grxfsiz); |
38517a78 ŁM |
482 | |
483 | /* 12. Set Non Periodic Tx FIFO Size */ | |
47117882 | 484 | writel((np_tx_fifo_sz << 16) | rx_fifo_sz, |
38517a78 ŁM |
485 | ®->gnptxfsiz); |
486 | ||
507e677b | 487 | for (i = 1; i < DWC2_MAX_HW_ENDPOINTS; i++) |
47117882 XZ |
488 | writel((rx_fifo_sz + np_tx_fifo_sz + tx_fifo_sz*(i-1)) | |
489 | tx_fifo_sz << 16, ®->dieptxf[i-1]); | |
38517a78 ŁM |
490 | |
491 | /* Flush the RX FIFO */ | |
492 | writel(RX_FIFO_FLUSH, ®->grstctl); | |
493 | while (readl(®->grstctl) & RX_FIFO_FLUSH) | |
507e677b | 494 | debug("%s: waiting for DWC2_UDC_OTG_GRSTCTL\n", __func__); |
38517a78 ŁM |
495 | |
496 | /* Flush all the Tx FIFO's */ | |
497 | writel(TX_FIFO_FLUSH_ALL, ®->grstctl); | |
498 | writel(TX_FIFO_FLUSH_ALL | TX_FIFO_FLUSH, ®->grstctl); | |
499 | while (readl(®->grstctl) & TX_FIFO_FLUSH) | |
507e677b | 500 | debug("%s: waiting for DWC2_UDC_OTG_GRSTCTL\n", __func__); |
38517a78 ŁM |
501 | |
502 | /* 13. Clear NAK bit of EP0, EP1, EP2*/ | |
503 | /* For Slave mode*/ | |
504 | /* EP0: Control OUT */ | |
505 | writel(DEPCTL_EPDIS | DEPCTL_CNAK, | |
506 | ®->out_endp[EP0_CON].doepctl); | |
507 | ||
508 | /* 14. Initialize OTG Link Core.*/ | |
509 | writel(GAHBCFG_INIT, ®->gahbcfg); | |
510 | } | |
511 | ||
b4d5cf0b | 512 | static void set_max_pktsize(struct dwc2_udc *dev, enum usb_device_speed speed) |
38517a78 ŁM |
513 | { |
514 | unsigned int ep_ctrl; | |
515 | int i; | |
516 | ||
517 | if (speed == USB_SPEED_HIGH) { | |
518 | ep0_fifo_size = 64; | |
519 | ep_fifo_size = 512; | |
520 | ep_fifo_size2 = 1024; | |
521 | dev->gadget.speed = USB_SPEED_HIGH; | |
522 | } else { | |
523 | ep0_fifo_size = 64; | |
524 | ep_fifo_size = 64; | |
525 | ep_fifo_size2 = 64; | |
526 | dev->gadget.speed = USB_SPEED_FULL; | |
527 | } | |
528 | ||
529 | dev->ep[0].ep.maxpacket = ep0_fifo_size; | |
507e677b | 530 | for (i = 1; i < DWC2_MAX_ENDPOINTS; i++) |
38517a78 ŁM |
531 | dev->ep[i].ep.maxpacket = ep_fifo_size; |
532 | ||
533 | /* EP0 - Control IN (64 bytes)*/ | |
534 | ep_ctrl = readl(®->in_endp[EP0_CON].diepctl); | |
535 | writel(ep_ctrl|(0<<0), ®->in_endp[EP0_CON].diepctl); | |
536 | ||
537 | /* EP0 - Control OUT (64 bytes)*/ | |
538 | ep_ctrl = readl(®->out_endp[EP0_CON].doepctl); | |
539 | writel(ep_ctrl|(0<<0), ®->out_endp[EP0_CON].doepctl); | |
540 | } | |
541 | ||
ae1f2f0c | 542 | static int dwc2_ep_enable(struct usb_ep *_ep, |
38517a78 ŁM |
543 | const struct usb_endpoint_descriptor *desc) |
544 | { | |
627d9298 | 545 | struct dwc2_ep *ep; |
b4d5cf0b | 546 | struct dwc2_udc *dev; |
06fa91cd | 547 | unsigned long flags = 0; |
38517a78 | 548 | |
ea2d9159 | 549 | debug("%s: %p\n", __func__, _ep); |
38517a78 | 550 | |
627d9298 | 551 | ep = container_of(_ep, struct dwc2_ep, ep); |
38517a78 ŁM |
552 | if (!_ep || !desc || ep->desc || _ep->name == ep0name |
553 | || desc->bDescriptorType != USB_DT_ENDPOINT | |
554 | || ep->bEndpointAddress != desc->bEndpointAddress | |
b2fb47f1 TR |
555 | || ep_maxpacket(ep) < |
556 | le16_to_cpu(get_unaligned(&desc->wMaxPacketSize))) { | |
38517a78 | 557 | |
ea2d9159 | 558 | debug("%s: bad ep or descriptor\n", __func__); |
38517a78 ŁM |
559 | return -EINVAL; |
560 | } | |
561 | ||
562 | /* xfer types must match, except that interrupt ~= bulk */ | |
563 | if (ep->bmAttributes != desc->bmAttributes | |
564 | && ep->bmAttributes != USB_ENDPOINT_XFER_BULK | |
565 | && desc->bmAttributes != USB_ENDPOINT_XFER_INT) { | |
566 | ||
ea2d9159 | 567 | debug("%s: %s type mismatch\n", __func__, _ep->name); |
38517a78 ŁM |
568 | return -EINVAL; |
569 | } | |
570 | ||
571 | /* hardware _could_ do smaller, but driver doesn't */ | |
8c9b4d55 FW |
572 | if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK && |
573 | le16_to_cpu(get_unaligned(&desc->wMaxPacketSize)) > | |
b2fb47f1 | 574 | ep_maxpacket(ep)) || !get_unaligned(&desc->wMaxPacketSize)) { |
38517a78 | 575 | |
ea2d9159 | 576 | debug("%s: bad %s maxpacket\n", __func__, _ep->name); |
38517a78 ŁM |
577 | return -ERANGE; |
578 | } | |
579 | ||
580 | dev = ep->dev; | |
581 | if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) { | |
582 | ||
ea2d9159 | 583 | debug("%s: bogus device state\n", __func__); |
38517a78 ŁM |
584 | return -ESHUTDOWN; |
585 | } | |
586 | ||
587 | ep->stopped = 0; | |
588 | ep->desc = desc; | |
589 | ep->pio_irqs = 0; | |
b2fb47f1 | 590 | ep->ep.maxpacket = le16_to_cpu(get_unaligned(&desc->wMaxPacketSize)); |
38517a78 ŁM |
591 | |
592 | /* Reset halt state */ | |
f52dd802 MV |
593 | dwc2_udc_set_nak(ep); |
594 | dwc2_udc_set_halt(_ep, 0); | |
38517a78 ŁM |
595 | |
596 | spin_lock_irqsave(&ep->dev->lock, flags); | |
f52dd802 | 597 | dwc2_udc_ep_activate(ep); |
38517a78 ŁM |
598 | spin_unlock_irqrestore(&ep->dev->lock, flags); |
599 | ||
ea2d9159 | 600 | debug("%s: enabled %s, stopped = %d, maxpacket = %d\n", |
38517a78 ŁM |
601 | __func__, _ep->name, ep->stopped, ep->ep.maxpacket); |
602 | return 0; | |
603 | } | |
604 | ||
605 | /* | |
606 | * Disable EP | |
607 | */ | |
ae1f2f0c | 608 | static int dwc2_ep_disable(struct usb_ep *_ep) |
38517a78 | 609 | { |
627d9298 | 610 | struct dwc2_ep *ep; |
06fa91cd | 611 | unsigned long flags = 0; |
38517a78 | 612 | |
ea2d9159 | 613 | debug("%s: %p\n", __func__, _ep); |
38517a78 | 614 | |
627d9298 | 615 | ep = container_of(_ep, struct dwc2_ep, ep); |
38517a78 | 616 | if (!_ep || !ep->desc) { |
ea2d9159 | 617 | debug("%s: %s not enabled\n", __func__, |
38517a78 ŁM |
618 | _ep ? ep->ep.name : NULL); |
619 | return -EINVAL; | |
620 | } | |
621 | ||
622 | spin_lock_irqsave(&ep->dev->lock, flags); | |
623 | ||
624 | /* Nuke all pending requests */ | |
625 | nuke(ep, -ESHUTDOWN); | |
626 | ||
627 | ep->desc = 0; | |
628 | ep->stopped = 1; | |
629 | ||
630 | spin_unlock_irqrestore(&ep->dev->lock, flags); | |
631 | ||
ea2d9159 | 632 | debug("%s: disabled %s\n", __func__, _ep->name); |
38517a78 ŁM |
633 | return 0; |
634 | } | |
635 | ||
155e740f | 636 | static struct usb_request *dwc2_alloc_request(struct usb_ep *ep, |
38517a78 ŁM |
637 | gfp_t gfp_flags) |
638 | { | |
c056c52b | 639 | struct dwc2_request *req; |
38517a78 | 640 | |
ea2d9159 | 641 | debug("%s: %s %p\n", __func__, ep->name, ep); |
38517a78 | 642 | |
6777a3cf | 643 | req = memalign(CONFIG_SYS_CACHELINE_SIZE, sizeof(*req)); |
38517a78 ŁM |
644 | if (!req) |
645 | return 0; | |
646 | ||
647 | memset(req, 0, sizeof *req); | |
648 | INIT_LIST_HEAD(&req->queue); | |
649 | ||
650 | return &req->req; | |
651 | } | |
652 | ||
155e740f | 653 | static void dwc2_free_request(struct usb_ep *ep, struct usb_request *_req) |
38517a78 | 654 | { |
c056c52b | 655 | struct dwc2_request *req; |
38517a78 | 656 | |
ea2d9159 | 657 | debug("%s: %p\n", __func__, ep); |
38517a78 | 658 | |
c056c52b | 659 | req = container_of(_req, struct dwc2_request, req); |
38517a78 ŁM |
660 | WARN_ON(!list_empty(&req->queue)); |
661 | kfree(req); | |
662 | } | |
663 | ||
664 | /* dequeue JUST ONE request */ | |
155e740f | 665 | static int dwc2_dequeue(struct usb_ep *_ep, struct usb_request *_req) |
38517a78 | 666 | { |
627d9298 | 667 | struct dwc2_ep *ep; |
c056c52b | 668 | struct dwc2_request *req; |
06fa91cd | 669 | unsigned long flags = 0; |
38517a78 | 670 | |
ea2d9159 | 671 | debug("%s: %p\n", __func__, _ep); |
38517a78 | 672 | |
627d9298 | 673 | ep = container_of(_ep, struct dwc2_ep, ep); |
38517a78 ŁM |
674 | if (!_ep || ep->ep.name == ep0name) |
675 | return -EINVAL; | |
676 | ||
677 | spin_lock_irqsave(&ep->dev->lock, flags); | |
678 | ||
679 | /* make sure it's actually queued on this endpoint */ | |
680 | list_for_each_entry(req, &ep->queue, queue) { | |
681 | if (&req->req == _req) | |
682 | break; | |
683 | } | |
684 | if (&req->req != _req) { | |
685 | spin_unlock_irqrestore(&ep->dev->lock, flags); | |
686 | return -EINVAL; | |
687 | } | |
688 | ||
689 | done(ep, req, -ECONNRESET); | |
690 | ||
691 | spin_unlock_irqrestore(&ep->dev->lock, flags); | |
692 | return 0; | |
693 | } | |
694 | ||
695 | /* | |
696 | * Return bytes in EP FIFO | |
697 | */ | |
155e740f | 698 | static int dwc2_fifo_status(struct usb_ep *_ep) |
38517a78 ŁM |
699 | { |
700 | int count = 0; | |
627d9298 | 701 | struct dwc2_ep *ep; |
38517a78 | 702 | |
627d9298 | 703 | ep = container_of(_ep, struct dwc2_ep, ep); |
38517a78 | 704 | if (!_ep) { |
ea2d9159 | 705 | debug("%s: bad ep\n", __func__); |
38517a78 ŁM |
706 | return -ENODEV; |
707 | } | |
708 | ||
ea2d9159 | 709 | debug("%s: %d\n", __func__, ep_index(ep)); |
38517a78 ŁM |
710 | |
711 | /* LPD can't report unclaimed bytes from IN fifos */ | |
712 | if (ep_is_in(ep)) | |
713 | return -EOPNOTSUPP; | |
714 | ||
715 | return count; | |
716 | } | |
717 | ||
718 | /* | |
719 | * Flush EP FIFO | |
720 | */ | |
155e740f | 721 | static void dwc2_fifo_flush(struct usb_ep *_ep) |
38517a78 | 722 | { |
627d9298 | 723 | struct dwc2_ep *ep; |
38517a78 | 724 | |
627d9298 | 725 | ep = container_of(_ep, struct dwc2_ep, ep); |
38517a78 | 726 | if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) { |
ea2d9159 | 727 | debug("%s: bad ep\n", __func__); |
38517a78 ŁM |
728 | return; |
729 | } | |
730 | ||
ea2d9159 | 731 | debug("%s: %d\n", __func__, ep_index(ep)); |
38517a78 ŁM |
732 | } |
733 | ||
f52dd802 | 734 | static const struct usb_gadget_ops dwc2_udc_ops = { |
38517a78 ŁM |
735 | /* current versions must always be self-powered */ |
736 | }; | |
737 | ||
b4d5cf0b | 738 | static struct dwc2_udc memory = { |
38517a78 ŁM |
739 | .usb_address = 0, |
740 | .gadget = { | |
f52dd802 | 741 | .ops = &dwc2_udc_ops, |
38517a78 ŁM |
742 | .ep0 = &memory.ep[0].ep, |
743 | .name = driver_name, | |
744 | }, | |
745 | ||
746 | /* control endpoint */ | |
747 | .ep[0] = { | |
748 | .ep = { | |
749 | .name = ep0name, | |
ae1f2f0c | 750 | .ops = &dwc2_ep_ops, |
38517a78 ŁM |
751 | .maxpacket = EP0_FIFO_SIZE, |
752 | }, | |
753 | .dev = &memory, | |
754 | ||
755 | .bEndpointAddress = 0, | |
756 | .bmAttributes = 0, | |
757 | ||
758 | .ep_type = ep_control, | |
759 | }, | |
760 | ||
761 | /* first group of endpoints */ | |
762 | .ep[1] = { | |
763 | .ep = { | |
764 | .name = "ep1in-bulk", | |
ae1f2f0c | 765 | .ops = &dwc2_ep_ops, |
38517a78 ŁM |
766 | .maxpacket = EP_FIFO_SIZE, |
767 | }, | |
768 | .dev = &memory, | |
769 | ||
770 | .bEndpointAddress = USB_DIR_IN | 1, | |
771 | .bmAttributes = USB_ENDPOINT_XFER_BULK, | |
772 | ||
773 | .ep_type = ep_bulk_out, | |
774 | .fifo_num = 1, | |
775 | }, | |
776 | ||
777 | .ep[2] = { | |
778 | .ep = { | |
779 | .name = "ep2out-bulk", | |
ae1f2f0c | 780 | .ops = &dwc2_ep_ops, |
38517a78 ŁM |
781 | .maxpacket = EP_FIFO_SIZE, |
782 | }, | |
783 | .dev = &memory, | |
784 | ||
785 | .bEndpointAddress = USB_DIR_OUT | 2, | |
786 | .bmAttributes = USB_ENDPOINT_XFER_BULK, | |
787 | ||
788 | .ep_type = ep_bulk_in, | |
789 | .fifo_num = 2, | |
790 | }, | |
791 | ||
792 | .ep[3] = { | |
793 | .ep = { | |
794 | .name = "ep3in-int", | |
ae1f2f0c | 795 | .ops = &dwc2_ep_ops, |
38517a78 ŁM |
796 | .maxpacket = EP_FIFO_SIZE, |
797 | }, | |
798 | .dev = &memory, | |
799 | ||
800 | .bEndpointAddress = USB_DIR_IN | 3, | |
801 | .bmAttributes = USB_ENDPOINT_XFER_INT, | |
802 | ||
803 | .ep_type = ep_interrupt, | |
804 | .fifo_num = 3, | |
805 | }, | |
806 | }; | |
807 | ||
808 | /* | |
809 | * probe - binds to the platform device | |
810 | */ | |
811 | ||
a4bb9b36 | 812 | int dwc2_udc_probe(struct dwc2_plat_otg_data *pdata) |
38517a78 | 813 | { |
b4d5cf0b | 814 | struct dwc2_udc *dev = &memory; |
e0059eae | 815 | int retval = 0; |
38517a78 | 816 | |
ea2d9159 | 817 | debug("%s: %p\n", __func__, pdata); |
38517a78 ŁM |
818 | |
819 | dev->pdata = pdata; | |
820 | ||
01472813 | 821 | reg = (struct dwc2_usbotg_reg *)pdata->regs_otg; |
38517a78 ŁM |
822 | |
823 | /* regs_otg = (void *)pdata->regs_otg; */ | |
824 | ||
825 | dev->gadget.is_dualspeed = 1; /* Hack only*/ | |
826 | dev->gadget.is_otg = 0; | |
827 | dev->gadget.is_a_peripheral = 0; | |
828 | dev->gadget.b_hnp_enable = 0; | |
829 | dev->gadget.a_hnp_support = 0; | |
830 | dev->gadget.a_alt_hnp_support = 0; | |
831 | ||
832 | the_controller = dev; | |
833 | ||
e0059eae ŁM |
834 | usb_ctrl = memalign(CONFIG_SYS_CACHELINE_SIZE, |
835 | ROUND(sizeof(struct usb_ctrlrequest), | |
836 | CONFIG_SYS_CACHELINE_SIZE)); | |
837 | if (!usb_ctrl) { | |
9b643e31 | 838 | pr_err("No memory available for UDC!\n"); |
e0059eae | 839 | return -ENOMEM; |
38517a78 | 840 | } |
e0059eae ŁM |
841 | |
842 | usb_ctrl_dma_addr = (dma_addr_t) usb_ctrl; | |
38517a78 ŁM |
843 | |
844 | udc_reinit(dev); | |
845 | ||
846 | return retval; | |
847 | } | |
848 | ||
2d48aa69 | 849 | int usb_gadget_handle_interrupts(int index) |
38517a78 ŁM |
850 | { |
851 | u32 intr_status = readl(®->gintsts); | |
852 | u32 gintmsk = readl(®->gintmsk); | |
853 | ||
854 | if (intr_status & gintmsk) | |
f52dd802 | 855 | return dwc2_udc_irq(1, (void *)the_controller); |
38517a78 ŁM |
856 | return 0; |
857 | } |