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232c150a WD |
1 | /* |
2 | * (C) Copyright 2003 | |
3 | * Gerry Hamel, geh@ti.com, Texas Instruments | |
4 | * | |
5 | * Based on | |
6 | * linux/drivers/usb/device/bi/omap.c | |
7 | * TI OMAP1510 USB bus interface driver | |
8 | * | |
9 | * Author: MontaVista Software, Inc. | |
10 | * source@mvista.com | |
11 | * (C) Copyright 2002 | |
12 | * | |
1a459660 | 13 | * SPDX-License-Identifier: GPL-2.0+ |
232c150a WD |
14 | */ |
15 | ||
16 | #include <common.h> | |
232c150a | 17 | #include <asm/io.h> |
bdda519d | 18 | #ifdef CONFIG_OMAP_SX1 |
232c150a | 19 | #include <i2c.h> |
bdda519d | 20 | #endif |
2731b9a8 JCPV |
21 | #include <usbdevice.h> |
22 | #include <usb/omap1510_udc.h> | |
232c150a | 23 | |
2731b9a8 | 24 | #include "ep0.h" |
232c150a WD |
25 | |
26 | ||
efa329cb | 27 | #define UDC_INIT_MDELAY 80 /* Device settle delay */ |
232c150a WD |
28 | #define UDC_MAX_ENDPOINTS 31 /* Number of endpoints on this UDC */ |
29 | ||
30 | /* Some kind of debugging output... */ | |
31 | #if 1 | |
32 | #define UDCDBG(str) | |
33 | #define UDCDBGA(fmt,args...) | |
34 | #else /* The bugs still exists... */ | |
35 | #define UDCDBG(str) serial_printf("[%s] %s:%d: " str "\n", __FILE__,__FUNCTION__,__LINE__) | |
36 | #define UDCDBGA(fmt,args...) serial_printf("[%s] %s:%d: " fmt "\n", __FILE__,__FUNCTION__,__LINE__, ##args) | |
37 | #endif | |
38 | ||
39 | #if 1 | |
40 | #define UDCREG(name) | |
41 | #define UDCREGL(name) | |
42 | #else /* The bugs still exists... */ | |
43 | #define UDCREG(name) serial_printf("%s():%d: %s[%08x]=%.4x\n",__FUNCTION__,__LINE__, (#name), name, inw(name)) /* For 16-bit regs */ | |
44 | #define UDCREGL(name) serial_printf("%s():%d: %s[%08x]=%.8x\n",__FUNCTION__,__LINE__, (#name), name, inl(name)) /* For 32-bit regs */ | |
45 | #endif | |
46 | ||
47 | ||
48 | static struct urb *ep0_urb = NULL; | |
49 | ||
50 | static struct usb_device_instance *udc_device; /* Used in interrupt handler */ | |
51 | static u16 udc_devstat = 0; /* UDC status (DEVSTAT) */ | |
52 | static u32 udc_interrupts = 0; | |
53 | ||
54 | static void udc_stall_ep (unsigned int ep_addr); | |
55 | ||
56 | ||
57 | static struct usb_endpoint_instance *omap1510_find_ep (int ep) | |
58 | { | |
59 | int i; | |
60 | ||
61 | for (i = 0; i < udc_device->bus->max_endpoints; i++) { | |
62 | if (udc_device->bus->endpoint_array[i].endpoint_address == ep) | |
63 | return &udc_device->bus->endpoint_array[i]; | |
64 | } | |
65 | return NULL; | |
66 | } | |
67 | ||
68 | /* ************************************************************************** */ | |
69 | /* IO | |
70 | */ | |
71 | ||
72 | /* | |
73 | * omap1510_prepare_endpoint_for_rx | |
74 | * | |
75 | * This function implements TRM Figure 14-11. | |
76 | * | |
77 | * The endpoint to prepare for transfer is specified as a physical endpoint | |
78 | * number. For OUT (rx) endpoints 1 through 15, the corresponding endpoint | |
79 | * configuration register is checked to see if the endpoint is ISO or not. | |
80 | * If the OUT endpoint is valid and is non-ISO then its FIFO is enabled. | |
81 | * No action is taken for endpoint 0 or for IN (tx) endpoints 16 through 30. | |
82 | */ | |
83 | static void omap1510_prepare_endpoint_for_rx (int ep_addr) | |
84 | { | |
85 | int ep_num = ep_addr & USB_ENDPOINT_NUMBER_MASK; | |
86 | ||
87 | UDCDBGA ("omap1510_prepare_endpoint %x", ep_addr); | |
88 | if (((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_OUT)) { | |
89 | if ((inw (UDC_EP_RX (ep_num)) & | |
90 | (UDC_EPn_RX_Valid | UDC_EPn_RX_Iso)) == | |
91 | UDC_EPn_RX_Valid) { | |
92 | /* rx endpoint is valid, non-ISO, so enable its FIFO */ | |
93 | outw (UDC_EP_Sel | ep_num, UDC_EP_NUM); | |
94 | outw (UDC_Set_FIFO_En, UDC_CTRL); | |
95 | outw (0, UDC_EP_NUM); | |
96 | } | |
97 | } | |
98 | } | |
99 | ||
100 | /* omap1510_configure_endpoints | |
101 | * | |
102 | * This function implements TRM Figure 14-10. | |
103 | */ | |
104 | static void omap1510_configure_endpoints (struct usb_device_instance *device) | |
105 | { | |
106 | int ep; | |
107 | struct usb_bus_instance *bus; | |
108 | struct usb_endpoint_instance *endpoint; | |
109 | unsigned short ep_ptr; | |
110 | unsigned short ep_size; | |
111 | unsigned short ep_isoc; | |
112 | unsigned short ep_doublebuffer; | |
113 | int ep_addr; | |
114 | int packet_size; | |
115 | int buffer_size; | |
116 | int attributes; | |
117 | ||
118 | bus = device->bus; | |
119 | ||
120 | /* There is a dedicated 2048 byte buffer for USB packets that may be | |
121 | * arbitrarily partitioned among the endpoints on 8-byte boundaries. | |
122 | * The first 8 bytes are reserved for receiving setup packets on | |
123 | * endpoint 0. | |
124 | */ | |
125 | ep_ptr = 8; /* reserve the first 8 bytes for the setup fifo */ | |
126 | ||
127 | for (ep = 0; ep < bus->max_endpoints; ep++) { | |
128 | endpoint = bus->endpoint_array + ep; | |
129 | ep_addr = endpoint->endpoint_address; | |
130 | if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) { | |
131 | /* IN endpoint */ | |
132 | packet_size = endpoint->tx_packetSize; | |
133 | attributes = endpoint->tx_attributes; | |
134 | } else { | |
135 | /* OUT endpoint */ | |
136 | packet_size = endpoint->rcv_packetSize; | |
137 | attributes = endpoint->rcv_attributes; | |
138 | } | |
139 | ||
140 | switch (packet_size) { | |
141 | case 0: | |
142 | ep_size = 0; | |
143 | break; | |
144 | case 8: | |
145 | ep_size = 0; | |
146 | break; | |
147 | case 16: | |
148 | ep_size = 1; | |
149 | break; | |
150 | case 32: | |
151 | ep_size = 2; | |
152 | break; | |
153 | case 64: | |
154 | ep_size = 3; | |
155 | break; | |
156 | case 128: | |
157 | ep_size = 4; | |
158 | break; | |
159 | case 256: | |
160 | ep_size = 5; | |
161 | break; | |
162 | case 512: | |
163 | ep_size = 6; | |
164 | break; | |
165 | default: | |
166 | UDCDBGA ("ep 0x%02x has bad packet size %d", | |
167 | ep_addr, packet_size); | |
168 | packet_size = 0; | |
169 | ep_size = 0; | |
170 | break; | |
171 | } | |
172 | ||
173 | switch (attributes & USB_ENDPOINT_XFERTYPE_MASK) { | |
174 | case USB_ENDPOINT_XFER_CONTROL: | |
175 | case USB_ENDPOINT_XFER_BULK: | |
176 | case USB_ENDPOINT_XFER_INT: | |
177 | default: | |
178 | /* A non-isochronous endpoint may optionally be | |
179 | * double-buffered. For now we disable | |
180 | * double-buffering. | |
181 | */ | |
182 | ep_doublebuffer = 0; | |
183 | ep_isoc = 0; | |
184 | if (packet_size > 64) | |
185 | packet_size = 0; | |
186 | if (!ep || !ep_doublebuffer) | |
187 | buffer_size = packet_size; | |
188 | else | |
189 | buffer_size = packet_size * 2; | |
190 | break; | |
191 | case USB_ENDPOINT_XFER_ISOC: | |
192 | /* Isochronous endpoints are always double- | |
193 | * buffered, but the double-buffering bit | |
194 | * in the endpoint configuration register | |
195 | * becomes the msb of the endpoint size so we | |
196 | * set the double-buffering flag to zero. | |
197 | */ | |
198 | ep_doublebuffer = 0; | |
199 | ep_isoc = 1; | |
200 | buffer_size = packet_size * 2; | |
201 | break; | |
202 | } | |
203 | ||
204 | /* check to see if our packet buffer RAM is exhausted */ | |
205 | if ((ep_ptr + buffer_size) > 2048) { | |
206 | UDCDBGA ("out of packet RAM for ep 0x%02x buf size %d", ep_addr, buffer_size); | |
207 | buffer_size = packet_size = 0; | |
208 | } | |
209 | ||
210 | /* force a default configuration for endpoint 0 since it is | |
211 | * always enabled | |
212 | */ | |
213 | if (!ep && ((packet_size < 8) || (packet_size > 64))) { | |
214 | buffer_size = packet_size = 64; | |
215 | ep_size = 3; | |
216 | } | |
217 | ||
218 | if (!ep) { | |
219 | /* configure endpoint 0 */ | |
220 | outw ((ep_size << 12) | (ep_ptr >> 3), UDC_EP0); | |
221 | /*UDCDBGA("ep 0 buffer offset 0x%03x packet size 0x%03x", */ | |
222 | /* ep_ptr, packet_size); */ | |
223 | } else if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) { | |
224 | /* IN endpoint */ | |
225 | if (packet_size) { | |
226 | outw ((1 << 15) | (ep_doublebuffer << 14) | | |
227 | (ep_size << 12) | (ep_isoc << 11) | | |
228 | (ep_ptr >> 3), | |
229 | UDC_EP_TX (ep_addr & | |
230 | USB_ENDPOINT_NUMBER_MASK)); | |
231 | UDCDBGA ("IN ep %d buffer offset 0x%03x" | |
232 | " packet size 0x%03x", | |
233 | ep_addr & USB_ENDPOINT_NUMBER_MASK, | |
234 | ep_ptr, packet_size); | |
235 | } else { | |
236 | outw (0, | |
237 | UDC_EP_TX (ep_addr & | |
238 | USB_ENDPOINT_NUMBER_MASK)); | |
239 | } | |
240 | } else { | |
241 | /* OUT endpoint */ | |
242 | if (packet_size) { | |
243 | outw ((1 << 15) | (ep_doublebuffer << 14) | | |
244 | (ep_size << 12) | (ep_isoc << 11) | | |
245 | (ep_ptr >> 3), | |
246 | UDC_EP_RX (ep_addr & | |
247 | USB_ENDPOINT_NUMBER_MASK)); | |
248 | UDCDBGA ("OUT ep %d buffer offset 0x%03x" | |
249 | " packet size 0x%03x", | |
250 | ep_addr & USB_ENDPOINT_NUMBER_MASK, | |
251 | ep_ptr, packet_size); | |
252 | } else { | |
253 | outw (0, | |
254 | UDC_EP_RX (ep_addr & | |
255 | USB_ENDPOINT_NUMBER_MASK)); | |
256 | } | |
257 | } | |
258 | ep_ptr += buffer_size; | |
259 | } | |
260 | } | |
261 | ||
262 | /* omap1510_deconfigure_device | |
263 | * | |
264 | * This function balances omap1510_configure_device. | |
265 | */ | |
266 | static void omap1510_deconfigure_device (void) | |
267 | { | |
268 | int epnum; | |
269 | ||
270 | UDCDBG ("clear Cfg_Lock"); | |
271 | outw (inw (UDC_SYSCON1) & ~UDC_Cfg_Lock, UDC_SYSCON1); | |
272 | UDCREG (UDC_SYSCON1); | |
273 | ||
274 | /* deconfigure all endpoints */ | |
275 | for (epnum = 1; epnum <= 15; epnum++) { | |
276 | outw (0, UDC_EP_RX (epnum)); | |
277 | outw (0, UDC_EP_TX (epnum)); | |
278 | } | |
279 | } | |
280 | ||
281 | /* omap1510_configure_device | |
282 | * | |
283 | * This function implements TRM Figure 14-9. | |
284 | */ | |
285 | static void omap1510_configure_device (struct usb_device_instance *device) | |
286 | { | |
287 | omap1510_configure_endpoints (device); | |
288 | ||
289 | ||
290 | /* Figure 14-9 indicates we should enable interrupts here, but we have | |
291 | * other routines (udc_all_interrupts, udc_suspended_interrupts) to | |
292 | * do that. | |
293 | */ | |
294 | ||
295 | UDCDBG ("set Cfg_Lock"); | |
296 | outw (inw (UDC_SYSCON1) | UDC_Cfg_Lock, UDC_SYSCON1); | |
297 | UDCREG (UDC_SYSCON1); | |
298 | } | |
299 | ||
300 | /* omap1510_write_noniso_tx_fifo | |
301 | * | |
302 | * This function implements TRM Figure 14-30. | |
303 | * | |
304 | * If the endpoint has an active tx_urb, then the next packet of data from the | |
305 | * URB is written to the tx FIFO. The total amount of data in the urb is given | |
306 | * by urb->actual_length. The maximum amount of data that can be sent in any | |
307 | * one packet is given by endpoint->tx_packetSize. The number of data bytes | |
308 | * from this URB that have already been transmitted is given by endpoint->sent. | |
309 | * endpoint->last is updated by this routine with the number of data bytes | |
310 | * transmitted in this packet. | |
311 | * | |
312 | * In accordance with Figure 14-30, the EP_NUM register must already have been | |
313 | * written with the value to select the appropriate tx FIFO before this routine | |
314 | * is called. | |
315 | */ | |
316 | static void omap1510_write_noniso_tx_fifo (struct usb_endpoint_instance | |
317 | *endpoint) | |
318 | { | |
319 | struct urb *urb = endpoint->tx_urb; | |
320 | ||
321 | if (urb) { | |
322 | unsigned int last, i; | |
323 | ||
324 | UDCDBGA ("urb->buffer %p, buffer_length %d, actual_length %d", | |
325 | urb->buffer, urb->buffer_length, urb->actual_length); | |
326 | if ((last = | |
327 | MIN (urb->actual_length - endpoint->sent, | |
328 | endpoint->tx_packetSize))) { | |
329 | u8 *cp = urb->buffer + endpoint->sent; | |
330 | ||
331 | UDCDBGA ("endpoint->sent %d, tx_packetSize %d, last %d", endpoint->sent, endpoint->tx_packetSize, last); | |
332 | ||
333 | if (((u32) cp & 1) == 0) { /* word aligned? */ | |
334 | outsw (UDC_DATA, cp, last >> 1); | |
335 | } else { /* byte aligned. */ | |
336 | for (i = 0; i < (last >> 1); i++) { | |
337 | u16 w = ((u16) cp[2 * i + 1] << 8) | | |
338 | (u16) cp[2 * i]; | |
339 | outw (w, UDC_DATA); | |
340 | } | |
341 | } | |
342 | if (last & 1) { | |
343 | outb (*(cp + last - 1), UDC_DATA); | |
344 | } | |
345 | } | |
346 | endpoint->last = last; | |
347 | } | |
348 | } | |
349 | ||
350 | /* omap1510_read_noniso_rx_fifo | |
351 | * | |
352 | * This function implements TRM Figure 14-28. | |
353 | * | |
354 | * If the endpoint has an active rcv_urb, then the next packet of data is read | |
355 | * from the rcv FIFO and written to rcv_urb->buffer at offset | |
356 | * rcv_urb->actual_length to append the packet data to the data from any | |
357 | * previous packets for this transfer. We assume that there is sufficient room | |
358 | * left in the buffer to hold an entire packet of data. | |
359 | * | |
360 | * The return value is the number of bytes read from the FIFO for this packet. | |
361 | * | |
362 | * In accordance with Figure 14-28, the EP_NUM register must already have been | |
363 | * written with the value to select the appropriate rcv FIFO before this routine | |
364 | * is called. | |
365 | */ | |
366 | static int omap1510_read_noniso_rx_fifo (struct usb_endpoint_instance | |
367 | *endpoint) | |
368 | { | |
369 | struct urb *urb = endpoint->rcv_urb; | |
370 | int len = 0; | |
371 | ||
372 | if (urb) { | |
373 | len = inw (UDC_RXFSTAT); | |
374 | ||
375 | if (len) { | |
376 | unsigned char *cp = urb->buffer + urb->actual_length; | |
377 | ||
378 | insw (UDC_DATA, cp, len >> 1); | |
379 | if (len & 1) | |
380 | *(cp + len - 1) = inb (UDC_DATA); | |
381 | } | |
382 | } | |
383 | return len; | |
384 | } | |
385 | ||
386 | /* omap1510_prepare_for_control_write_status | |
387 | * | |
388 | * This function implements TRM Figure 14-17. | |
389 | * | |
390 | * We have to deal here with non-autodecoded control writes that haven't already | |
391 | * been dealt with by ep0_recv_setup. The non-autodecoded standard control | |
392 | * write requests are: set/clear endpoint feature, set configuration, set | |
393 | * interface, and set descriptor. ep0_recv_setup handles set/clear requests for | |
394 | * ENDPOINT_HALT by halting the endpoint for a set request and resetting the | |
395 | * endpoint for a clear request. ep0_recv_setup returns an error for | |
396 | * SET_DESCRIPTOR requests which causes them to be terminated with a stall by | |
397 | * the setup handler. A SET_INTERFACE request is handled by ep0_recv_setup by | |
398 | * generating a DEVICE_SET_INTERFACE event. This leaves only the | |
399 | * SET_CONFIGURATION event for us to deal with here. | |
400 | * | |
401 | */ | |
402 | static void omap1510_prepare_for_control_write_status (struct urb *urb) | |
403 | { | |
404 | struct usb_device_request *request = &urb->device_request;; | |
405 | ||
406 | /* check for a SET_CONFIGURATION request */ | |
407 | if (request->bRequest == USB_REQ_SET_CONFIGURATION) { | |
408 | int configuration = le16_to_cpu (request->wValue) & 0xff; | |
409 | unsigned short devstat = inw (UDC_DEVSTAT); | |
410 | ||
411 | if ((devstat & (UDC_ADD | UDC_CFG)) == UDC_ADD) { | |
412 | /* device is currently in ADDRESSED state */ | |
413 | if (configuration) { | |
414 | /* Assume the specified non-zero configuration | |
415 | * value is valid and switch to the CONFIGURED | |
416 | * state. | |
417 | */ | |
418 | outw (UDC_Dev_Cfg, UDC_SYSCON2); | |
419 | } | |
420 | } else if ((devstat & UDC_CFG) == UDC_CFG) { | |
421 | /* device is currently in CONFIGURED state */ | |
422 | if (!configuration) { | |
423 | /* Switch to ADDRESSED state. */ | |
424 | outw (UDC_Clr_Cfg, UDC_SYSCON2); | |
425 | } | |
426 | } | |
427 | } | |
428 | ||
429 | /* select EP0 tx FIFO */ | |
430 | outw (UDC_EP_Dir | UDC_EP_Sel, UDC_EP_NUM); | |
431 | /* clear endpoint (no data bytes in status stage) */ | |
432 | outw (UDC_Clr_EP, UDC_CTRL); | |
433 | /* enable the EP0 tx FIFO */ | |
434 | outw (UDC_Set_FIFO_En, UDC_CTRL); | |
435 | /* deselect the endpoint */ | |
436 | outw (UDC_EP_Dir, UDC_EP_NUM); | |
437 | } | |
438 | ||
439 | /* udc_state_transition_up | |
440 | * udc_state_transition_down | |
441 | * | |
442 | * Helper functions to implement device state changes. The device states and | |
443 | * the events that transition between them are: | |
444 | * | |
445 | * STATE_ATTACHED | |
446 | * || /\ | |
447 | * \/ || | |
448 | * DEVICE_HUB_CONFIGURED DEVICE_HUB_RESET | |
449 | * || /\ | |
450 | * \/ || | |
451 | * STATE_POWERED | |
452 | * || /\ | |
453 | * \/ || | |
454 | * DEVICE_RESET DEVICE_POWER_INTERRUPTION | |
455 | * || /\ | |
456 | * \/ || | |
457 | * STATE_DEFAULT | |
458 | * || /\ | |
459 | * \/ || | |
460 | * DEVICE_ADDRESS_ASSIGNED DEVICE_RESET | |
461 | * || /\ | |
462 | * \/ || | |
463 | * STATE_ADDRESSED | |
464 | * || /\ | |
465 | * \/ || | |
466 | * DEVICE_CONFIGURED DEVICE_DE_CONFIGURED | |
467 | * || /\ | |
468 | * \/ || | |
469 | * STATE_CONFIGURED | |
470 | * | |
471 | * udc_state_transition_up transitions up (in the direction from STATE_ATTACHED | |
472 | * to STATE_CONFIGURED) from the specified initial state to the specified final | |
473 | * state, passing through each intermediate state on the way. If the initial | |
474 | * state is at or above (i.e. nearer to STATE_CONFIGURED) the final state, then | |
475 | * no state transitions will take place. | |
476 | * | |
477 | * udc_state_transition_down transitions down (in the direction from | |
478 | * STATE_CONFIGURED to STATE_ATTACHED) from the specified initial state to the | |
479 | * specified final state, passing through each intermediate state on the way. | |
480 | * If the initial state is at or below (i.e. nearer to STATE_ATTACHED) the final | |
481 | * state, then no state transitions will take place. | |
482 | * | |
483 | * These functions must only be called with interrupts disabled. | |
484 | */ | |
485 | static void udc_state_transition_up (usb_device_state_t initial, | |
486 | usb_device_state_t final) | |
487 | { | |
488 | if (initial < final) { | |
489 | switch (initial) { | |
490 | case STATE_ATTACHED: | |
491 | usbd_device_event_irq (udc_device, | |
492 | DEVICE_HUB_CONFIGURED, 0); | |
493 | if (final == STATE_POWERED) | |
494 | break; | |
495 | case STATE_POWERED: | |
496 | usbd_device_event_irq (udc_device, DEVICE_RESET, 0); | |
497 | if (final == STATE_DEFAULT) | |
498 | break; | |
499 | case STATE_DEFAULT: | |
500 | usbd_device_event_irq (udc_device, | |
501 | DEVICE_ADDRESS_ASSIGNED, 0); | |
502 | if (final == STATE_ADDRESSED) | |
503 | break; | |
504 | case STATE_ADDRESSED: | |
505 | usbd_device_event_irq (udc_device, DEVICE_CONFIGURED, | |
506 | 0); | |
507 | case STATE_CONFIGURED: | |
508 | break; | |
509 | default: | |
510 | break; | |
511 | } | |
512 | } | |
513 | } | |
514 | ||
515 | static void udc_state_transition_down (usb_device_state_t initial, | |
516 | usb_device_state_t final) | |
517 | { | |
518 | if (initial > final) { | |
519 | switch (initial) { | |
520 | case STATE_CONFIGURED: | |
521 | usbd_device_event_irq (udc_device, DEVICE_DE_CONFIGURED, 0); | |
522 | if (final == STATE_ADDRESSED) | |
523 | break; | |
524 | case STATE_ADDRESSED: | |
525 | usbd_device_event_irq (udc_device, DEVICE_RESET, 0); | |
526 | if (final == STATE_DEFAULT) | |
527 | break; | |
528 | case STATE_DEFAULT: | |
529 | usbd_device_event_irq (udc_device, DEVICE_POWER_INTERRUPTION, 0); | |
530 | if (final == STATE_POWERED) | |
531 | break; | |
532 | case STATE_POWERED: | |
533 | usbd_device_event_irq (udc_device, DEVICE_HUB_RESET, 0); | |
534 | case STATE_ATTACHED: | |
535 | break; | |
536 | default: | |
537 | break; | |
538 | } | |
539 | } | |
540 | } | |
541 | ||
542 | /* Handle all device state changes. | |
543 | * This function implements TRM Figure 14-21. | |
544 | */ | |
545 | static void omap1510_udc_state_changed (void) | |
546 | { | |
547 | u16 bits; | |
548 | u16 devstat = inw (UDC_DEVSTAT); | |
549 | ||
550 | UDCDBGA ("state changed, devstat %x, old %x", devstat, udc_devstat); | |
551 | ||
552 | bits = devstat ^ udc_devstat; | |
553 | if (bits) { | |
554 | if (bits & UDC_ATT) { | |
555 | if (devstat & UDC_ATT) { | |
556 | UDCDBG ("device attached and powered"); | |
557 | udc_state_transition_up (udc_device->device_state, STATE_POWERED); | |
558 | } else { | |
559 | UDCDBG ("device detached or unpowered"); | |
560 | udc_state_transition_down (udc_device->device_state, STATE_ATTACHED); | |
561 | } | |
562 | } | |
563 | if (bits & UDC_USB_Reset) { | |
564 | if (devstat & UDC_USB_Reset) { | |
565 | UDCDBG ("device reset in progess"); | |
566 | udc_state_transition_down (udc_device->device_state, STATE_POWERED); | |
567 | } else { | |
568 | UDCDBG ("device reset completed"); | |
569 | } | |
570 | } | |
571 | if (bits & UDC_DEF) { | |
572 | if (devstat & UDC_DEF) { | |
573 | UDCDBG ("device entering default state"); | |
574 | udc_state_transition_up (udc_device->device_state, STATE_DEFAULT); | |
575 | } else { | |
576 | UDCDBG ("device leaving default state"); | |
577 | udc_state_transition_down (udc_device->device_state, STATE_POWERED); | |
578 | } | |
579 | } | |
580 | if (bits & UDC_SUS) { | |
581 | if (devstat & UDC_SUS) { | |
582 | UDCDBG ("entering suspended state"); | |
583 | usbd_device_event_irq (udc_device, DEVICE_BUS_INACTIVE, 0); | |
584 | } else { | |
585 | UDCDBG ("leaving suspended state"); | |
586 | usbd_device_event_irq (udc_device, DEVICE_BUS_ACTIVITY, 0); | |
587 | } | |
588 | } | |
589 | if (bits & UDC_R_WK_OK) { | |
590 | UDCDBGA ("remote wakeup %s", (devstat & UDC_R_WK_OK) | |
591 | ? "enabled" : "disabled"); | |
592 | } | |
593 | if (bits & UDC_ADD) { | |
594 | if (devstat & UDC_ADD) { | |
595 | UDCDBG ("default -> addressed"); | |
596 | udc_state_transition_up (udc_device->device_state, STATE_ADDRESSED); | |
597 | } else { | |
598 | UDCDBG ("addressed -> default"); | |
599 | udc_state_transition_down (udc_device->device_state, STATE_DEFAULT); | |
600 | } | |
601 | } | |
602 | if (bits & UDC_CFG) { | |
603 | if (devstat & UDC_CFG) { | |
604 | UDCDBG ("device configured"); | |
605 | /* The ep0_recv_setup function generates the | |
606 | * DEVICE_CONFIGURED event when a | |
607 | * USB_REQ_SET_CONFIGURATION setup packet is | |
608 | * received, so we should already be in the | |
609 | * state STATE_CONFIGURED. | |
610 | */ | |
611 | udc_state_transition_up (udc_device->device_state, STATE_CONFIGURED); | |
612 | } else { | |
613 | UDCDBG ("device deconfigured"); | |
614 | udc_state_transition_down (udc_device->device_state, STATE_ADDRESSED); | |
615 | } | |
616 | } | |
617 | } | |
618 | ||
619 | /* Clear interrupt source */ | |
620 | outw (UDC_DS_Chg, UDC_IRQ_SRC); | |
621 | ||
622 | /* Save current DEVSTAT */ | |
623 | udc_devstat = devstat; | |
624 | } | |
625 | ||
626 | /* Handle SETUP USB interrupt. | |
627 | * This function implements TRM Figure 14-14. | |
628 | */ | |
629 | static void omap1510_udc_setup (struct usb_endpoint_instance *endpoint) | |
630 | { | |
631 | UDCDBG ("-> Entering device setup"); | |
386eda02 | 632 | |
232c150a WD |
633 | do { |
634 | const int setup_pktsize = 8; | |
635 | unsigned char *datap = | |
636 | (unsigned char *) &ep0_urb->device_request; | |
637 | ||
638 | /* Gain access to EP 0 setup FIFO */ | |
639 | outw (UDC_Setup_Sel, UDC_EP_NUM); | |
640 | ||
641 | /* Read control request data */ | |
642 | insb (UDC_DATA, datap, setup_pktsize); | |
643 | ||
644 | UDCDBGA ("EP0 setup read [%x %x %x %x %x %x %x %x]", | |
645 | *(datap + 0), *(datap + 1), *(datap + 2), | |
646 | *(datap + 3), *(datap + 4), *(datap + 5), | |
647 | *(datap + 6), *(datap + 7)); | |
648 | ||
649 | /* Reset EP0 setup FIFO */ | |
650 | outw (0, UDC_EP_NUM); | |
651 | } while (inw (UDC_IRQ_SRC) & UDC_Setup); | |
652 | ||
653 | /* Try to process setup packet */ | |
654 | if (ep0_recv_setup (ep0_urb)) { | |
655 | /* Not a setup packet, stall next EP0 transaction */ | |
656 | udc_stall_ep (0); | |
657 | UDCDBG ("can't parse setup packet, still waiting for setup"); | |
658 | return; | |
659 | } | |
660 | ||
661 | /* Check direction */ | |
662 | if ((ep0_urb->device_request.bmRequestType & USB_REQ_DIRECTION_MASK) | |
663 | == USB_REQ_HOST2DEVICE) { | |
664 | UDCDBG ("control write on EP0"); | |
665 | if (le16_to_cpu (ep0_urb->device_request.wLength)) { | |
666 | /* We don't support control write data stages. | |
667 | * The only standard control write request with a data | |
668 | * stage is SET_DESCRIPTOR, and ep0_recv_setup doesn't | |
669 | * support that so we just stall those requests. A | |
670 | * function driver might support a non-standard | |
671 | * write request with a data stage, but it isn't | |
672 | * obvious what we would do with the data if we read it | |
673 | * so we'll just stall it. It seems like the API isn't | |
674 | * quite right here. | |
675 | */ | |
676 | #if 0 | |
677 | /* Here is what we would do if we did support control | |
678 | * write data stages. | |
679 | */ | |
680 | ep0_urb->actual_length = 0; | |
681 | outw (0, UDC_EP_NUM); | |
682 | /* enable the EP0 rx FIFO */ | |
683 | outw (UDC_Set_FIFO_En, UDC_CTRL); | |
684 | #else | |
685 | /* Stall this request */ | |
686 | UDCDBG ("Stalling unsupported EP0 control write data " | |
687 | "stage."); | |
688 | udc_stall_ep (0); | |
689 | #endif | |
690 | } else { | |
691 | omap1510_prepare_for_control_write_status (ep0_urb); | |
692 | } | |
693 | } else { | |
694 | UDCDBG ("control read on EP0"); | |
695 | /* The ep0_recv_setup function has already placed our response | |
696 | * packet data in ep0_urb->buffer and the packet length in | |
697 | * ep0_urb->actual_length. | |
698 | */ | |
699 | endpoint->tx_urb = ep0_urb; | |
700 | endpoint->sent = 0; | |
701 | /* select the EP0 tx FIFO */ | |
702 | outw (UDC_EP_Dir | UDC_EP_Sel, UDC_EP_NUM); | |
703 | /* Write packet data to the FIFO. omap1510_write_noniso_tx_fifo | |
704 | * will update endpoint->last with the number of bytes written | |
705 | * to the FIFO. | |
706 | */ | |
707 | omap1510_write_noniso_tx_fifo (endpoint); | |
708 | /* enable the FIFO to start the packet transmission */ | |
709 | outw (UDC_Set_FIFO_En, UDC_CTRL); | |
710 | /* deselect the EP0 tx FIFO */ | |
711 | outw (UDC_EP_Dir, UDC_EP_NUM); | |
712 | } | |
713 | ||
714 | UDCDBG ("<- Leaving device setup"); | |
715 | } | |
716 | ||
717 | /* Handle endpoint 0 RX interrupt | |
718 | * This routine implements TRM Figure 14-16. | |
719 | */ | |
720 | static void omap1510_udc_ep0_rx (struct usb_endpoint_instance *endpoint) | |
721 | { | |
722 | unsigned short status; | |
723 | ||
724 | UDCDBG ("RX on EP0"); | |
725 | /* select EP0 rx FIFO */ | |
726 | outw (UDC_EP_Sel, UDC_EP_NUM); | |
727 | ||
728 | status = inw (UDC_STAT_FLG); | |
729 | ||
730 | if (status & UDC_ACK) { | |
731 | /* Check direction */ | |
732 | if ((ep0_urb->device_request.bmRequestType | |
733 | & USB_REQ_DIRECTION_MASK) == USB_REQ_HOST2DEVICE) { | |
734 | /* This rx interrupt must be for a control write data | |
735 | * stage packet. | |
736 | * | |
737 | * We don't support control write data stages. | |
738 | * We should never end up here. | |
739 | */ | |
740 | ||
741 | /* clear the EP0 rx FIFO */ | |
742 | outw (UDC_Clr_EP, UDC_CTRL); | |
743 | ||
744 | /* deselect the EP0 rx FIFO */ | |
745 | outw (0, UDC_EP_NUM); | |
746 | ||
747 | UDCDBG ("Stalling unexpected EP0 control write " | |
748 | "data stage packet"); | |
749 | udc_stall_ep (0); | |
750 | } else { | |
751 | /* This rx interrupt must be for a control read status | |
752 | * stage packet. | |
753 | */ | |
754 | UDCDBG ("ACK on EP0 control read status stage packet"); | |
755 | /* deselect EP0 rx FIFO */ | |
756 | outw (0, UDC_EP_NUM); | |
757 | } | |
758 | } else if (status & UDC_STALL) { | |
759 | UDCDBG ("EP0 stall during RX"); | |
760 | /* deselect EP0 rx FIFO */ | |
761 | outw (0, UDC_EP_NUM); | |
762 | } else { | |
763 | /* deselect EP0 rx FIFO */ | |
764 | outw (0, UDC_EP_NUM); | |
765 | } | |
766 | } | |
767 | ||
768 | /* Handle endpoint 0 TX interrupt | |
769 | * This routine implements TRM Figure 14-18. | |
770 | */ | |
771 | static void omap1510_udc_ep0_tx (struct usb_endpoint_instance *endpoint) | |
772 | { | |
773 | unsigned short status; | |
774 | struct usb_device_request *request = &ep0_urb->device_request; | |
775 | ||
776 | UDCDBG ("TX on EP0"); | |
777 | /* select EP0 TX FIFO */ | |
778 | outw (UDC_EP_Dir | UDC_EP_Sel, UDC_EP_NUM); | |
779 | ||
780 | status = inw (UDC_STAT_FLG); | |
781 | if (status & UDC_ACK) { | |
782 | /* Check direction */ | |
783 | if ((request->bmRequestType & USB_REQ_DIRECTION_MASK) == | |
784 | USB_REQ_HOST2DEVICE) { | |
785 | /* This tx interrupt must be for a control write status | |
786 | * stage packet. | |
787 | */ | |
788 | UDCDBG ("ACK on EP0 control write status stage packet"); | |
789 | /* deselect EP0 TX FIFO */ | |
790 | outw (UDC_EP_Dir, UDC_EP_NUM); | |
791 | } else { | |
792 | /* This tx interrupt must be for a control read data | |
793 | * stage packet. | |
794 | */ | |
795 | int wLength = le16_to_cpu (request->wLength); | |
796 | ||
797 | /* Update our count of bytes sent so far in this | |
798 | * transfer. | |
799 | */ | |
800 | endpoint->sent += endpoint->last; | |
801 | ||
802 | /* We are finished with this transfer if we have sent | |
803 | * all of the bytes in our tx urb (urb->actual_length) | |
804 | * unless we need a zero-length terminating packet. We | |
805 | * need a zero-length terminating packet if we returned | |
806 | * fewer bytes than were requested (wLength) by the host, | |
807 | * and the number of bytes we returned is an exact | |
808 | * multiple of the packet size endpoint->tx_packetSize. | |
809 | */ | |
810 | if ((endpoint->sent == ep0_urb->actual_length) | |
811 | && ((ep0_urb->actual_length == wLength) | |
812 | || (endpoint->last != | |
813 | endpoint->tx_packetSize))) { | |
814 | /* Done with control read data stage. */ | |
815 | UDCDBG ("control read data stage complete"); | |
816 | /* deselect EP0 TX FIFO */ | |
817 | outw (UDC_EP_Dir, UDC_EP_NUM); | |
818 | /* select EP0 RX FIFO to prepare for control | |
819 | * read status stage. | |
820 | */ | |
821 | outw (UDC_EP_Sel, UDC_EP_NUM); | |
822 | /* clear the EP0 RX FIFO */ | |
823 | outw (UDC_Clr_EP, UDC_CTRL); | |
824 | /* enable the EP0 RX FIFO */ | |
825 | outw (UDC_Set_FIFO_En, UDC_CTRL); | |
826 | /* deselect the EP0 RX FIFO */ | |
827 | outw (0, UDC_EP_NUM); | |
828 | } else { | |
829 | /* We still have another packet of data to send | |
830 | * in this control read data stage or else we | |
831 | * need a zero-length terminating packet. | |
832 | */ | |
833 | UDCDBG ("ACK control read data stage packet"); | |
834 | omap1510_write_noniso_tx_fifo (endpoint); | |
835 | /* enable the EP0 tx FIFO to start transmission */ | |
836 | outw (UDC_Set_FIFO_En, UDC_CTRL); | |
837 | /* deselect EP0 TX FIFO */ | |
838 | outw (UDC_EP_Dir, UDC_EP_NUM); | |
839 | } | |
840 | } | |
841 | } else if (status & UDC_STALL) { | |
842 | UDCDBG ("EP0 stall during TX"); | |
843 | /* deselect EP0 TX FIFO */ | |
844 | outw (UDC_EP_Dir, UDC_EP_NUM); | |
845 | } else { | |
846 | /* deselect EP0 TX FIFO */ | |
847 | outw (UDC_EP_Dir, UDC_EP_NUM); | |
848 | } | |
849 | } | |
850 | ||
851 | /* Handle RX transaction on non-ISO endpoint. | |
852 | * This function implements TRM Figure 14-27. | |
853 | * The ep argument is a physical endpoint number for a non-ISO OUT endpoint | |
854 | * in the range 1 to 15. | |
855 | */ | |
856 | static void omap1510_udc_epn_rx (int ep) | |
857 | { | |
858 | unsigned short status; | |
859 | ||
860 | /* Check endpoint status */ | |
861 | status = inw (UDC_STAT_FLG); | |
862 | ||
863 | if (status & UDC_ACK) { | |
864 | int nbytes; | |
865 | struct usb_endpoint_instance *endpoint = | |
866 | omap1510_find_ep (ep); | |
867 | ||
868 | nbytes = omap1510_read_noniso_rx_fifo (endpoint); | |
869 | usbd_rcv_complete (endpoint, nbytes, 0); | |
870 | ||
871 | /* enable rx FIFO to prepare for next packet */ | |
872 | outw (UDC_Set_FIFO_En, UDC_CTRL); | |
873 | } else if (status & UDC_STALL) { | |
874 | UDCDBGA ("STALL on RX endpoint %d", ep); | |
875 | } else if (status & UDC_NAK) { | |
876 | UDCDBGA ("NAK on RX ep %d", ep); | |
877 | } else { | |
878 | serial_printf ("omap-bi: RX on ep %d with status %x", ep, | |
879 | status); | |
880 | } | |
881 | } | |
882 | ||
883 | /* Handle TX transaction on non-ISO endpoint. | |
884 | * This function implements TRM Figure 14-29. | |
885 | * The ep argument is a physical endpoint number for a non-ISO IN endpoint | |
886 | * in the range 16 to 30. | |
887 | */ | |
888 | static void omap1510_udc_epn_tx (int ep) | |
889 | { | |
890 | unsigned short status; | |
891 | ||
892 | /*serial_printf("omap1510_udc_epn_tx( %x )\n",ep); */ | |
893 | ||
894 | /* Check endpoint status */ | |
895 | status = inw (UDC_STAT_FLG); | |
896 | ||
897 | if (status & UDC_ACK) { | |
898 | struct usb_endpoint_instance *endpoint = | |
899 | omap1510_find_ep (ep); | |
900 | ||
901 | /* We need to transmit a terminating zero-length packet now if | |
902 | * we have sent all of the data in this URB and the transfer | |
903 | * size was an exact multiple of the packet size. | |
904 | */ | |
905 | if (endpoint->tx_urb | |
906 | && (endpoint->last == endpoint->tx_packetSize) | |
907 | && (endpoint->tx_urb->actual_length - endpoint->sent - | |
908 | endpoint->last == 0)) { | |
909 | /* Prepare to transmit a zero-length packet. */ | |
910 | endpoint->sent += endpoint->last; | |
911 | /* write 0 bytes of data to FIFO */ | |
912 | omap1510_write_noniso_tx_fifo (endpoint); | |
913 | /* enable tx FIFO to start transmission */ | |
914 | outw (UDC_Set_FIFO_En, UDC_CTRL); | |
915 | } else if (endpoint->tx_urb | |
916 | && endpoint->tx_urb->actual_length) { | |
917 | /* retire the data that was just sent */ | |
918 | usbd_tx_complete (endpoint); | |
919 | /* Check to see if we have more data ready to transmit | |
920 | * now. | |
921 | */ | |
922 | if (endpoint->tx_urb | |
923 | && endpoint->tx_urb->actual_length) { | |
924 | /* write data to FIFO */ | |
925 | omap1510_write_noniso_tx_fifo (endpoint); | |
926 | /* enable tx FIFO to start transmission */ | |
927 | outw (UDC_Set_FIFO_En, UDC_CTRL); | |
928 | } | |
929 | } | |
930 | } else if (status & UDC_STALL) { | |
931 | UDCDBGA ("STALL on TX endpoint %d", ep); | |
932 | } else if (status & UDC_NAK) { | |
933 | UDCDBGA ("NAK on TX endpoint %d", ep); | |
934 | } else { | |
935 | /*serial_printf("omap-bi: TX on ep %d with status %x\n", ep, status); */ | |
936 | } | |
937 | } | |
938 | ||
939 | ||
940 | /* | |
941 | ------------------------------------------------------------------------------- | |
942 | */ | |
943 | ||
944 | /* Handle general USB interrupts and dispatch according to type. | |
945 | * This function implements TRM Figure 14-13. | |
946 | */ | |
947 | void omap1510_udc_irq (void) | |
948 | { | |
949 | u16 irq_src = inw (UDC_IRQ_SRC); | |
950 | int valid_irq = 0; | |
951 | ||
952 | if (!(irq_src & ~UDC_SOF_Flg)) /* ignore SOF interrupts ) */ | |
953 | return; | |
954 | ||
955 | UDCDBGA ("< IRQ #%d start >- %x", udc_interrupts, irq_src); | |
956 | /*serial_printf("< IRQ #%d start >- %x\n", udc_interrupts, irq_src); */ | |
957 | ||
958 | if (irq_src & UDC_DS_Chg) { | |
959 | /* Device status changed */ | |
960 | omap1510_udc_state_changed (); | |
961 | valid_irq++; | |
962 | } | |
963 | if (irq_src & UDC_EP0_RX) { | |
964 | /* Endpoint 0 receive */ | |
965 | outw (UDC_EP0_RX, UDC_IRQ_SRC); /* ack interrupt */ | |
966 | omap1510_udc_ep0_rx (udc_device->bus->endpoint_array + 0); | |
967 | valid_irq++; | |
968 | } | |
969 | if (irq_src & UDC_EP0_TX) { | |
970 | /* Endpoint 0 transmit */ | |
971 | outw (UDC_EP0_TX, UDC_IRQ_SRC); /* ack interrupt */ | |
972 | omap1510_udc_ep0_tx (udc_device->bus->endpoint_array + 0); | |
973 | valid_irq++; | |
974 | } | |
975 | if (irq_src & UDC_Setup) { | |
976 | /* Device setup */ | |
977 | omap1510_udc_setup (udc_device->bus->endpoint_array + 0); | |
978 | valid_irq++; | |
979 | } | |
980 | /*if (!valid_irq) */ | |
981 | /* serial_printf("unknown interrupt, IRQ_SRC %.4x\n", irq_src); */ | |
982 | UDCDBGA ("< IRQ #%d end >", udc_interrupts); | |
983 | udc_interrupts++; | |
984 | } | |
985 | ||
986 | /* This function implements TRM Figure 14-26. */ | |
987 | void omap1510_udc_noniso_irq (void) | |
988 | { | |
989 | unsigned short epnum; | |
990 | unsigned short irq_src = inw (UDC_IRQ_SRC); | |
991 | int valid_irq = 0; | |
992 | ||
993 | if (!(irq_src & (UDC_EPn_RX | UDC_EPn_TX))) | |
994 | return; | |
995 | ||
996 | UDCDBGA ("non-ISO IRQ, IRQ_SRC %x", inw (UDC_IRQ_SRC)); | |
997 | ||
998 | if (irq_src & UDC_EPn_RX) { /* Endpoint N OUT transaction */ | |
999 | /* Determine the endpoint number for this interrupt */ | |
1000 | epnum = (inw (UDC_EPN_STAT) & 0x0f00) >> 8; | |
1001 | UDCDBGA ("RX on ep %x", epnum); | |
1002 | ||
1003 | /* acknowledge interrupt */ | |
1004 | outw (UDC_EPn_RX, UDC_IRQ_SRC); | |
1005 | ||
1006 | if (epnum) { | |
1007 | /* select the endpoint FIFO */ | |
1008 | outw (UDC_EP_Sel | epnum, UDC_EP_NUM); | |
1009 | ||
1010 | omap1510_udc_epn_rx (epnum); | |
1011 | ||
1012 | /* deselect the endpoint FIFO */ | |
1013 | outw (epnum, UDC_EP_NUM); | |
1014 | } | |
1015 | valid_irq++; | |
1016 | } | |
1017 | if (irq_src & UDC_EPn_TX) { /* Endpoint N IN transaction */ | |
1018 | /* Determine the endpoint number for this interrupt */ | |
1019 | epnum = (inw (UDC_EPN_STAT) & 0x000f) | USB_DIR_IN; | |
1020 | UDCDBGA ("TX on ep %x", epnum); | |
1021 | ||
1022 | /* acknowledge interrupt */ | |
1023 | outw (UDC_EPn_TX, UDC_IRQ_SRC); | |
1024 | ||
1025 | if (epnum) { | |
1026 | /* select the endpoint FIFO */ | |
1027 | outw (UDC_EP_Sel | UDC_EP_Dir | epnum, UDC_EP_NUM); | |
1028 | ||
1029 | omap1510_udc_epn_tx (epnum); | |
1030 | ||
1031 | /* deselect the endpoint FIFO */ | |
1032 | outw (UDC_EP_Dir | epnum, UDC_EP_NUM); | |
1033 | } | |
1034 | valid_irq++; | |
1035 | } | |
1036 | if (!valid_irq) | |
1037 | serial_printf (": unknown non-ISO interrupt, IRQ_SRC %.4x\n", | |
1038 | irq_src); | |
1039 | } | |
1040 | ||
1041 | /* | |
1042 | ------------------------------------------------------------------------------- | |
1043 | */ | |
1044 | ||
1045 | ||
1046 | /* | |
1047 | * Start of public functions. | |
1048 | */ | |
1049 | ||
1050 | /* Called to start packet transmission. */ | |
dedacc18 | 1051 | int udc_endpoint_write (struct usb_endpoint_instance *endpoint) |
232c150a WD |
1052 | { |
1053 | unsigned short epnum = | |
1054 | endpoint->endpoint_address & USB_ENDPOINT_NUMBER_MASK; | |
1055 | ||
1056 | UDCDBGA ("Starting transmit on ep %x", epnum); | |
1057 | ||
1058 | if (endpoint->tx_urb) { | |
1059 | /* select the endpoint FIFO */ | |
1060 | outw (UDC_EP_Sel | UDC_EP_Dir | epnum, UDC_EP_NUM); | |
1061 | /* write data to FIFO */ | |
1062 | omap1510_write_noniso_tx_fifo (endpoint); | |
1063 | /* enable tx FIFO to start transmission */ | |
1064 | outw (UDC_Set_FIFO_En, UDC_CTRL); | |
1065 | /* deselect the endpoint FIFO */ | |
1066 | outw (UDC_EP_Dir | epnum, UDC_EP_NUM); | |
1067 | } | |
dedacc18 JCPV |
1068 | |
1069 | return 0; | |
232c150a WD |
1070 | } |
1071 | ||
1072 | /* Start to initialize h/w stuff */ | |
1073 | int udc_init (void) | |
1074 | { | |
1075 | u16 udc_rev; | |
bdda519d | 1076 | uchar value; |
efa329cb WD |
1077 | ulong gpio; |
1078 | int i; | |
1079 | ||
1080 | /* Let the device settle down before we start */ | |
1081 | for (i = 0; i < UDC_INIT_MDELAY; i++) udelay(1000); | |
232c150a WD |
1082 | |
1083 | udc_device = NULL; | |
1084 | ||
1085 | UDCDBG ("starting"); | |
1086 | ||
1087 | /* Check peripheral reset. Must be 1 to make sure | |
1088 | MPU TIPB peripheral reset is inactive */ | |
1089 | UDCREG (ARM_RSTCT2); | |
1090 | ||
1091 | /* Set and check clock control. | |
1092 | * We might ought to be using the clock control API to do | |
1093 | * this instead of fiddling with the clock registers directly | |
1094 | * here. | |
1095 | */ | |
1096 | outw ((1 << 4) | (1 << 5), CLOCK_CTRL); | |
1097 | UDCREG (CLOCK_CTRL); | |
1d10dcd0 HJ |
1098 | |
1099 | #ifdef CONFIG_OMAP1510 | |
1100 | /* This code was originally implemented for OMAP1510 and | |
1101 | * therefore is only applicable for OMAP1510 boards. For | |
1102 | * OMAP5912 or OMAP16xx the register APLL_CTRL does not | |
1103 | * exist and DPLL_CTRL is already configured. | |
1104 | */ | |
1105 | ||
232c150a WD |
1106 | /* Set and check APLL */ |
1107 | outw (0x0008, APLL_CTRL); | |
1108 | UDCREG (APLL_CTRL); | |
1109 | /* Set and check DPLL */ | |
1110 | outw (0x2210, DPLL_CTRL); | |
1111 | UDCREG (DPLL_CTRL); | |
1d10dcd0 HJ |
1112 | #endif |
1113 | /* Set and check SOFT | |
1114 | * The below line of code has been changed to perform a | |
1115 | * read-modify-write instead of a simple write for | |
1116 | * configuring the SOFT_REQ register. This allows the code | |
1117 | * to be compatible with OMAP5912 and OMAP16xx devices | |
1118 | */ | |
1119 | outw ((1 << 4) | (1 << 3) | 1 | (inw(SOFT_REQ)), SOFT_REQ); | |
1120 | ||
232c150a WD |
1121 | /* Short delay to wait for DPLL */ |
1122 | udelay (1000); | |
1123 | ||
1124 | /* Print banner with device revision */ | |
1125 | udc_rev = inw (UDC_REV) & 0xff; | |
1d10dcd0 | 1126 | #ifdef CONFIG_OMAP1510 |
232c150a WD |
1127 | printf ("USB: TI OMAP1510 USB function module rev %d.%d\n", |
1128 | udc_rev >> 4, udc_rev & 0xf); | |
1d10dcd0 HJ |
1129 | #endif |
1130 | ||
1131 | #ifdef CONFIG_OMAP1610 | |
1132 | printf ("USB: TI OMAP5912 USB function module rev %d.%d\n", | |
1133 | udc_rev >> 4, udc_rev & 0xf); | |
1134 | #endif | |
232c150a | 1135 | |
bdda519d WD |
1136 | #ifdef CONFIG_OMAP_SX1 |
1137 | i2c_read (0x32, 0x04, 1, &value, 1); | |
1138 | value |= 0x04; | |
1139 | i2c_write (0x32, 0x04, 1, &value, 1); | |
232c150a | 1140 | |
bdda519d WD |
1141 | i2c_read (0x32, 0x03, 1, &value, 1); |
1142 | value |= 0x01; | |
1143 | i2c_write (0x32, 0x03, 1, &value, 1); | |
efa329cb WD |
1144 | |
1145 | gpio = inl(GPIO_PIN_CONTROL_REG); | |
1146 | gpio |= 0x0002; /* A_IRDA_OFF */ | |
1147 | gpio |= 0x0800; /* A_SWITCH */ | |
1148 | gpio |= 0x8000; /* A_USB_ON */ | |
1149 | outl (gpio, GPIO_PIN_CONTROL_REG); | |
1150 | ||
1151 | gpio = inl(GPIO_DIR_CONTROL_REG); | |
1152 | gpio &= ~0x0002; /* A_IRDA_OFF */ | |
1153 | gpio &= ~0x0800; /* A_SWITCH */ | |
1154 | gpio &= ~0x8000; /* A_USB_ON */ | |
1155 | outl (gpio, GPIO_DIR_CONTROL_REG); | |
1156 | ||
1157 | gpio = inl(GPIO_DATA_OUTPUT_REG); | |
1158 | gpio |= 0x0002; /* A_IRDA_OFF */ | |
1159 | gpio &= ~0x0800; /* A_SWITCH */ | |
1160 | gpio &= ~0x8000; /* A_USB_ON */ | |
1161 | outl (gpio, GPIO_DATA_OUTPUT_REG); | |
bdda519d | 1162 | #endif |
232c150a WD |
1163 | |
1164 | /* The VBUS_MODE bit selects whether VBUS detection is done via | |
1165 | * software (1) or hardware (0). When software detection is | |
1166 | * selected, VBUS_CTRL selects whether USB is not connected (0) | |
1167 | * or connected (1). | |
1168 | */ | |
1169 | outl (inl (FUNC_MUX_CTRL_0) | UDC_VBUS_MODE, FUNC_MUX_CTRL_0); | |
1170 | outl (inl (FUNC_MUX_CTRL_0) & ~UDC_VBUS_CTRL, FUNC_MUX_CTRL_0); | |
1171 | UDCREGL (FUNC_MUX_CTRL_0); | |
1172 | ||
1173 | /* | |
1174 | * At this point, device is ready for configuration... | |
1175 | */ | |
1176 | ||
1177 | UDCDBG ("disable USB interrupts"); | |
1178 | outw (0, UDC_IRQ_EN); | |
1179 | UDCREG (UDC_IRQ_EN); | |
1180 | ||
1181 | UDCDBG ("disable USB DMA"); | |
1182 | outw (0, UDC_DMA_IRQ_EN); | |
1183 | UDCREG (UDC_DMA_IRQ_EN); | |
1184 | ||
1185 | UDCDBG ("initialize SYSCON1"); | |
1186 | outw (UDC_Self_Pwr | UDC_Pullup_En, UDC_SYSCON1); | |
1187 | UDCREG (UDC_SYSCON1); | |
1188 | ||
1189 | return 0; | |
1190 | } | |
1191 | ||
1192 | /* Stall endpoint */ | |
1193 | static void udc_stall_ep (unsigned int ep_addr) | |
1194 | { | |
1195 | /*int ep_addr = PHYS_EP_TO_EP_ADDR(ep); */ | |
1196 | int ep_num = ep_addr & USB_ENDPOINT_NUMBER_MASK; | |
1197 | ||
1198 | UDCDBGA ("stall ep_addr %d", ep_addr); | |
1199 | ||
1200 | /* REVISIT? | |
1201 | * The OMAP TRM section 14.2.4.2 says we must check that the FIFO | |
1202 | * is empty before halting the endpoint. The current implementation | |
1203 | * doesn't check that the FIFO is empty. | |
1204 | */ | |
1205 | ||
1206 | if (!ep_num) { | |
1207 | outw (UDC_Stall_Cmd, UDC_SYSCON2); | |
1208 | } else if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_OUT) { | |
1209 | if (inw (UDC_EP_RX (ep_num)) & UDC_EPn_RX_Valid) { | |
1210 | /* we have a valid rx endpoint, so halt it */ | |
1211 | outw (UDC_EP_Sel | ep_num, UDC_EP_NUM); | |
1212 | outw (UDC_Set_Halt, UDC_CTRL); | |
1213 | outw (ep_num, UDC_EP_NUM); | |
1214 | } | |
1215 | } else { | |
1216 | if (inw (UDC_EP_TX (ep_num)) & UDC_EPn_TX_Valid) { | |
1217 | /* we have a valid tx endpoint, so halt it */ | |
1218 | outw (UDC_EP_Sel | UDC_EP_Dir | ep_num, UDC_EP_NUM); | |
1219 | outw (UDC_Set_Halt, UDC_CTRL); | |
1220 | outw (ep_num, UDC_EP_NUM); | |
1221 | } | |
1222 | } | |
1223 | } | |
1224 | ||
1225 | /* Reset endpoint */ | |
1226 | #if 0 | |
1227 | static void udc_reset_ep (unsigned int ep_addr) | |
1228 | { | |
1229 | /*int ep_addr = PHYS_EP_TO_EP_ADDR(ep); */ | |
1230 | int ep_num = ep_addr & USB_ENDPOINT_NUMBER_MASK; | |
1231 | ||
1232 | UDCDBGA ("reset ep_addr %d", ep_addr); | |
1233 | ||
1234 | if (!ep_num) { | |
1235 | /* control endpoint 0 can't be reset */ | |
1236 | } else if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_OUT) { | |
1237 | UDCDBGA ("UDC_EP_RX(%d) = 0x%04x", ep_num, | |
1238 | inw (UDC_EP_RX (ep_num))); | |
1239 | if (inw (UDC_EP_RX (ep_num)) & UDC_EPn_RX_Valid) { | |
1240 | /* we have a valid rx endpoint, so reset it */ | |
1241 | outw (ep_num | UDC_EP_Sel, UDC_EP_NUM); | |
1242 | outw (UDC_Reset_EP, UDC_CTRL); | |
1243 | outw (ep_num, UDC_EP_NUM); | |
1244 | UDCDBGA ("OUT endpoint %d reset", ep_num); | |
1245 | } | |
1246 | } else { | |
1247 | UDCDBGA ("UDC_EP_TX(%d) = 0x%04x", ep_num, | |
1248 | inw (UDC_EP_TX (ep_num))); | |
1249 | /* Resetting of tx endpoints seems to be causing the USB function | |
1250 | * module to fail, which causes problems when the driver is | |
1251 | * uninstalled. We'll skip resetting tx endpoints for now until | |
1252 | * we figure out what the problem is. | |
1253 | */ | |
1254 | #if 0 | |
1255 | if (inw (UDC_EP_TX (ep_num)) & UDC_EPn_TX_Valid) { | |
1256 | /* we have a valid tx endpoint, so reset it */ | |
1257 | outw (ep_num | UDC_EP_Dir | UDC_EP_Sel, UDC_EP_NUM); | |
1258 | outw (UDC_Reset_EP, UDC_CTRL); | |
1259 | outw (ep_num | UDC_EP_Dir, UDC_EP_NUM); | |
1260 | UDCDBGA ("IN endpoint %d reset", ep_num); | |
1261 | } | |
1262 | #endif | |
1263 | } | |
1264 | } | |
1265 | #endif | |
1266 | ||
1267 | /* ************************************************************************** */ | |
1268 | ||
1269 | /** | |
1270 | * udc_check_ep - check logical endpoint | |
1271 | * | |
1272 | * Return physical endpoint number to use for this logical endpoint or zero if not valid. | |
1273 | */ | |
1274 | #if 0 | |
1275 | int udc_check_ep (int logical_endpoint, int packetsize) | |
1276 | { | |
1277 | if ((logical_endpoint == 0x80) || | |
1278 | ((logical_endpoint & 0x8f) != logical_endpoint)) { | |
1279 | return 0; | |
1280 | } | |
1281 | ||
1282 | switch (packetsize) { | |
1283 | case 8: | |
1284 | case 16: | |
1285 | case 32: | |
1286 | case 64: | |
1287 | case 128: | |
1288 | case 256: | |
1289 | case 512: | |
1290 | break; | |
1291 | default: | |
1292 | return 0; | |
1293 | } | |
1294 | ||
1295 | return EP_ADDR_TO_PHYS_EP (logical_endpoint); | |
1296 | } | |
1297 | #endif | |
1298 | ||
1299 | /* | |
1300 | * udc_setup_ep - setup endpoint | |
1301 | * | |
1302 | * Associate a physical endpoint with endpoint_instance | |
1303 | */ | |
1304 | void udc_setup_ep (struct usb_device_instance *device, | |
1305 | unsigned int ep, struct usb_endpoint_instance *endpoint) | |
1306 | { | |
1307 | UDCDBGA ("setting up endpoint addr %x", endpoint->endpoint_address); | |
1308 | ||
1309 | /* This routine gets called by bi_modinit for endpoint 0 and from | |
1310 | * bi_config for all of the other endpoints. bi_config gets called | |
1311 | * during the DEVICE_CREATE, DEVICE_CONFIGURED, and | |
1312 | * DEVICE_SET_INTERFACE events. We need to reconfigure the OMAP packet | |
1313 | * RAM after bi_config scans the selected device configuration and | |
1314 | * initializes the endpoint structures, but before this routine enables | |
1315 | * the OUT endpoint FIFOs. Since bi_config calls this routine in a | |
1316 | * loop for endpoints 1 through UDC_MAX_ENDPOINTS, we reconfigure our | |
1317 | * packet RAM here when ep==1. | |
1318 | * I really hate to do this here, but it seems like the API exported | |
1319 | * by the USB bus interface controller driver to the usbd-bi module | |
1320 | * isn't quite right so there is no good place to do this. | |
1321 | */ | |
1322 | if (ep == 1) { | |
1323 | omap1510_deconfigure_device (); | |
1324 | omap1510_configure_device (device); | |
1325 | } | |
1326 | ||
1327 | if (endpoint && (ep < UDC_MAX_ENDPOINTS)) { | |
1328 | int ep_addr = endpoint->endpoint_address; | |
1329 | ||
1330 | if (!ep_addr) { | |
1331 | /* nothing to do for endpoint 0 */ | |
1332 | } else if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) { | |
1333 | /* nothing to do for IN (tx) endpoints */ | |
1334 | } else { /* OUT (rx) endpoint */ | |
1335 | if (endpoint->rcv_packetSize) { | |
1336 | /*struct urb* urb = &(urb_out_array[ep&0xFF]); */ | |
1337 | /*urb->endpoint = endpoint; */ | |
1338 | /*urb->device = device; */ | |
1339 | /*urb->buffer_length = sizeof(urb->buffer); */ | |
1340 | ||
1341 | /*endpoint->rcv_urb = urb; */ | |
1342 | omap1510_prepare_endpoint_for_rx (ep_addr); | |
1343 | } | |
1344 | } | |
1345 | } | |
1346 | } | |
1347 | ||
1348 | /** | |
1349 | * udc_disable_ep - disable endpoint | |
1350 | * @ep: | |
1351 | * | |
1352 | * Disable specified endpoint | |
1353 | */ | |
1354 | #if 0 | |
1355 | void udc_disable_ep (unsigned int ep_addr) | |
1356 | { | |
1357 | /*int ep_addr = PHYS_EP_TO_EP_ADDR(ep); */ | |
1358 | int ep_num = ep_addr & USB_ENDPOINT_NUMBER_MASK; | |
1359 | struct usb_endpoint_instance *endpoint = omap1510_find_ep (ep_addr); /*udc_device->bus->endpoint_array + ep; */ | |
1360 | ||
1361 | UDCDBGA ("disable ep_addr %d", ep_addr); | |
1362 | ||
1363 | if (!ep_num) { | |
1364 | /* nothing to do for endpoint 0 */ ; | |
1365 | } else if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) { | |
1366 | if (endpoint->tx_packetSize) { | |
1367 | /* we have a valid tx endpoint */ | |
1368 | /*usbd_flush_tx(endpoint); */ | |
1369 | endpoint->tx_urb = NULL; | |
1370 | } | |
1371 | } else { | |
1372 | if (endpoint->rcv_packetSize) { | |
1373 | /* we have a valid rx endpoint */ | |
1374 | /*usbd_flush_rcv(endpoint); */ | |
1375 | endpoint->rcv_urb = NULL; | |
1376 | } | |
1377 | } | |
1378 | } | |
1379 | #endif | |
1380 | ||
1381 | /* ************************************************************************** */ | |
1382 | ||
1383 | /** | |
1384 | * udc_connected - is the USB cable connected | |
1385 | * | |
1386 | * Return non-zero if cable is connected. | |
1387 | */ | |
1388 | #if 0 | |
1389 | int udc_connected (void) | |
1390 | { | |
1391 | return ((inw (UDC_DEVSTAT) & UDC_ATT) == UDC_ATT); | |
1392 | } | |
1393 | #endif | |
1394 | ||
1395 | /* Turn on the USB connection by enabling the pullup resistor */ | |
1396 | void udc_connect (void) | |
1397 | { | |
1398 | UDCDBG ("connect, enable Pullup"); | |
1399 | outl (0x00000018, FUNC_MUX_CTRL_D); | |
1400 | } | |
1401 | ||
1402 | /* Turn off the USB connection by disabling the pullup resistor */ | |
1403 | void udc_disconnect (void) | |
1404 | { | |
1405 | UDCDBG ("disconnect, disable Pullup"); | |
1406 | outl (0x00000000, FUNC_MUX_CTRL_D); | |
1407 | } | |
1408 | ||
1409 | /* ************************************************************************** */ | |
1410 | ||
1411 | ||
1412 | /* | |
1413 | * udc_disable_interrupts - disable interrupts | |
1414 | * switch off interrupts | |
1415 | */ | |
1416 | #if 0 | |
1417 | void udc_disable_interrupts (struct usb_device_instance *device) | |
1418 | { | |
1419 | UDCDBG ("disabling all interrupts"); | |
1420 | outw (0, UDC_IRQ_EN); | |
1421 | } | |
1422 | #endif | |
1423 | ||
1424 | /* ************************************************************************** */ | |
1425 | ||
1426 | /** | |
1427 | * udc_ep0_packetsize - return ep0 packetsize | |
1428 | */ | |
1429 | #if 0 | |
1430 | int udc_ep0_packetsize (void) | |
1431 | { | |
1432 | return EP0_PACKETSIZE; | |
1433 | } | |
1434 | #endif | |
1435 | ||
1436 | /* Switch on the UDC */ | |
1437 | void udc_enable (struct usb_device_instance *device) | |
1438 | { | |
1439 | UDCDBGA ("enable device %p, status %d", device, device->status); | |
1440 | ||
1441 | /* initialize driver state variables */ | |
1442 | udc_devstat = 0; | |
1443 | ||
1444 | /* Save the device structure pointer */ | |
1445 | udc_device = device; | |
1446 | ||
1447 | /* Setup ep0 urb */ | |
1448 | if (!ep0_urb) { | |
1449 | ep0_urb = | |
1450 | usbd_alloc_urb (udc_device, | |
1451 | udc_device->bus->endpoint_array); | |
1452 | } else { | |
1453 | serial_printf ("udc_enable: ep0_urb already allocated %p\n", | |
1454 | ep0_urb); | |
1455 | } | |
1456 | ||
1457 | UDCDBG ("Check clock status"); | |
1458 | UDCREG (STATUS_REQ); | |
1459 | ||
1460 | /* The VBUS_MODE bit selects whether VBUS detection is done via | |
1461 | * software (1) or hardware (0). When software detection is | |
1462 | * selected, VBUS_CTRL selects whether USB is not connected (0) | |
1463 | * or connected (1). | |
1464 | */ | |
1465 | outl (inl (FUNC_MUX_CTRL_0) | UDC_VBUS_CTRL | UDC_VBUS_MODE, | |
1466 | FUNC_MUX_CTRL_0); | |
1467 | UDCREGL (FUNC_MUX_CTRL_0); | |
1468 | ||
1469 | omap1510_configure_device (device); | |
1470 | } | |
1471 | ||
1472 | /* Switch off the UDC */ | |
1473 | void udc_disable (void) | |
1474 | { | |
1475 | UDCDBG ("disable UDC"); | |
1476 | ||
1477 | omap1510_deconfigure_device (); | |
1478 | ||
1479 | /* The VBUS_MODE bit selects whether VBUS detection is done via | |
1480 | * software (1) or hardware (0). When software detection is | |
1481 | * selected, VBUS_CTRL selects whether USB is not connected (0) | |
1482 | * or connected (1). | |
1483 | */ | |
1484 | outl (inl (FUNC_MUX_CTRL_0) | UDC_VBUS_MODE, FUNC_MUX_CTRL_0); | |
1485 | outl (inl (FUNC_MUX_CTRL_0) & ~UDC_VBUS_CTRL, FUNC_MUX_CTRL_0); | |
1486 | UDCREGL (FUNC_MUX_CTRL_0); | |
1487 | ||
1488 | /* Free ep0 URB */ | |
1489 | if (ep0_urb) { | |
1490 | /*usbd_dealloc_urb(ep0_urb); */ | |
1491 | ep0_urb = NULL; | |
1492 | } | |
1493 | ||
1494 | /* Reset device pointer. | |
1495 | * We ought to do this here to balance the initialization of udc_device | |
1496 | * in udc_enable, but some of our other exported functions get called | |
1497 | * by the bus interface driver after udc_disable, so we have to hang on | |
1498 | * to the device pointer to avoid a null pointer dereference. */ | |
1499 | /* udc_device = NULL; */ | |
1500 | } | |
1501 | ||
1502 | /** | |
1503 | * udc_startup - allow udc code to do any additional startup | |
1504 | */ | |
1505 | void udc_startup_events (struct usb_device_instance *device) | |
1506 | { | |
1507 | /* The DEVICE_INIT event puts the USB device in the state STATE_INIT. */ | |
1508 | usbd_device_event_irq (device, DEVICE_INIT, 0); | |
1509 | ||
1510 | /* The DEVICE_CREATE event puts the USB device in the state | |
1511 | * STATE_ATTACHED. | |
1512 | */ | |
1513 | usbd_device_event_irq (device, DEVICE_CREATE, 0); | |
1514 | ||
1515 | /* Some USB controller driver implementations signal | |
1516 | * DEVICE_HUB_CONFIGURED and DEVICE_RESET events here. | |
1517 | * DEVICE_HUB_CONFIGURED causes a transition to the state STATE_POWERED, | |
1518 | * and DEVICE_RESET causes a transition to the state STATE_DEFAULT. | |
1519 | * The OMAP USB client controller has the capability to detect when the | |
1520 | * USB cable is connected to a powered USB bus via the ATT bit in the | |
1521 | * DEVSTAT register, so we will defer the DEVICE_HUB_CONFIGURED and | |
1522 | * DEVICE_RESET events until later. | |
1523 | */ | |
1524 | ||
1525 | udc_enable (device); | |
1526 | } | |
1527 | ||
16c8d5e7 | 1528 | /** |
386eda02 | 1529 | * udc_irq - do pseudo interrupts |
16c8d5e7 WD |
1530 | */ |
1531 | void udc_irq(void) | |
1532 | { | |
1533 | /* Loop while we have interrupts. | |
1534 | * If we don't do this, the input chain | |
1535 | * polling delay is likely to miss | |
1536 | * host requests. | |
1537 | */ | |
1538 | while (inw (UDC_IRQ_SRC) & ~UDC_SOF_Flg) { | |
1539 | /* Handle any new IRQs */ | |
1540 | omap1510_udc_irq (); | |
1541 | omap1510_udc_noniso_irq (); | |
1542 | } | |
1543 | } | |
1544 | ||
1545 | /* Flow control */ | |
1546 | void udc_set_nak(int epid) | |
1547 | { | |
1548 | /* TODO: implement this functionality in omap1510 */ | |
1549 | } | |
1550 | ||
1551 | void udc_unset_nak (int epid) | |
1552 | { | |
1553 | /* TODO: implement this functionality in omap1510 */ | |
1554 | } |