[people/ms/u-boot.git] / drivers / usb / gadget / regs-otg.h

/* linux/arch/arm/plat-s3c/include/plat/regs-otg.h
 *
 * Copyright (C) 2004 Herbert Poetzl <herbert@13thfloor.at>
 *
 * Registers remapping:
 * Lukasz Majewski <l.majewski@samsumg.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __ASM_ARCH_REGS_USB_OTG_HS_H
#define __ASM_ARCH_REGS_USB_OTG_HS_H

/* USB2.0 OTG Controller register */
struct s3c_usbotg_phy {
	u32 phypwr;
	u32 phyclk;
	u32 rstcon;
};

/* Device Logical IN Endpoint-Specific Registers */
struct s3c_dev_in_endp {
	u32 diepctl;
	u8  res1[4];
	u32 diepint;
	u8  res2[4];
	u32 dieptsiz;
	u32 diepdma;
	u8  res3[4];
	u32 diepdmab;
};

/* Device Logical OUT Endpoint-Specific Registers */
struct s3c_dev_out_endp {
	u32 doepctl;
	u8  res1[4];
	u32 doepint;
	u8  res2[4];
	u32 doeptsiz;
	u32 doepdma;
	u8  res3[4];
	u32 doepdmab;
};

struct ep_fifo {
	u32 fifo;
	u8  res[4092];
};

/* USB2.0 OTG Controller register */
struct s3c_usbotg_reg {
	/* Core Global Registers */
	u32 gotgctl; /* OTG Control & Status */
	u32 gotgint; /* OTG Interrupt */
	u32 gahbcfg; /* Core AHB Configuration */
	u32 gusbcfg; /* Core USB Configuration */
	u32 grstctl; /* Core Reset */
	u32 gintsts; /* Core Interrupt */
	u32 gintmsk; /* Core Interrupt Mask */
	u32 grxstsr; /* Receive Status Debug Read/Status Read */
	u32 grxstsp; /* Receive Status Debug Pop/Status Pop */
	u32 grxfsiz; /* Receive FIFO Size */
	u32 gnptxfsiz; /* Non-Periodic Transmit FIFO Size */
	u8  res1[216];
	u32 dieptxf[15]; /* Device Periodic Transmit FIFO size register */
	u8  res2[1728];
	/* Device Configuration */
	u32 dcfg; /* Device Configuration Register */
	u32 dctl; /* Device Control */
	u32 dsts; /* Device Status */
	u8  res3[4];
	u32 diepmsk; /* Device IN Endpoint Common Interrupt Mask */
	u32 doepmsk; /* Device OUT Endpoint Common Interrupt Mask */
	u32 daint; /* Device All Endpoints Interrupt */
	u32 daintmsk; /* Device All Endpoints Interrupt Mask */
	u8  res4[224];
	struct s3c_dev_in_endp in_endp[16];
	struct s3c_dev_out_endp out_endp[16];
	u8  res5[768];
	struct ep_fifo ep[16];
};

/*===================================================================== */
/*definitions related to CSR setting */

/* S3C_UDC_OTG_GOTGCTL */
#define B_SESSION_VALID		(0x1<<19)
#define A_SESSION_VALID		(0x1<<18)

/* S3C_UDC_OTG_GAHBCFG */
#define PTXFE_HALF			(0<<8)
#define PTXFE_ZERO			(1<<8)
#define NPTXFE_HALF			(0<<7)
#define NPTXFE_ZERO			(1<<7)
#define MODE_SLAVE			(0<<5)
#define MODE_DMA			(1<<5)
#define BURST_SINGLE			(0<<1)
#define BURST_INCR			(1<<1)
#define BURST_INCR4			(3<<1)
#define BURST_INCR8			(5<<1)
#define BURST_INCR16			(7<<1)
#define GBL_INT_UNMASK			(1<<0)
#define GBL_INT_MASK			(0<<0)

/* S3C_UDC_OTG_GRSTCTL */
#define AHB_MASTER_IDLE		(1u<<31)
#define CORE_SOFT_RESET		(0x1<<0)

/* S3C_UDC_OTG_GINTSTS/S3C_UDC_OTG_GINTMSK core interrupt register */
#define INT_RESUME			(1u<<31)
#define INT_DISCONN			(0x1<<29)
#define INT_CONN_ID_STS_CNG		(0x1<<28)
#define INT_OUT_EP			(0x1<<19)
#define INT_IN_EP			(0x1<<18)
#define INT_ENUMDONE			(0x1<<13)
#define INT_RESET			(0x1<<12)
#define INT_SUSPEND			(0x1<<11)
#define INT_EARLY_SUSPEND		(0x1<<10)
#define INT_NP_TX_FIFO_EMPTY		(0x1<<5)
#define INT_RX_FIFO_NOT_EMPTY		(0x1<<4)
#define INT_SOF			(0x1<<3)
#define INT_DEV_MODE			(0x0<<0)
#define INT_HOST_MODE			(0x1<<1)
#define INT_GOUTNakEff			(0x01<<7)
#define INT_GINNakEff			(0x01<<6)

#define FULL_SPEED_CONTROL_PKT_SIZE	8
#define FULL_SPEED_BULK_PKT_SIZE	64

#define HIGH_SPEED_CONTROL_PKT_SIZE	64
#define HIGH_SPEED_BULK_PKT_SIZE	512

#define RX_FIFO_SIZE			(1024*4)
#define NPTX_FIFO_SIZE			(1024*4)
#define PTX_FIFO_SIZE			(1536*1)

#define DEPCTL_TXFNUM_0		(0x0<<22)
#define DEPCTL_TXFNUM_1		(0x1<<22)
#define DEPCTL_TXFNUM_2		(0x2<<22)
#define DEPCTL_TXFNUM_3		(0x3<<22)
#define DEPCTL_TXFNUM_4		(0x4<<22)

/* Enumeration speed */
#define USB_HIGH_30_60MHZ		(0x0<<1)
#define USB_FULL_30_60MHZ		(0x1<<1)
#define USB_LOW_6MHZ			(0x2<<1)
#define USB_FULL_48MHZ			(0x3<<1)

/* S3C_UDC_OTG_GRXSTSP STATUS */
#define OUT_PKT_RECEIVED		(0x2<<17)
#define OUT_TRANSFER_COMPLELTED	(0x3<<17)
#define SETUP_TRANSACTION_COMPLETED	(0x4<<17)
#define SETUP_PKT_RECEIVED		(0x6<<17)
#define GLOBAL_OUT_NAK			(0x1<<17)

/* S3C_UDC_OTG_DCTL device control register */
#define NORMAL_OPERATION		(0x1<<0)
#define SOFT_DISCONNECT		(0x1<<1)

/* S3C_UDC_OTG_DAINT device all endpoint interrupt register */
#define DAINT_OUT_BIT			(16)
#define DAINT_MASK			(0xFFFF)

/* S3C_UDC_OTG_DIEPCTL0/DOEPCTL0 device
   control IN/OUT endpoint 0 control register */
#define DEPCTL_EPENA			(0x1<<31)
#define DEPCTL_EPDIS			(0x1<<30)
#define DEPCTL_SETD1PID		(0x1<<29)
#define DEPCTL_SETD0PID		(0x1<<28)
#define DEPCTL_SNAK			(0x1<<27)
#define DEPCTL_CNAK			(0x1<<26)
#define DEPCTL_STALL			(0x1<<21)
#define DEPCTL_TYPE_BIT		(18)
#define DEPCTL_TYPE_MASK		(0x3<<18)
#define DEPCTL_CTRL_TYPE		(0x0<<18)
#define DEPCTL_ISO_TYPE		(0x1<<18)
#define DEPCTL_BULK_TYPE		(0x2<<18)
#define DEPCTL_INTR_TYPE		(0x3<<18)
#define DEPCTL_USBACTEP		(0x1<<15)
#define DEPCTL_NEXT_EP_BIT		(11)
#define DEPCTL_MPS_BIT			(0)
#define DEPCTL_MPS_MASK		(0x7FF)

#define DEPCTL0_MPS_64			(0x0<<0)
#define DEPCTL0_MPS_32			(0x1<<0)
#define DEPCTL0_MPS_16			(0x2<<0)
#define DEPCTL0_MPS_8			(0x3<<0)
#define DEPCTL_MPS_BULK_512		(512<<0)
#define DEPCTL_MPS_INT_MPS_16		(16<<0)

#define DIEPCTL0_NEXT_EP_BIT		(11)


/* S3C_UDC_OTG_DIEPMSK/DOEPMSK device IN/OUT endpoint
   common interrupt mask register */
/* S3C_UDC_OTG_DIEPINTn/DOEPINTn device IN/OUT endpoint interrupt register */
#define BACK2BACK_SETUP_RECEIVED	(0x1<<6)
#define INTKNEPMIS			(0x1<<5)
#define INTKN_TXFEMP			(0x1<<4)
#define NON_ISO_IN_EP_TIMEOUT		(0x1<<3)
#define CTRL_OUT_EP_SETUP_PHASE_DONE	(0x1<<3)
#define AHB_ERROR			(0x1<<2)
#define EPDISBLD			(0x1<<1)
#define TRANSFER_DONE			(0x1<<0)

#define USB_PHY_CTRL_EN0                (0x1 << 0)

/* OPHYPWR */
#define PHY_0_SLEEP                     (0x1 << 5)
#define OTG_DISABLE_0                   (0x1 << 4)
#define ANALOG_PWRDOWN                  (0x1 << 3)
#define FORCE_SUSPEND_0                 (0x1 << 0)

/* URSTCON */
#define HOST_SW_RST                     (0x1 << 4)
#define PHY_SW_RST1                     (0x1 << 3)
#define PHYLNK_SW_RST                   (0x1 << 2)
#define LINK_SW_RST                     (0x1 << 1)
#define PHY_SW_RST0                     (0x1 << 0)

/* OPHYCLK */
#define COMMON_ON_N1                    (0x1 << 7)
#define COMMON_ON_N0                    (0x1 << 4)
#define ID_PULLUP0                      (0x1 << 2)
#define CLK_SEL_24MHZ                   (0x3 << 0)
#define CLK_SEL_12MHZ                   (0x2 << 0)
#define CLK_SEL_48MHZ                   (0x0 << 0)

/* Device Configuration Register DCFG */
#define DEV_SPEED_HIGH_SPEED_20         (0x0 << 0)
#define DEV_SPEED_FULL_SPEED_20         (0x1 << 0)
#define DEV_SPEED_LOW_SPEED_11          (0x2 << 0)
#define DEV_SPEED_FULL_SPEED_11         (0x3 << 0)
#define EP_MISS_CNT(x)                  (x << 18)
#define DEVICE_ADDRESS(x)               (x << 4)

/* Core Reset Register (GRSTCTL) */
#define TX_FIFO_FLUSH                   (0x1 << 5)
#define RX_FIFO_FLUSH                   (0x1 << 4)
#define TX_FIFO_NUMBER(x)               (x << 6)
#define TX_FIFO_FLUSH_ALL               TX_FIFO_NUMBER(0x10)

/* Masks definitions */
#define GINTMSK_INIT	(INT_OUT_EP | INT_IN_EP | INT_RESUME | INT_ENUMDONE\
			| INT_RESET | INT_SUSPEND)
#define DOEPMSK_INIT	(CTRL_OUT_EP_SETUP_PHASE_DONE | AHB_ERROR|TRANSFER_DONE)
#define DIEPMSK_INIT	(NON_ISO_IN_EP_TIMEOUT|AHB_ERROR|TRANSFER_DONE)
#define GAHBCFG_INIT	(PTXFE_HALF | NPTXFE_HALF | MODE_DMA | BURST_INCR4\
			| GBL_INT_UNMASK)

/* Device Endpoint X Transfer Size Register (DIEPTSIZX) */
#define DIEPT_SIZ_PKT_CNT(x)                      (x << 19)
#define DIEPT_SIZ_XFER_SIZE(x)                    (x << 0)

/* Device OUT Endpoint X Transfer Size Register (DOEPTSIZX) */
#define DOEPT_SIZ_PKT_CNT(x)                      (x << 19)
#define DOEPT_SIZ_XFER_SIZE(x)                    (x << 0)
#define DOEPT_SIZ_XFER_SIZE_MAX_EP0               (0x7F << 0)
#define DOEPT_SIZ_XFER_SIZE_MAX_EP                (0x7FFF << 0)

/* Device Endpoint-N Control Register (DIEPCTLn/DOEPCTLn) */
#define DIEPCTL_TX_FIFO_NUM(x)                    (x << 22)
#define DIEPCTL_TX_FIFO_NUM_MASK                  (~DIEPCTL_TX_FIFO_NUM(0xF))

/* Device ALL Endpoints Interrupt Register (DAINT) */
#define DAINT_IN_EP_INT(x)                        (x << 0)
#define DAINT_OUT_EP_INT(x)                       (x << 16)
#endif
Commit	Line	Data
38517a78 ŁM	1	/* linux/arch/arm/plat-s3c/include/plat/regs-otg.h
	2	*
	3	* Copyright (C) 2004 Herbert Poetzl <herbert@13thfloor.at>
	4	*
	5	* Registers remapping:
	6	* Lukasz Majewski <l.majewski@samsumg.com>
	7	*
1a459660	8	* SPDX-License-Identifier: GPL-2.0+
38517a78 ŁM	9	*/
	10
	11	#ifndef __ASM_ARCH_REGS_USB_OTG_HS_H
	12	#define __ASM_ARCH_REGS_USB_OTG_HS_H
	13
	14	/* USB2.0 OTG Controller register */
	15	struct s3c_usbotg_phy {
	16	u32 phypwr;
	17	u32 phyclk;
	18	u32 rstcon;
	19	};
	20
	21	/* Device Logical IN Endpoint-Specific Registers */
	22	struct s3c_dev_in_endp {
	23	u32 diepctl;
	24	u8 res1[4];
	25	u32 diepint;
	26	u8 res2[4];
	27	u32 dieptsiz;
	28	u32 diepdma;
	29	u8 res3[4];
	30	u32 diepdmab;
	31	};
	32
	33	/* Device Logical OUT Endpoint-Specific Registers */
	34	struct s3c_dev_out_endp {
	35	u32 doepctl;
	36	u8 res1[4];
	37	u32 doepint;
	38	u8 res2[4];
	39	u32 doeptsiz;
	40	u32 doepdma;
	41	u8 res3[4];
	42	u32 doepdmab;
	43	};
	44
	45	struct ep_fifo {
	46	u32 fifo;
	47	u8 res[4092];
	48	};
	49
	50	/* USB2.0 OTG Controller register */
	51	struct s3c_usbotg_reg {
	52	/* Core Global Registers */
	53	u32 gotgctl; /* OTG Control & Status */
	54	u32 gotgint; /* OTG Interrupt */
	55	u32 gahbcfg; /* Core AHB Configuration */
	56	u32 gusbcfg; /* Core USB Configuration */
	57	u32 grstctl; /* Core Reset */
	58	u32 gintsts; /* Core Interrupt */
	59	u32 gintmsk; /* Core Interrupt Mask */
	60	u32 grxstsr; /* Receive Status Debug Read/Status Read */
	61	u32 grxstsp; /* Receive Status Debug Pop/Status Pop */
	62	u32 grxfsiz; /* Receive FIFO Size */
	63	u32 gnptxfsiz; /* Non-Periodic Transmit FIFO Size */
	64	u8 res1[216];
	65	u32 dieptxf[15]; /* Device Periodic Transmit FIFO size register */
	66	u8 res2[1728];
	67	/* Device Configuration */
	68	u32 dcfg; /* Device Configuration Register */
	69	u32 dctl; /* Device Control */
	70	u32 dsts; /* Device Status */
	71	u8 res3[4];
	72	u32 diepmsk; /* Device IN Endpoint Common Interrupt Mask */
73	u32 doepmsk; /* Device OUT Endpoint Common Interrupt Mask */
74	u32 daint; /* Device All Endpoints Interrupt */
75	u32 daintmsk; /* Device All Endpoints Interrupt Mask */
76	u8 res4[224];
77	struct s3c_dev_in_endp in_endp[16];
78	struct s3c_dev_out_endp out_endp[16];
79	u8 res5[768];
80	struct ep_fifo ep[16];
81	};
82
83	/===================================================================== /
84	/definitions related to CSR setting /
85
86	/* S3C_UDC_OTG_GOTGCTL */
87	#define B_SESSION_VALID (0x1<<19)
88	#define A_SESSION_VALID (0x1<<18)
89
90	/* S3C_UDC_OTG_GAHBCFG */
91	#define PTXFE_HALF (0<<8)
92	#define PTXFE_ZERO (1<<8)
93	#define NPTXFE_HALF (0<<7)
94	#define NPTXFE_ZERO (1<<7)
95	#define MODE_SLAVE (0<<5)
96	#define MODE_DMA (1<<5)
97	#define BURST_SINGLE (0<<1)
98	#define BURST_INCR (1<<1)
99	#define BURST_INCR4 (3<<1)
100	#define BURST_INCR8 (5<<1)
101	#define BURST_INCR16 (7<<1)
102	#define GBL_INT_UNMASK (1<<0)
103	#define GBL_INT_MASK (0<<0)
104
105	/* S3C_UDC_OTG_GRSTCTL */
106	#define AHB_MASTER_IDLE (1u<<31)
107	#define CORE_SOFT_RESET (0x1<<0)
108
109	/* S3C_UDC_OTG_GINTSTS/S3C_UDC_OTG_GINTMSK core interrupt register */
110	#define INT_RESUME (1u<<31)
111	#define INT_DISCONN (0x1<<29)
112	#define INT_CONN_ID_STS_CNG (0x1<<28)
113	#define INT_OUT_EP (0x1<<19)
114	#define INT_IN_EP (0x1<<18)
115	#define INT_ENUMDONE (0x1<<13)
116	#define INT_RESET (0x1<<12)
117	#define INT_SUSPEND (0x1<<11)
118	#define INT_EARLY_SUSPEND (0x1<<10)
119	#define INT_NP_TX_FIFO_EMPTY (0x1<<5)
120	#define INT_RX_FIFO_NOT_EMPTY (0x1<<4)
121	#define INT_SOF (0x1<<3)
122	#define INT_DEV_MODE (0x0<<0)
123	#define INT_HOST_MODE (0x1<<1)
124	#define INT_GOUTNakEff (0x01<<7)
125	#define INT_GINNakEff (0x01<<6)
126
127	#define FULL_SPEED_CONTROL_PKT_SIZE 8
128	#define FULL_SPEED_BULK_PKT_SIZE 64
129
130	#define HIGH_SPEED_CONTROL_PKT_SIZE 64
131	#define HIGH_SPEED_BULK_PKT_SIZE 512
132
133	#define RX_FIFO_SIZE (1024*4)
134	#define NPTX_FIFO_SIZE (1024*4)
135	#define PTX_FIFO_SIZE (1536*1)
136
137	#define DEPCTL_TXFNUM_0 (0x0<<22)
138	#define DEPCTL_TXFNUM_1 (0x1<<22)
139	#define DEPCTL_TXFNUM_2 (0x2<<22)
140	#define DEPCTL_TXFNUM_3 (0x3<<22)
141	#define DEPCTL_TXFNUM_4 (0x4<<22)
142
143	/* Enumeration speed */
144	#define USB_HIGH_30_60MHZ (0x0<<1)
145	#define USB_FULL_30_60MHZ (0x1<<1)
146	#define USB_LOW_6MHZ (0x2<<1)
147	#define USB_FULL_48MHZ (0x3<<1)
148
149	/* S3C_UDC_OTG_GRXSTSP STATUS */
150	#define OUT_PKT_RECEIVED (0x2<<17)
151	#define OUT_TRANSFER_COMPLELTED (0x3<<17)
152	#define SETUP_TRANSACTION_COMPLETED (0x4<<17)
153	#define SETUP_PKT_RECEIVED (0x6<<17)
154	#define GLOBAL_OUT_NAK (0x1<<17)
155
156	/* S3C_UDC_OTG_DCTL device control register */
157	#define NORMAL_OPERATION (0x1<<0)
158	#define SOFT_DISCONNECT (0x1<<1)
159
160	/* S3C_UDC_OTG_DAINT device all endpoint interrupt register */
161	#define DAINT_OUT_BIT (16)
162	#define DAINT_MASK (0xFFFF)
163
164	/* S3C_UDC_OTG_DIEPCTL0/DOEPCTL0 device
165	control IN/OUT endpoint 0 control register */
166	#define DEPCTL_EPENA (0x1<<31)
167	#define DEPCTL_EPDIS (0x1<<30)
168	#define DEPCTL_SETD1PID (0x1<<29)
169	#define DEPCTL_SETD0PID (0x1<<28)
170	#define DEPCTL_SNAK (0x1<<27)
171	#define DEPCTL_CNAK (0x1<<26)
172	#define DEPCTL_STALL (0x1<<21)
173	#define DEPCTL_TYPE_BIT (18)
174	#define DEPCTL_TYPE_MASK (0x3<<18)
175	#define DEPCTL_CTRL_TYPE (0x0<<18)
176	#define DEPCTL_ISO_TYPE (0x1<<18)
177	#define DEPCTL_BULK_TYPE (0x2<<18)
178	#define DEPCTL_INTR_TYPE (0x3<<18)
179	#define DEPCTL_USBACTEP (0x1<<15)
180	#define DEPCTL_NEXT_EP_BIT (11)
181	#define DEPCTL_MPS_BIT (0)
182	#define DEPCTL_MPS_MASK (0x7FF)
183
184	#define DEPCTL0_MPS_64 (0x0<<0)
185	#define DEPCTL0_MPS_32 (0x1<<0)
186	#define DEPCTL0_MPS_16 (0x2<<0)
187	#define DEPCTL0_MPS_8 (0x3<<0)
188	#define DEPCTL_MPS_BULK_512 (512<<0)
189	#define DEPCTL_MPS_INT_MPS_16 (16<<0)
190
191	#define DIEPCTL0_NEXT_EP_BIT (11)
192
193
194	/* S3C_UDC_OTG_DIEPMSK/DOEPMSK device IN/OUT endpoint
195	common interrupt mask register */
196	/* S3C_UDC_OTG_DIEPINTn/DOEPINTn device IN/OUT endpoint interrupt register */
197	#define BACK2BACK_SETUP_RECEIVED (0x1<<6)
198	#define INTKNEPMIS (0x1<<5)
199	#define INTKN_TXFEMP (0x1<<4)
200	#define NON_ISO_IN_EP_TIMEOUT (0x1<<3)
201	#define CTRL_OUT_EP_SETUP_PHASE_DONE (0x1<<3)
202	#define AHB_ERROR (0x1<<2)
203	#define EPDISBLD (0x1<<1)
204	#define TRANSFER_DONE (0x1<<0)
205
206	#define USB_PHY_CTRL_EN0 (0x1 << 0)
207
208	/* OPHYPWR */
209	#define PHY_0_SLEEP (0x1 << 5)
210	#define OTG_DISABLE_0 (0x1 << 4)
211	#define ANALOG_PWRDOWN (0x1 << 3)
212	#define FORCE_SUSPEND_0 (0x1 << 0)
213
214	/* URSTCON */
215	#define HOST_SW_RST (0x1 << 4)
216	#define PHY_SW_RST1 (0x1 << 3)
217	#define PHYLNK_SW_RST (0x1 << 2)
218	#define LINK_SW_RST (0x1 << 1)
219	#define PHY_SW_RST0 (0x1 << 0)
220
221	/* OPHYCLK */
222	#define COMMON_ON_N1 (0x1 << 7)
223	#define COMMON_ON_N0 (0x1 << 4)
224	#define ID_PULLUP0 (0x1 << 2)
225	#define CLK_SEL_24MHZ (0x3 << 0)
226	#define CLK_SEL_12MHZ (0x2 << 0)
227	#define CLK_SEL_48MHZ (0x0 << 0)
228
229	/* Device Configuration Register DCFG */
230	#define DEV_SPEED_HIGH_SPEED_20 (0x0 << 0)
231	#define DEV_SPEED_FULL_SPEED_20 (0x1 << 0)
232	#define DEV_SPEED_LOW_SPEED_11 (0x2 << 0)
233	#define DEV_SPEED_FULL_SPEED_11 (0x3 << 0)
234	#define EP_MISS_CNT(x) (x << 18)
235	#define DEVICE_ADDRESS(x) (x << 4)
236
237	/* Core Reset Register (GRSTCTL) */
238	#define TX_FIFO_FLUSH (0x1 << 5)
239	#define RX_FIFO_FLUSH (0x1 << 4)
240	#define TX_FIFO_NUMBER(x) (x << 6)
241	#define TX_FIFO_FLUSH_ALL TX_FIFO_NUMBER(0x10)
242
243	/* Masks definitions */
244	#define GINTMSK_INIT (INT_OUT_EP \| INT_IN_EP \| INT_RESUME \| INT_ENUMDONE\
245	\| INT_RESET \| INT_SUSPEND)
246	#define DOEPMSK_INIT (CTRL_OUT_EP_SETUP_PHASE_DONE \| AHB_ERROR\|TRANSFER_DONE)
247	#define DIEPMSK_INIT (NON_ISO_IN_EP_TIMEOUT\|AHB_ERROR\|TRANSFER_DONE)
248	#define GAHBCFG_INIT (PTXFE_HALF \| NPTXFE_HALF \| MODE_DMA \| BURST_INCR4\
249	\| GBL_INT_UNMASK)
250
251	/* Device Endpoint X Transfer Size Register (DIEPTSIZX) */
252	#define DIEPT_SIZ_PKT_CNT(x) (x << 19)
253	#define DIEPT_SIZ_XFER_SIZE(x) (x << 0)
254
255	/* Device OUT Endpoint X Transfer Size Register (DOEPTSIZX) */
256	#define DOEPT_SIZ_PKT_CNT(x) (x << 19)
257	#define DOEPT_SIZ_XFER_SIZE(x) (x << 0)
258	#define DOEPT_SIZ_XFER_SIZE_MAX_EP0 (0x7F << 0)
259	#define DOEPT_SIZ_XFER_SIZE_MAX_EP (0x7FFF << 0)
260
261	/* Device Endpoint-N Control Register (DIEPCTLn/DOEPCTLn) */
262	#define DIEPCTL_TX_FIFO_NUM(x) (x << 22)
263	#define DIEPCTL_TX_FIFO_NUM_MASK (~DIEPCTL_TX_FIFO_NUM(0xF))
264
265	/* Device ALL Endpoints Interrupt Register (DAINT) */
266	#define DAINT_IN_EP_INT(x) (x << 0)
267	#define DAINT_OUT_EP_INT(x) (x << 16)
268	#endif