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Commit | Line | Data |
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6e7e9294 MY |
1 | # |
2 | # USB Host Controller Drivers | |
3 | # | |
4 | comment "USB Host Controller Drivers" | |
5 | ||
2b58e1b7 MY |
6 | config USB_HOST |
7 | bool | |
8 | ||
6e7e9294 MY |
9 | config USB_XHCI_HCD |
10 | bool "xHCI HCD (USB 3.0) support" | |
2b58e1b7 | 11 | select USB_HOST |
6e7e9294 MY |
12 | ---help--- |
13 | The eXtensible Host Controller Interface (xHCI) is standard for USB 3.0 | |
14 | "SuperSpeed" host controller hardware. | |
15 | ||
6e7e9294 MY |
16 | if USB_XHCI_HCD |
17 | ||
10db7500 MY |
18 | config USB_XHCI_DWC3 |
19 | bool "DesignWare USB3 DRD Core Support" | |
20 | help | |
21 | Say Y or if your system has a Dual Role SuperSpeed | |
22 | USB controller based on the DesignWare USB3 IP Core. | |
23 | ||
81c1f6f0 SR |
24 | config USB_XHCI_MVEBU |
25 | bool "MVEBU USB 3.0 support" | |
26 | default y | |
27 | depends on ARCH_MVEBU | |
81192b79 | 28 | select DM_REGULATOR |
81c1f6f0 SR |
29 | help |
30 | Choose this option to add support for USB 3.0 driver on mvebu | |
31 | SoCs, which includes Armada8K, Armada3700 and other Armada | |
32 | family SoCs. | |
33 | ||
d7cde281 BM |
34 | config USB_XHCI_PCI |
35 | bool "Support for PCI-based xHCI USB controller" | |
978f6a3b | 36 | depends on DM_USB |
d7cde281 BM |
37 | default y if X86 |
38 | help | |
39 | Enables support for the PCI-based xHCI controller. | |
40 | ||
f7bb27a5 KY |
41 | config USB_XHCI_ROCKCHIP |
42 | bool "Support for Rockchip on-chip xHCI USB controller" | |
43 | depends on ARCH_ROCKCHIP | |
e85f00ab MD |
44 | depends on DM_REGULATOR |
45 | depends on DM_USB | |
f7bb27a5 KY |
46 | default y |
47 | help | |
48 | Enables support for the on-chip xHCI controller on Rockchip SoCs. | |
49 | ||
40d1a31e PC |
50 | config USB_XHCI_STI |
51 | bool "Support for STMicroelectronics STiH407 family on-chip xHCI USB controller" | |
52 | depends on ARCH_STI | |
53 | default y | |
54 | help | |
55 | Enables support for the on-chip xHCI controller on STMicroelectronics | |
56 | STiH407 family SoCs. This is a driver for the dwc3 to provide the glue logic | |
57 | to configure the controller. | |
58 | ||
63d74747 MS |
59 | config USB_XHCI_ZYNQMP |
60 | bool "Support for Xilinx ZynqMP on-chip xHCI USB controller" | |
61 | depends on ARCH_ZYNQMP | |
62 | help | |
63 | Enables support for the on-chip xHCI controller on Xilinx ZynqMP SoCs. | |
64 | ||
ef3f3b81 UM |
65 | config USB_XHCI_DRA7XX_INDEX |
66 | int "DRA7XX xHCI USB index" | |
67 | range 0 1 | |
68 | default 0 | |
69 | depends on DRA7XX | |
70 | help | |
71 | Select the DRA7XX xHCI USB index. | |
72 | Current supported values: 0, 1. | |
73 | ||
93cb8247 | 74 | endif # USB_XHCI_HCD |
fee331f6 | 75 | |
6e7e9294 MY |
76 | config USB_EHCI_HCD |
77 | bool "EHCI HCD (USB 2.0) support" | |
64d6ac5b | 78 | default y if ARCH_MX5 || ARCH_MX6 |
2b58e1b7 | 79 | select USB_HOST |
6e7e9294 MY |
80 | ---help--- |
81 | The Enhanced Host Controller Interface (EHCI) is standard for USB 2.0 | |
82 | "high speed" (480 Mbit/sec, 60 Mbyte/sec) host controller hardware. | |
83 | If your USB host controller supports USB 2.0, you will likely want to | |
84 | configure this Host Controller Driver. | |
85 | ||
86 | EHCI controllers are packaged with "companion" host controllers (OHCI | |
87 | or UHCI) to handle USB 1.1 devices connected to root hub ports. Ports | |
88 | will connect to EHCI if the device is high speed, otherwise they | |
89 | connect to a companion controller. If you configure EHCI, you should | |
90 | probably configure the OHCI (for NEC and some other vendors) USB Host | |
91 | Controller Driver or UHCI (for Via motherboards) Host Controller | |
92 | Driver too. | |
93 | ||
94 | You may want to read <file:Documentation/usb/ehci.txt>. | |
95 | ||
6e7e9294 MY |
96 | if USB_EHCI_HCD |
97 | ||
17b68b5a WY |
98 | config USB_EHCI_ATMEL |
99 | bool "Support for Atmel on-chip EHCI USB controller" | |
100 | depends on ARCH_AT91 | |
101 | default y | |
102 | ---help--- | |
103 | Enables support for the on-chip EHCI controller on Atmel chips. | |
104 | ||
cd48225b | 105 | config USB_EHCI_MARVELL |
80f1f320 TR |
106 | bool "Support for Marvell on-chip EHCI USB controller" |
107 | depends on ARCH_MVEBU || KIRKWOOD || ORION5X | |
cd48225b SR |
108 | default y |
109 | ---help--- | |
110 | Enables support for the on-chip EHCI controller on MVEBU SoCs. | |
111 | ||
919e802c NK |
112 | config USB_EHCI_MX6 |
113 | bool "Support for i.MX6 on-chip EHCI USB controller" | |
114 | depends on ARCH_MX6 | |
115 | default y | |
116 | ---help--- | |
117 | Enables support for the on-chip EHCI controller on i.MX6 SoCs. | |
118 | ||
2deebe24 SA |
119 | config USB_EHCI_MX7 |
120 | bool "Support for i.MX7 on-chip EHCI USB controller" | |
121 | depends on ARCH_MX7 | |
122 | default y | |
123 | ---help--- | |
124 | Enables support for the on-chip EHCI controller on i.MX7 SoCs. | |
125 | ||
1d1ab61c TR |
126 | config USB_EHCI_OMAP |
127 | bool "Support for OMAP3+ on-chip EHCI USB controller" | |
128 | depends on ARCH_OMAP2PLUS | |
129 | default y | |
130 | ---help--- | |
131 | Enables support for the on-chip EHCI controller on OMAP3 and later | |
132 | SoCs. | |
133 | ||
c4483093 SA |
134 | if USB_EHCI_MX7 |
135 | ||
136 | config MXC_USB_OTG_HACTIVE | |
137 | bool "USB Power pin high active" | |
138 | ---help--- | |
139 | Set the USB Power pin polarity to be high active (PWR_POL) | |
140 | ||
141 | endif | |
142 | ||
5a822118 MK |
143 | config USB_EHCI_MSM |
144 | bool "Support for Qualcomm on-chip EHCI USB controller" | |
145 | depends on DM_USB | |
146 | select USB_ULPI_VIEWPORT | |
147 | default n | |
148 | ---help--- | |
149 | Enables support for the on-chip EHCI controller on Qualcomm | |
150 | Snapdragon SoCs. | |
151 | This driver supports combination of Chipidea USB controller | |
152 | and Synapsys USB PHY in host mode only. | |
153 | ||
a11a5b8a BM |
154 | config USB_EHCI_PCI |
155 | bool "Support for PCI-based EHCI USB controller" | |
156 | default y if X86 | |
157 | help | |
158 | Enables support for the PCI-based EHCI controller. | |
159 | ||
2cdc778b SDPP |
160 | config USB_EHCI_ZYNQ |
161 | bool "Support for Xilinx Zynq on-chip EHCI USB controller" | |
162 | depends on ARCH_ZYNQ | |
163 | default y | |
164 | ---help--- | |
165 | Enable support for Zynq on-chip EHCI USB controller | |
166 | ||
90fbb282 AB |
167 | config USB_EHCI_GENERIC |
168 | bool "Support for generic EHCI USB controller" | |
169 | depends on OF_CONTROL | |
170 | depends on DM_USB | |
171 | default n | |
172 | ---help--- | |
173 | Enables support for generic EHCI controller. | |
174 | ||
93cb8247 MY |
175 | endif # USB_EHCI_HCD |
176 | ||
177 | config USB_OHCI_HCD | |
178 | bool "OHCI HCD (USB 1.1) support" | |
179 | ---help--- | |
180 | The Open Host Controller Interface (OHCI) is a standard for accessing | |
181 | USB 1.1 host controller hardware. It does more in hardware than Intel's | |
182 | UHCI specification. If your USB host controller follows the OHCI spec, | |
183 | say Y. On most non-x86 systems, and on x86 hardware that's not using a | |
184 | USB controller from Intel or VIA, this is appropriate. If your host | |
185 | controller doesn't use PCI, this is probably appropriate. For a PCI | |
186 | based system where you're not sure, the "lspci -v" entry will list the | |
187 | right "prog-if" for your USB controller(s): EHCI, OHCI, or UHCI. | |
188 | ||
189 | if USB_OHCI_HCD | |
190 | ||
191 | config USB_OHCI_GENERIC | |
192 | bool "Support for generic OHCI USB controller" | |
193 | depends on OF_CONTROL | |
194 | depends on DM_USB | |
2b58e1b7 | 195 | select USB_HOST |
93cb8247 MY |
196 | ---help--- |
197 | Enables support for generic OHCI controller. | |
198 | ||
199 | endif # USB_OHCI_HCD | |
96d8284b MY |
200 | |
201 | config USB_UHCI_HCD | |
202 | bool "UHCI HCD (most Intel and VIA) support" | |
2b58e1b7 | 203 | select USB_HOST |
96d8284b MY |
204 | ---help--- |
205 | The Universal Host Controller Interface is a standard by Intel for | |
206 | accessing the USB hardware in the PC (which is also called the USB | |
207 | host controller). If your USB host controller conforms to this | |
208 | standard, you may want to say Y, but see below. All recent boards | |
209 | with Intel PCI chipsets (like intel 430TX, 440FX, 440LX, 440BX, | |
210 | i810, i820) conform to this standard. Also all VIA PCI chipsets | |
211 | (like VIA VP2, VP3, MVP3, Apollo Pro, Apollo Pro II or Apollo Pro | |
212 | 133) and LEON/GRLIB SoCs with the GRUSBHC controller. | |
213 | If unsure, say Y. | |
214 | ||
215 | if USB_UHCI_HCD | |
216 | ||
217 | endif # USB_UHCI_HCD | |
4ac72f5c PT |
218 | |
219 | config USB_DWC2 | |
220 | bool "DesignWare USB2 Core support" | |
221 | select USB_HOST | |
222 | ---help--- | |
223 | The DesignWare USB 2.0 controller is compliant with the | |
224 | USB-Implementers Forum (USB-IF) USB 2.0 specifications. | |
225 | Hi-Speed (480 Mbps), Full-Speed (12 Mbps), and Low-Speed (1.5 Mbps) | |
226 | operation is compliant to the controller Supplement. If you want to | |
227 | enable this controller in host mode, say Y. |