[people/ms/u-boot.git] / drivers / usb / host / ehci-fsl.c

/*
 * (C) Copyright 2009, 2011, 2016 Freescale Semiconductor, Inc.
 *
 * (C) Copyright 2008, Excito Elektronik i Sk=E5ne AB
 *
 * Author: Tor Krill tor@excito.com
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <pci.h>
#include <usb.h>
#include <asm/io.h>
#include <usb/ehci-ci.h>
#include <hwconfig.h>
#include <fsl_usb.h>
#include <fdt_support.h>
#include <dm.h>

#include "ehci.h"

DECLARE_GLOBAL_DATA_PTR;

#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#endif

#ifdef CONFIG_DM_USB
struct ehci_fsl_priv {
	struct ehci_ctrl ehci;
	fdt_addr_t hcd_base;
	char *phy_type;
};
#endif

static void set_txfifothresh(struct usb_ehci *, u32);
#ifdef CONFIG_DM_USB
static int ehci_fsl_init(struct ehci_fsl_priv *priv, struct usb_ehci *ehci,
		  struct ehci_hccr *hccr, struct ehci_hcor *hcor);
#else
static int ehci_fsl_init(int index, struct usb_ehci *ehci,
			 struct ehci_hccr *hccr, struct ehci_hcor *hcor);
#endif

/* Check USB PHY clock valid */
static int usb_phy_clk_valid(struct usb_ehci *ehci)
{
	if (!((in_be32(&ehci->control) & PHY_CLK_VALID) ||
			in_be32(&ehci->prictrl))) {
		printf("USB PHY clock invalid!\n");
		return 0;
	} else {
		return 1;
	}
}

#ifdef CONFIG_DM_USB
static int ehci_fsl_ofdata_to_platdata(struct udevice *dev)
{
	struct ehci_fsl_priv *priv = dev_get_priv(dev);
	const void *prop;

	prop = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy_type",
			   NULL);
	if (prop) {
		priv->phy_type = (char *)prop;
		debug("phy_type %s\n", priv->phy_type);
	}

	return 0;
}

static int ehci_fsl_init_after_reset(struct ehci_ctrl *ctrl)
{
	struct usb_ehci *ehci = NULL;
	struct ehci_fsl_priv *priv = container_of(ctrl, struct ehci_fsl_priv,
						   ehci);

	ehci = (struct usb_ehci *)priv->hcd_base;
	if (ehci_fsl_init(priv, ehci, priv->ehci.hccr, priv->ehci.hcor) < 0)
		return -ENXIO;

	return 0;
}

static const struct ehci_ops fsl_ehci_ops = {
	.init_after_reset = ehci_fsl_init_after_reset,
};

static int ehci_fsl_probe(struct udevice *dev)
{
	struct ehci_fsl_priv *priv = dev_get_priv(dev);
	struct usb_ehci *ehci = NULL;
	struct ehci_hccr *hccr;
	struct ehci_hcor *hcor;

	/*
	 * Get the base address for EHCI controller from the device node
	 */
	priv->hcd_base = devfdt_get_addr(dev);
	if (priv->hcd_base == FDT_ADDR_T_NONE) {
		debug("Can't get the EHCI register base address\n");
		return -ENXIO;
	}
	ehci = (struct usb_ehci *)priv->hcd_base;
	hccr = (struct ehci_hccr *)(&ehci->caplength);
	hcor = (struct ehci_hcor *)
		((u32)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));

	if (ehci_fsl_init(priv, ehci, hccr, hcor) < 0)
		return -ENXIO;

	debug("ehci-fsl: init hccr %x and hcor %x hc_length %d\n",
	      (u32)hccr, (u32)hcor,
	      (u32)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));

	return ehci_register(dev, hccr, hcor, &fsl_ehci_ops, 0, USB_INIT_HOST);
}

static const struct udevice_id ehci_usb_ids[] = {
	{ .compatible = "fsl-usb2-mph", },
	{ .compatible = "fsl-usb2-dr", },
	{ }
};

U_BOOT_DRIVER(ehci_fsl) = {
	.name	= "ehci_fsl",
	.id	= UCLASS_USB,
	.of_match = ehci_usb_ids,
	.ofdata_to_platdata = ehci_fsl_ofdata_to_platdata,
	.probe = ehci_fsl_probe,
	.remove = ehci_deregister,
	.ops	= &ehci_usb_ops,
	.platdata_auto_alloc_size = sizeof(struct usb_platdata),
	.priv_auto_alloc_size = sizeof(struct ehci_fsl_priv),
	.flags	= DM_FLAG_ALLOC_PRIV_DMA,
};
#else
/*
 * Create the appropriate control structures to manage
 * a new EHCI host controller.
 *
 * Excerpts from linux ehci fsl driver.
 */
int ehci_hcd_init(int index, enum usb_init_type init,
		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
	struct usb_ehci *ehci = NULL;

	switch (index) {
	case 0:
		ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
		break;
	case 1:
		ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB2_ADDR;
		break;
	default:
		printf("ERROR: wrong controller index!!\n");
		return -EINVAL;
	};

	*hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
	*hcor = (struct ehci_hcor *)((uint32_t) *hccr +
			HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));

	return ehci_fsl_init(index, ehci, *hccr, *hcor);
}

/*
 * Destroy the appropriate control structures corresponding
 * the the EHCI host controller.
 */
int ehci_hcd_stop(int index)
{
	return 0;
}
#endif

#ifdef CONFIG_DM_USB
static int ehci_fsl_init(struct ehci_fsl_priv *priv, struct usb_ehci *ehci,
		  struct ehci_hccr *hccr, struct ehci_hcor *hcor)
#else
static int ehci_fsl_init(int index, struct usb_ehci *ehci,
			 struct ehci_hccr *hccr, struct ehci_hcor *hcor)
#endif
{
	const char *phy_type = NULL;
#ifndef CONFIG_DM_USB
	size_t len;
	char current_usb_controller[5];
#endif
#ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
	char usb_phy[5];

	usb_phy[0] = '\0';
#endif
	if (has_erratum_a007075()) {
		/*
		 * A 5ms delay is needed after applying soft-reset to the
		 * controller to let external ULPI phy come out of reset.
		 * This delay needs to be added before re-initializing
		 * the controller after soft-resetting completes
		 */
		mdelay(5);
	}

	/* Set to Host mode */
	setbits_le32(&ehci->usbmode, CM_HOST);

	out_be32(&ehci->snoop1, SNOOP_SIZE_2GB);
	out_be32(&ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB);

	/* Init phy */
#ifdef CONFIG_DM_USB
	if (priv->phy_type)
		phy_type = priv->phy_type;
#else
	memset(current_usb_controller, '\0', 5);
	snprintf(current_usb_controller, sizeof(current_usb_controller),
		 "usb%d", index+1);

	if (hwconfig_sub(current_usb_controller, "phy_type"))
		phy_type = hwconfig_subarg(current_usb_controller,
				"phy_type", &len);
#endif
	else
		phy_type = env_get("usb_phy_type");

	if (!phy_type) {
#ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
		/* if none specified assume internal UTMI */
		strcpy(usb_phy, "utmi");
		phy_type = usb_phy;
#else
		printf("WARNING: USB phy type not defined !!\n");
		return -1;
#endif
	}

	if (!strncmp(phy_type, "utmi", 4)) {
#if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
		clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
				PHY_CLK_SEL_UTMI);
		clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
				UTMI_PHY_EN);
		udelay(1000); /* delay required for PHY Clk to appear */
#endif
		out_le32(&(hcor)->or_portsc[0], PORT_PTS_UTMI);
		clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
				USB_EN);
	} else {
		clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
				PHY_CLK_SEL_ULPI);
		clrsetbits_be32(&ehci->control, UTMI_PHY_EN |
				CONTROL_REGISTER_W1C_MASK, USB_EN);
		udelay(1000); /* delay required for PHY Clk to appear */
		if (!usb_phy_clk_valid(ehci))
			return -EINVAL;
		out_le32(&(hcor)->or_portsc[0], PORT_PTS_ULPI);
	}

	out_be32(&ehci->prictrl, 0x0000000c);
	out_be32(&ehci->age_cnt_limit, 0x00000040);
	out_be32(&ehci->sictrl, 0x00000001);

	in_le32(&ehci->usbmode);

	if (has_erratum_a007798())
		set_txfifothresh(ehci, TXFIFOTHRESH);

	if (has_erratum_a004477()) {
		/*
		 * When reset is issued while any ULPI transaction is ongoing
		 * then it may result to corruption of ULPI Function Control
		 * Register which eventually causes phy clock to enter low
		 * power mode which stops the clock. Thus delay is required
		 * before reset to let ongoing ULPI transaction complete.
		 */
		udelay(1);
	}
	return 0;
}

/*
 * Setting the value of TXFIFO_THRESH field in TXFILLTUNING register
 * to counter DDR latencies in writing data into Tx buffer.
 * This prevents Tx buffer from getting underrun
 */
static void set_txfifothresh(struct usb_ehci *ehci, u32 txfifo_thresh)
{
	u32 cmd;
	cmd = ehci_readl(&ehci->txfilltuning);
	cmd &= ~TXFIFO_THRESH_MASK;
	cmd |= TXFIFO_THRESH(txfifo_thresh);
	ehci_writel(&ehci->txfilltuning, cmd);
}
Commit	Line	Data
6b92487d	1	/*
ba699a5f	2	* (C) Copyright 2009, 2011, 2016 Freescale Semiconductor, Inc.
4ef01010	3	*
6b92487d MT	4	* (C) Copyright 2008, Excito Elektronik i Sk=E5ne AB
	5	*
	6	* Author: Tor Krill tor@excito.com
	7	*
1a459660	8	* SPDX-License-Identifier: GPL-2.0+
6b92487d MT	9	*/
	10
	11	#include <common.h>
	12	#include <pci.h>
	13	#include <usb.h>
6b92487d	14	#include <asm/io.h>
e162c6b1	15	#include <usb/ehci-ci.h>
1b719e66	16	#include <hwconfig.h>
c26c80a1	17	#include <fsl_usb.h>
a1c04e27	18	#include <fdt_support.h>
ba699a5f	19	#include <dm.h>
6b92487d	20
2731b9a8	21	#include "ehci.h"
6b92487d	22
ba699a5f RB	23	DECLARE_GLOBAL_DATA_PTR;
ba699a5f RB	24
a1c04e27 NB	25	#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
	26	#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
	27	#endif
	28
ba699a5f RB	29	#ifdef CONFIG_DM_USB
	30	struct ehci_fsl_priv {
	31	struct ehci_ctrl ehci;
	32	fdt_addr_t hcd_base;
	33	char *phy_type;
	34	};
	35	#endif
	36
896720ce	37	static void set_txfifothresh(struct usb_ehci *, u32);
ba699a5f RB	38	#ifdef CONFIG_DM_USB
	39	static int ehci_fsl_init(struct ehci_fsl_priv priv, struct usb_ehci ehci,
	40	struct ehci_hccr hccr, struct ehci_hcor hcor);
	41	#else
1e61ce9f RB	42	static int ehci_fsl_init(int index, struct usb_ehci *ehci,
1e61ce9f RB	43	struct ehci_hccr hccr, struct ehci_hcor hcor);
ba699a5f	44	#endif
896720ce	45
047cea36 SL	46	/* Check USB PHY clock valid */
	47	static int usb_phy_clk_valid(struct usb_ehci *ehci)
	48	{
	49	if (!((in_be32(&ehci->control) & PHY_CLK_VALID) \|\|
	50	in_be32(&ehci->prictrl))) {
	51	printf("USB PHY clock invalid!\n");
	52	return 0;
	53	} else {
	54	return 1;
	55	}
	56	}
	57
ba699a5f RB	58	#ifdef CONFIG_DM_USB
	59	static int ehci_fsl_ofdata_to_platdata(struct udevice *dev)
	60	{
	61	struct ehci_fsl_priv *priv = dev_get_priv(dev);
	62	const void *prop;
	63
e160f7d4	64	prop = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy_type",
ba699a5f RB	65	NULL);
	66	if (prop) {
	67	priv->phy_type = (char *)prop;
	68	debug("phy_type %s\n", priv->phy_type);
	69	}
	70
	71	return 0;
	72	}
	73
	74	static int ehci_fsl_init_after_reset(struct ehci_ctrl *ctrl)
	75	{
	76	struct usb_ehci *ehci = NULL;
	77	struct ehci_fsl_priv *priv = container_of(ctrl, struct ehci_fsl_priv,
	78	ehci);
	79
	80	ehci = (struct usb_ehci *)priv->hcd_base;
	81	if (ehci_fsl_init(priv, ehci, priv->ehci.hccr, priv->ehci.hcor) < 0)
	82	return -ENXIO;
	83
	84	return 0;
	85	}
	86
	87	static const struct ehci_ops fsl_ehci_ops = {
	88	.init_after_reset = ehci_fsl_init_after_reset,
	89	};
	90
	91	static int ehci_fsl_probe(struct udevice *dev)
	92	{
	93	struct ehci_fsl_priv *priv = dev_get_priv(dev);
	94	struct usb_ehci *ehci = NULL;
	95	struct ehci_hccr *hccr;
	96	struct ehci_hcor *hcor;
	97
	98	/*
	99	* Get the base address for EHCI controller from the device node
	100	*/
a821c4af	101	priv->hcd_base = devfdt_get_addr(dev);
ba699a5f RB	102	if (priv->hcd_base == FDT_ADDR_T_NONE) {
	103	debug("Can't get the EHCI register base address\n");
	104	return -ENXIO;
	105	}
	106	ehci = (struct usb_ehci *)priv->hcd_base;
	107	hccr = (struct ehci_hccr *)(&ehci->caplength);
	108	hcor = (struct ehci_hcor *)
	109	((u32)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
	110
	111	if (ehci_fsl_init(priv, ehci, hccr, hcor) < 0)
	112	return -ENXIO;
	113
	114	debug("ehci-fsl: init hccr %x and hcor %x hc_length %d\n",
	115	(u32)hccr, (u32)hcor,
	116	(u32)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
	117
	118	return ehci_register(dev, hccr, hcor, &fsl_ehci_ops, 0, USB_INIT_HOST);
	119	}
	120
ba699a5f RB	121	static const struct udevice_id ehci_usb_ids[] = {
	122	{ .compatible = "fsl-usb2-mph", },
	123	{ .compatible = "fsl-usb2-dr", },
	124	{ }
	125	};
	126
	127	U_BOOT_DRIVER(ehci_fsl) = {
	128	.name = "ehci_fsl",
	129	.id = UCLASS_USB,
	130	.of_match = ehci_usb_ids,
	131	.ofdata_to_platdata = ehci_fsl_ofdata_to_platdata,
	132	.probe = ehci_fsl_probe,
40527342	133	.remove = ehci_deregister,
ba699a5f RB	134	.ops = &ehci_usb_ops,
	135	.platdata_auto_alloc_size = sizeof(struct usb_platdata),
	136	.priv_auto_alloc_size = sizeof(struct ehci_fsl_priv),
	137	.flags = DM_FLAG_ALLOC_PRIV_DMA,
	138	};
	139	#else
6b92487d MT	140	/*
	141	* Create the appropriate control structures to manage
	142	* a new EHCI host controller.
	143	*
	144	* Excerpts from linux ehci fsl driver.
	145	*/
127efc4f TK	146	int ehci_hcd_init(int index, enum usb_init_type init,
127efc4f TK	147	struct ehci_hccr hccr, struct ehci_hcor hcor)
6b92487d	148	{
77354e9d	149	struct usb_ehci *ehci = NULL;
1e61ce9f RB	150
	151	switch (index) {
	152	case 0:
	153	ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
	154	break;
	155	case 1:
	156	ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB2_ADDR;
	157	break;
	158	default:
	159	printf("ERROR: wrong controller index!!\n");
	160	return -EINVAL;
	161	};
	162
	163	hccr = (struct ehci_hccr )((uint32_t)&ehci->caplength);
	164	hcor = (struct ehci_hcor )((uint32_t) *hccr +
	165	HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
	166
	167	return ehci_fsl_init(index, ehci, hccr, hcor);
	168	}
	169
	170	/*
	171	* Destroy the appropriate control structures corresponding
	172	* the the EHCI host controller.
	173	*/
	174	int ehci_hcd_stop(int index)
	175	{
	176	return 0;
	177	}
ba699a5f	178	#endif
1e61ce9f	179
ba699a5f RB	180	#ifdef CONFIG_DM_USB
	181	static int ehci_fsl_init(struct ehci_fsl_priv priv, struct usb_ehci ehci,
	182	struct ehci_hccr hccr, struct ehci_hcor hcor)
	183	#else
1e61ce9f RB	184	static int ehci_fsl_init(int index, struct usb_ehci *ehci,
1e61ce9f RB	185	struct ehci_hccr hccr, struct ehci_hcor hcor)
ba699a5f	186	#endif
1e61ce9f	187	{
1b719e66	188	const char *phy_type = NULL;
ba699a5f	189	#ifndef CONFIG_DM_USB
1b719e66	190	size_t len;
0ecb15c8	191	char current_usb_controller[5];
ba699a5f	192	#endif
dd22f7cf KG	193	#ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
dd22f7cf KG	194	char usb_phy[5];
1b719e66 RM	195
1b719e66 RM	196	usb_phy[0] = '\0';
dd22f7cf	197	#endif
11856919 NB	198	if (has_erratum_a007075()) {
	199	/*
	200	* A 5ms delay is needed after applying soft-reset to the
	201	* controller to let external ULPI phy come out of reset.
	202	* This delay needs to be added before re-initializing
	203	* the controller after soft-resetting completes
	204	*/
	205	mdelay(5);
	206	}
6b92487d	207
6b92487d	208	/* Set to Host mode */
08066152	209	setbits_le32(&ehci->usbmode, CM_HOST);
6b92487d	210
08066152 VM	211	out_be32(&ehci->snoop1, SNOOP_SIZE_2GB);
08066152 VM	212	out_be32(&ehci->snoop2, 0x80000000 \| SNOOP_SIZE_2GB);
6b92487d MT	213
6b92487d MT	214	/* Init phy */
ba699a5f RB	215	#ifdef CONFIG_DM_USB
	216	if (priv->phy_type)
	217	phy_type = priv->phy_type;
	218	#else
	219	memset(current_usb_controller, '\0', 5);
	220	snprintf(current_usb_controller, sizeof(current_usb_controller),
	221	"usb%d", index+1);
	222
0ecb15c8 NB	223	if (hwconfig_sub(current_usb_controller, "phy_type"))
	224	phy_type = hwconfig_subarg(current_usb_controller,
	225	"phy_type", &len);
ba699a5f	226	#endif
4ef01010	227	else
00caae6d	228	phy_type = env_get("usb_phy_type");
1b719e66 RM	229
	230	if (!phy_type) {
	231	#ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
	232	/* if none specified assume internal UTMI */
	233	strcpy(usb_phy, "utmi");
	234	phy_type = usb_phy;
	235	#else
	236	printf("WARNING: USB phy type not defined !!\n");
	237	return -1;
	238	#endif
	239	}
	240
91d7746d	241	if (!strncmp(phy_type, "utmi", 4)) {
1b719e66	242	#if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
15231f6d NB	243	clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
	244	PHY_CLK_SEL_UTMI);
	245	clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
	246	UTMI_PHY_EN);
1b719e66 RM	247	udelay(1000); /* delay required for PHY Clk to appear */
1b719e66 RM	248	#endif
1e61ce9f	249	out_le32(&(hcor)->or_portsc[0], PORT_PTS_UTMI);
15231f6d NB	250	clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
15231f6d NB	251	USB_EN);
1b719e66	252	} else {
15231f6d NB	253	clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
	254	PHY_CLK_SEL_ULPI);
	255	clrsetbits_be32(&ehci->control, UTMI_PHY_EN \|
	256	CONTROL_REGISTER_W1C_MASK, USB_EN);
1b719e66	257	udelay(1000); /* delay required for PHY Clk to appear */
047cea36 SL	258	if (!usb_phy_clk_valid(ehci))
047cea36 SL	259	return -EINVAL;
1e61ce9f	260	out_le32(&(hcor)->or_portsc[0], PORT_PTS_ULPI);
1b719e66	261	}
6b92487d	262
08066152 VM	263	out_be32(&ehci->prictrl, 0x0000000c);
	264	out_be32(&ehci->age_cnt_limit, 0x00000040);
	265	out_be32(&ehci->sictrl, 0x00000001);
6b92487d	266
08066152	267	in_le32(&ehci->usbmode);
6b92487d	268
f3dff695	269	if (has_erratum_a007798())
896720ce NB	270	set_txfifothresh(ehci, TXFIFOTHRESH);
896720ce NB	271
0dc78ff8 NB	272	if (has_erratum_a004477()) {
	273	/*
	274	* When reset is issued while any ULPI transaction is ongoing
	275	* then it may result to corruption of ULPI Function Control
	276	* Register which eventually causes phy clock to enter low
	277	* power mode which stops the clock. Thus delay is required
	278	* before reset to let ongoing ULPI transaction complete.
	279	*/
	280	udelay(1);
	281	}
6b92487d MT	282	return 0;
	283	}
	284
896720ce NB	285	/*
	286	* Setting the value of TXFIFO_THRESH field in TXFILLTUNING register
	287	* to counter DDR latencies in writing data into Tx buffer.
	288	* This prevents Tx buffer from getting underrun
	289	*/
	290	static void set_txfifothresh(struct usb_ehci *ehci, u32 txfifo_thresh)
	291	{
	292	u32 cmd;
	293	cmd = ehci_readl(&ehci->txfilltuning);
	294	cmd &= ~TXFIFO_THRESH_MASK;
	295	cmd \|= TXFIFO_THRESH(txfifo_thresh);
	296	ehci_writel(&ehci->txfilltuning, cmd);
	297	}