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Commit | Line | Data |
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aaf098cf MT |
1 | /*- |
2 | * Copyright (c) 2007-2008, Juniper Networks, Inc. | |
db63299b | 3 | * Copyright (c) 2008, Excito Elektronik i Skåne AB |
c0d722fe RB |
4 | * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it> |
5 | * | |
aaf098cf MT |
6 | * All rights reserved. |
7 | * | |
e62b5266 | 8 | * SPDX-License-Identifier: GPL-2.0 |
aaf098cf | 9 | */ |
aaf098cf | 10 | #include <common.h> |
46b01797 | 11 | #include <dm.h> |
8f62ca64 | 12 | #include <errno.h> |
db63299b | 13 | #include <asm/byteorder.h> |
93ad908c | 14 | #include <asm/unaligned.h> |
aaf098cf MT |
15 | #include <usb.h> |
16 | #include <asm/io.h> | |
db63299b | 17 | #include <malloc.h> |
cf92e05c | 18 | #include <memalign.h> |
67333f76 | 19 | #include <watchdog.h> |
8f62ca64 | 20 | #include <linux/compiler.h> |
2731b9a8 JCPV |
21 | |
22 | #include "ehci.h" | |
aaf098cf | 23 | |
676ae068 LS |
24 | #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT |
25 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 | |
26 | #endif | |
aaf098cf | 27 | |
5077f96f JW |
28 | /* |
29 | * EHCI spec page 20 says that the HC may take up to 16 uFrames (= 4ms) to halt. | |
30 | * Let's time out after 8 to have a little safety margin on top of that. | |
31 | */ | |
32 | #define HCHALT_TIMEOUT (8 * 1000) | |
33 | ||
46b01797 | 34 | #ifndef CONFIG_DM_USB |
b959655f | 35 | static struct ehci_ctrl ehcic[CONFIG_USB_MAX_CONTROLLER_COUNT]; |
46b01797 | 36 | #endif |
71c5de4f TR |
37 | |
38 | #define ALIGN_END_ADDR(type, ptr, size) \ | |
98ae840a | 39 | ((unsigned long)(ptr) + roundup((size) * sizeof(type), USB_DMA_MINALIGN)) |
aaf098cf | 40 | |
db63299b | 41 | static struct descriptor { |
42 | struct usb_hub_descriptor hub; | |
43 | struct usb_device_descriptor device; | |
44 | struct usb_linux_config_descriptor config; | |
45 | struct usb_linux_interface_descriptor interface; | |
46 | struct usb_endpoint_descriptor endpoint; | |
47 | } __attribute__ ((packed)) descriptor = { | |
48 | { | |
49 | 0x8, /* bDescLength */ | |
50 | 0x29, /* bDescriptorType: hub descriptor */ | |
51 | 2, /* bNrPorts -- runtime modified */ | |
52 | 0, /* wHubCharacteristics */ | |
5f4b4f2f | 53 | 10, /* bPwrOn2PwrGood */ |
db63299b | 54 | 0, /* bHubCntrCurrent */ |
337fc7e6 BM |
55 | { /* Device removable */ |
56 | } /* at most 7 ports! XXX */ | |
db63299b | 57 | }, |
58 | { | |
59 | 0x12, /* bLength */ | |
60 | 1, /* bDescriptorType: UDESC_DEVICE */ | |
6d313c84 | 61 | cpu_to_le16(0x0200), /* bcdUSB: v2.0 */ |
db63299b | 62 | 9, /* bDeviceClass: UDCLASS_HUB */ |
63 | 0, /* bDeviceSubClass: UDSUBCLASS_HUB */ | |
64 | 1, /* bDeviceProtocol: UDPROTO_HSHUBSTT */ | |
65 | 64, /* bMaxPacketSize: 64 bytes */ | |
66 | 0x0000, /* idVendor */ | |
67 | 0x0000, /* idProduct */ | |
6d313c84 | 68 | cpu_to_le16(0x0100), /* bcdDevice */ |
db63299b | 69 | 1, /* iManufacturer */ |
70 | 2, /* iProduct */ | |
71 | 0, /* iSerialNumber */ | |
72 | 1 /* bNumConfigurations: 1 */ | |
73 | }, | |
74 | { | |
75 | 0x9, | |
76 | 2, /* bDescriptorType: UDESC_CONFIG */ | |
77 | cpu_to_le16(0x19), | |
78 | 1, /* bNumInterface */ | |
79 | 1, /* bConfigurationValue */ | |
80 | 0, /* iConfiguration */ | |
81 | 0x40, /* bmAttributes: UC_SELF_POWER */ | |
82 | 0 /* bMaxPower */ | |
83 | }, | |
84 | { | |
85 | 0x9, /* bLength */ | |
86 | 4, /* bDescriptorType: UDESC_INTERFACE */ | |
87 | 0, /* bInterfaceNumber */ | |
88 | 0, /* bAlternateSetting */ | |
89 | 1, /* bNumEndpoints */ | |
90 | 9, /* bInterfaceClass: UICLASS_HUB */ | |
91 | 0, /* bInterfaceSubClass: UISUBCLASS_HUB */ | |
92 | 0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */ | |
93 | 0 /* iInterface */ | |
94 | }, | |
95 | { | |
96 | 0x7, /* bLength */ | |
97 | 5, /* bDescriptorType: UDESC_ENDPOINT */ | |
98 | 0x81, /* bEndpointAddress: | |
99 | * UE_DIR_IN | EHCI_INTR_ENDPT | |
100 | */ | |
101 | 3, /* bmAttributes: UE_INTERRUPT */ | |
8f8bd565 | 102 | 8, /* wMaxPacketSize */ |
db63299b | 103 | 255 /* bInterval */ |
104 | }, | |
aaf098cf MT |
105 | }; |
106 | ||
c0d722fe RB |
107 | #if defined(CONFIG_EHCI_IS_TDI) |
108 | #define ehci_is_TDI() (1) | |
109 | #else | |
110 | #define ehci_is_TDI() (0) | |
111 | #endif | |
112 | ||
24ed894f SG |
113 | static struct ehci_ctrl *ehci_get_ctrl(struct usb_device *udev) |
114 | { | |
46b01797 | 115 | #ifdef CONFIG_DM_USB |
25c8ebdf | 116 | return dev_get_priv(usb_get_bus(udev->dev)); |
46b01797 | 117 | #else |
24ed894f | 118 | return udev->controller; |
46b01797 | 119 | #endif |
24ed894f SG |
120 | } |
121 | ||
deb8508c | 122 | static int ehci_get_port_speed(struct ehci_ctrl *ctrl, uint32_t reg) |
b068deb3 JL |
123 | { |
124 | return PORTSC_PSPD(reg); | |
125 | } | |
126 | ||
deb8508c | 127 | static void ehci_set_usbmode(struct ehci_ctrl *ctrl) |
b068deb3 JL |
128 | { |
129 | uint32_t tmp; | |
130 | uint32_t *reg_ptr; | |
131 | ||
11d18a19 | 132 | reg_ptr = (uint32_t *)((u8 *)&ctrl->hcor->or_usbcmd + USBMODE); |
b068deb3 JL |
133 | tmp = ehci_readl(reg_ptr); |
134 | tmp |= USBMODE_CM_HC; | |
135 | #if defined(CONFIG_EHCI_MMIO_BIG_ENDIAN) | |
136 | tmp |= USBMODE_BE; | |
7ab0d355 MV |
137 | #else |
138 | tmp &= ~USBMODE_BE; | |
b068deb3 JL |
139 | #endif |
140 | ehci_writel(reg_ptr, tmp); | |
141 | } | |
142 | ||
deb8508c | 143 | static void ehci_powerup_fixup(struct ehci_ctrl *ctrl, uint32_t *status_reg, |
727fce36 | 144 | uint32_t *reg) |
3874b6d6 MV |
145 | { |
146 | mdelay(50); | |
147 | } | |
148 | ||
deb8508c | 149 | static uint32_t *ehci_get_portsc_register(struct ehci_ctrl *ctrl, int port) |
aac064f7 | 150 | { |
99c22556 BM |
151 | int max_ports = HCS_N_PORTS(ehci_readl(&ctrl->hccr->cr_hcsparams)); |
152 | ||
153 | if (port < 0 || port >= max_ports) { | |
aac064f7 | 154 | /* Printing the message would cause a scan failure! */ |
99c22556 BM |
155 | debug("The request port(%u) exceeds maximum port number\n", |
156 | port); | |
aac064f7 SG |
157 | return NULL; |
158 | } | |
159 | ||
6a1a8162 | 160 | return (uint32_t *)&ctrl->hcor->or_portsc[port]; |
aac064f7 SG |
161 | } |
162 | ||
1ed9f9ad | 163 | static int handshake(uint32_t *ptr, uint32_t mask, uint32_t done, int usec) |
db63299b | 164 | { |
51ab142b | 165 | uint32_t result; |
166 | do { | |
167 | result = ehci_readl(ptr); | |
09c83a45 | 168 | udelay(5); |
51ab142b | 169 | if (result == ~(uint32_t)0) |
170 | return -1; | |
171 | result &= mask; | |
172 | if (result == done) | |
173 | return 0; | |
1ed9f9ad MT |
174 | usec--; |
175 | } while (usec > 0); | |
51ab142b | 176 | return -1; |
177 | } | |
178 | ||
aeca43e3 | 179 | static int ehci_reset(struct ehci_ctrl *ctrl) |
51ab142b | 180 | { |
181 | uint32_t cmd; | |
51ab142b | 182 | int ret = 0; |
183 | ||
aeca43e3 | 184 | cmd = ehci_readl(&ctrl->hcor->or_usbcmd); |
273d7204 | 185 | cmd = (cmd & ~CMD_RUN) | CMD_RESET; |
aeca43e3 SG |
186 | ehci_writel(&ctrl->hcor->or_usbcmd, cmd); |
187 | ret = handshake((uint32_t *)&ctrl->hcor->or_usbcmd, | |
676ae068 | 188 | CMD_RESET, 0, 250 * 1000); |
51ab142b | 189 | if (ret < 0) { |
190 | printf("EHCI fail to reset\n"); | |
191 | goto out; | |
192 | } | |
193 | ||
b068deb3 | 194 | if (ehci_is_TDI()) |
aeca43e3 | 195 | ctrl->ops.set_usb_mode(ctrl); |
9ab4ce22 SG |
196 | |
197 | #ifdef CONFIG_USB_EHCI_TXFIFO_THRESH | |
aeca43e3 | 198 | cmd = ehci_readl(&ctrl->hcor->or_txfilltuning); |
14eb79b7 | 199 | cmd &= ~TXFIFO_THRESH_MASK; |
9ab4ce22 | 200 | cmd |= TXFIFO_THRESH(CONFIG_USB_EHCI_TXFIFO_THRESH); |
aeca43e3 | 201 | ehci_writel(&ctrl->hcor->or_txfilltuning, cmd); |
9ab4ce22 | 202 | #endif |
51ab142b | 203 | out: |
204 | return ret; | |
db63299b | 205 | } |
aaf098cf | 206 | |
5077f96f JW |
207 | static int ehci_shutdown(struct ehci_ctrl *ctrl) |
208 | { | |
209 | int i, ret = 0; | |
210 | uint32_t cmd, reg; | |
99c22556 | 211 | int max_ports = HCS_N_PORTS(ehci_readl(&ctrl->hccr->cr_hcsparams)); |
5077f96f | 212 | |
1e1be6d4 MV |
213 | if (!ctrl || !ctrl->hcor) |
214 | return -EINVAL; | |
215 | ||
5077f96f | 216 | cmd = ehci_readl(&ctrl->hcor->or_usbcmd); |
1e6fb0e3 PF |
217 | /* If not run, directly return */ |
218 | if (!(cmd & CMD_RUN)) | |
219 | return 0; | |
5077f96f JW |
220 | cmd &= ~(CMD_PSE | CMD_ASE); |
221 | ehci_writel(&ctrl->hcor->or_usbcmd, cmd); | |
222 | ret = handshake(&ctrl->hcor->or_usbsts, STS_ASS | STS_PSS, 0, | |
223 | 100 * 1000); | |
224 | ||
225 | if (!ret) { | |
99c22556 | 226 | for (i = 0; i < max_ports; i++) { |
5077f96f JW |
227 | reg = ehci_readl(&ctrl->hcor->or_portsc[i]); |
228 | reg |= EHCI_PS_SUSP; | |
229 | ehci_writel(&ctrl->hcor->or_portsc[i], reg); | |
230 | } | |
231 | ||
232 | cmd &= ~CMD_RUN; | |
233 | ehci_writel(&ctrl->hcor->or_usbcmd, cmd); | |
234 | ret = handshake(&ctrl->hcor->or_usbsts, STS_HALT, STS_HALT, | |
235 | HCHALT_TIMEOUT); | |
236 | } | |
237 | ||
238 | if (ret) | |
239 | puts("EHCI failed to shut down host controller.\n"); | |
240 | ||
241 | return ret; | |
242 | } | |
243 | ||
aaf098cf MT |
244 | static int ehci_td_buffer(struct qTD *td, void *buf, size_t sz) |
245 | { | |
b8adb120 | 246 | uint32_t delta, next; |
abd702f4 | 247 | unsigned long addr = (unsigned long)buf; |
aaf098cf MT |
248 | int idx; |
249 | ||
189a6956 | 250 | if (addr != ALIGN(addr, ARCH_DMA_MINALIGN)) |
b8adb120 MV |
251 | debug("EHCI-HCD: Misaligned buffer address (%p)\n", buf); |
252 | ||
189a6956 IY |
253 | flush_dcache_range(addr, ALIGN(addr + sz, ARCH_DMA_MINALIGN)); |
254 | ||
aaf098cf | 255 | idx = 0; |
cdeb9161 | 256 | while (idx < QT_BUFFER_CNT) { |
cf7c93cd | 257 | td->qt_buffer[idx] = cpu_to_hc32(virt_to_phys((void *)addr)); |
3ed16071 | 258 | td->qt_buffer_hi[idx] = 0; |
14eb79b7 | 259 | next = (addr + EHCI_PAGE_SIZE) & ~(EHCI_PAGE_SIZE - 1); |
aaf098cf MT |
260 | delta = next - addr; |
261 | if (delta >= sz) | |
262 | break; | |
263 | sz -= delta; | |
264 | addr = next; | |
265 | idx++; | |
266 | } | |
267 | ||
cdeb9161 | 268 | if (idx == QT_BUFFER_CNT) { |
98ae840a | 269 | printf("out of buffer pointers (%zu bytes left)\n", sz); |
aaf098cf MT |
270 | return -1; |
271 | } | |
272 | ||
273 | return 0; | |
274 | } | |
275 | ||
c60795f4 IY |
276 | static inline u8 ehci_encode_speed(enum usb_device_speed speed) |
277 | { | |
278 | #define QH_HIGH_SPEED 2 | |
279 | #define QH_FULL_SPEED 0 | |
280 | #define QH_LOW_SPEED 1 | |
281 | if (speed == USB_SPEED_HIGH) | |
282 | return QH_HIGH_SPEED; | |
283 | if (speed == USB_SPEED_LOW) | |
284 | return QH_LOW_SPEED; | |
285 | return QH_FULL_SPEED; | |
286 | } | |
287 | ||
46b01797 | 288 | static void ehci_update_endpt2_dev_n_port(struct usb_device *udev, |
4e2c4ad3 HG |
289 | struct QH *qh) |
290 | { | |
faa7db24 SB |
291 | uint8_t portnr = 0; |
292 | uint8_t hubaddr = 0; | |
4e2c4ad3 | 293 | |
46b01797 | 294 | if (udev->speed != USB_SPEED_LOW && udev->speed != USB_SPEED_FULL) |
4e2c4ad3 HG |
295 | return; |
296 | ||
faa7db24 | 297 | usb_find_usb2_hub_address_port(udev, &hubaddr, &portnr); |
4e2c4ad3 | 298 | |
faa7db24 SB |
299 | qh->qh_endpt2 |= cpu_to_hc32(QH_ENDPT2_PORTNUM(portnr) | |
300 | QH_ENDPT2_HUBADDR(hubaddr)); | |
4e2c4ad3 HG |
301 | } |
302 | ||
aaf098cf MT |
303 | static int |
304 | ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, | |
305 | int length, struct devrequest *req) | |
306 | { | |
71c5de4f | 307 | ALLOC_ALIGN_BUFFER(struct QH, qh, 1, USB_DMA_MINALIGN); |
5cec214e BT |
308 | struct qTD *qtd; |
309 | int qtd_count = 0; | |
de98e8b2 | 310 | int qtd_counter = 0; |
aaf098cf MT |
311 | volatile struct qTD *vtd; |
312 | unsigned long ts; | |
313 | uint32_t *tdp; | |
db191346 | 314 | uint32_t endpt, maxpacket, token, usbsts; |
aaf098cf | 315 | uint32_t c, toggle; |
db63299b | 316 | uint32_t cmd; |
96820a35 | 317 | int timeout; |
1ed9f9ad | 318 | int ret = 0; |
24ed894f | 319 | struct ehci_ctrl *ctrl = ehci_get_ctrl(dev); |
aaf098cf | 320 | |
db63299b | 321 | debug("dev=%p, pipe=%lx, buffer=%p, length=%d, req=%p\n", dev, pipe, |
aaf098cf MT |
322 | buffer, length, req); |
323 | if (req != NULL) | |
db63299b | 324 | debug("req=%u (%#x), type=%u (%#x), value=%u (%#x), index=%u\n", |
aaf098cf MT |
325 | req->request, req->request, |
326 | req->requesttype, req->requesttype, | |
327 | le16_to_cpu(req->value), le16_to_cpu(req->value), | |
db63299b | 328 | le16_to_cpu(req->index)); |
aaf098cf | 329 | |
db191346 | 330 | #define PKT_ALIGN 512 |
5cec214e BT |
331 | /* |
332 | * The USB transfer is split into qTD transfers. Eeach qTD transfer is | |
333 | * described by a transfer descriptor (the qTD). The qTDs form a linked | |
334 | * list with a queue head (QH). | |
335 | * | |
336 | * Each qTD transfer starts with a new USB packet, i.e. a packet cannot | |
337 | * have its beginning in a qTD transfer and its end in the following | |
338 | * one, so the qTD transfer lengths have to be chosen accordingly. | |
339 | * | |
340 | * Each qTD transfer uses up to QT_BUFFER_CNT data buffers, mapped to | |
341 | * single pages. The first data buffer can start at any offset within a | |
342 | * page (not considering the cache-line alignment issues), while the | |
343 | * following buffers must be page-aligned. There is no alignment | |
344 | * constraint on the size of a qTD transfer. | |
345 | */ | |
346 | if (req != NULL) | |
347 | /* 1 qTD will be needed for SETUP, and 1 for ACK. */ | |
348 | qtd_count += 1 + 1; | |
349 | if (length > 0 || req == NULL) { | |
350 | /* | |
351 | * Determine the qTD transfer size that will be used for the | |
db191346 BT |
352 | * data payload (not considering the first qTD transfer, which |
353 | * may be longer or shorter, and the final one, which may be | |
354 | * shorter). | |
5cec214e BT |
355 | * |
356 | * In order to keep each packet within a qTD transfer, the qTD | |
db191346 BT |
357 | * transfer size is aligned to PKT_ALIGN, which is a multiple of |
358 | * wMaxPacketSize (except in some cases for interrupt transfers, | |
359 | * see comment in submit_int_msg()). | |
5cec214e | 360 | * |
db191346 | 361 | * By default, i.e. if the input buffer is aligned to PKT_ALIGN, |
5cec214e BT |
362 | * QT_BUFFER_CNT full pages will be used. |
363 | */ | |
364 | int xfr_sz = QT_BUFFER_CNT; | |
365 | /* | |
db191346 BT |
366 | * However, if the input buffer is not aligned to PKT_ALIGN, the |
367 | * qTD transfer size will be one page shorter, and the first qTD | |
5cec214e BT |
368 | * data buffer of each transfer will be page-unaligned. |
369 | */ | |
98ae840a | 370 | if ((unsigned long)buffer & (PKT_ALIGN - 1)) |
5cec214e BT |
371 | xfr_sz--; |
372 | /* Convert the qTD transfer size to bytes. */ | |
373 | xfr_sz *= EHCI_PAGE_SIZE; | |
374 | /* | |
db191346 BT |
375 | * Approximate by excess the number of qTDs that will be |
376 | * required for the data payload. The exact formula is way more | |
377 | * complicated and saves at most 2 qTDs, i.e. a total of 128 | |
378 | * bytes. | |
5cec214e | 379 | */ |
db191346 | 380 | qtd_count += 2 + length / xfr_sz; |
5cec214e BT |
381 | } |
382 | /* | |
db191346 BT |
383 | * Threshold value based on the worst-case total size of the allocated qTDs for |
384 | * a mass-storage transfer of 65535 blocks of 512 bytes. | |
5cec214e | 385 | */ |
db191346 | 386 | #if CONFIG_SYS_MALLOC_LEN <= 64 + 128 * 1024 |
5cec214e BT |
387 | #warning CONFIG_SYS_MALLOC_LEN may be too small for EHCI |
388 | #endif | |
389 | qtd = memalign(USB_DMA_MINALIGN, qtd_count * sizeof(struct qTD)); | |
390 | if (qtd == NULL) { | |
391 | printf("unable to allocate TDs\n"); | |
392 | return -1; | |
393 | } | |
394 | ||
71c5de4f | 395 | memset(qh, 0, sizeof(struct QH)); |
5cec214e | 396 | memset(qtd, 0, qtd_count * sizeof(*qtd)); |
de98e8b2 | 397 | |
b8adb120 MV |
398 | toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe)); |
399 | ||
41b1f0ac MV |
400 | /* |
401 | * Setup QH (3.6 in ehci-r10.pdf) | |
402 | * | |
403 | * qh_link ................. 03-00 H | |
404 | * qh_endpt1 ............... 07-04 H | |
405 | * qh_endpt2 ............... 0B-08 H | |
406 | * - qh_curtd | |
407 | * qh_overlay.qt_next ...... 13-10 H | |
408 | * - qh_overlay.qt_altnext | |
409 | */ | |
cf7c93cd | 410 | qh->qh_link = cpu_to_hc32(virt_to_phys(&ctrl->qh_list) | QH_LINK_TYPE_QH); |
c60795f4 | 411 | c = (dev->speed != USB_SPEED_HIGH) && !usb_pipeendpoint(pipe); |
db191346 | 412 | maxpacket = usb_maxpacket(dev, pipe); |
14eb79b7 | 413 | endpt = QH_ENDPT1_RL(8) | QH_ENDPT1_C(c) | |
db191346 | 414 | QH_ENDPT1_MAXPKTLEN(maxpacket) | QH_ENDPT1_H(0) | |
14eb79b7 | 415 | QH_ENDPT1_DTC(QH_ENDPT1_DTC_DT_FROM_QTD) | |
c60795f4 | 416 | QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)) | |
14eb79b7 BT |
417 | QH_ENDPT1_ENDPT(usb_pipeendpoint(pipe)) | QH_ENDPT1_I(0) | |
418 | QH_ENDPT1_DEVADDR(usb_pipedevice(pipe)); | |
71c5de4f | 419 | qh->qh_endpt1 = cpu_to_hc32(endpt); |
4e2c4ad3 | 420 | endpt = QH_ENDPT2_MULT(1) | QH_ENDPT2_UFCMASK(0) | QH_ENDPT2_UFSMASK(0); |
71c5de4f | 421 | qh->qh_endpt2 = cpu_to_hc32(endpt); |
4e2c4ad3 | 422 | ehci_update_endpt2_dev_n_port(dev, qh); |
71c5de4f | 423 | qh->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); |
2456b97f | 424 | qh->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); |
aaf098cf | 425 | |
71c5de4f | 426 | tdp = &qh->qh_overlay.qt_next; |
aaf098cf | 427 | if (req != NULL) { |
41b1f0ac MV |
428 | /* |
429 | * Setup request qTD (3.5 in ehci-r10.pdf) | |
430 | * | |
431 | * qt_next ................ 03-00 H | |
432 | * qt_altnext ............. 07-04 H | |
433 | * qt_token ............... 0B-08 H | |
434 | * | |
435 | * [ buffer, buffer_hi ] loaded with "req". | |
436 | */ | |
de98e8b2 MV |
437 | qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); |
438 | qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); | |
14eb79b7 BT |
439 | token = QT_TOKEN_DT(0) | QT_TOKEN_TOTALBYTES(sizeof(*req)) | |
440 | QT_TOKEN_IOC(0) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) | | |
441 | QT_TOKEN_PID(QT_TOKEN_PID_SETUP) | | |
442 | QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE); | |
de98e8b2 | 443 | qtd[qtd_counter].qt_token = cpu_to_hc32(token); |
14eb79b7 BT |
444 | if (ehci_td_buffer(&qtd[qtd_counter], req, sizeof(*req))) { |
445 | printf("unable to construct SETUP TD\n"); | |
aaf098cf MT |
446 | goto fail; |
447 | } | |
41b1f0ac | 448 | /* Update previous qTD! */ |
cf7c93cd | 449 | *tdp = cpu_to_hc32(virt_to_phys(&qtd[qtd_counter])); |
de98e8b2 | 450 | tdp = &qtd[qtd_counter++].qt_next; |
aaf098cf MT |
451 | toggle = 1; |
452 | } | |
453 | ||
454 | if (length > 0 || req == NULL) { | |
5cec214e BT |
455 | uint8_t *buf_ptr = buffer; |
456 | int left_length = length; | |
457 | ||
458 | do { | |
459 | /* | |
460 | * Determine the size of this qTD transfer. By default, | |
461 | * QT_BUFFER_CNT full pages can be used. | |
462 | */ | |
463 | int xfr_bytes = QT_BUFFER_CNT * EHCI_PAGE_SIZE; | |
464 | /* | |
465 | * However, if the input buffer is not page-aligned, the | |
466 | * portion of the first page before the buffer start | |
467 | * offset within that page is unusable. | |
468 | */ | |
98ae840a | 469 | xfr_bytes -= (unsigned long)buf_ptr & (EHCI_PAGE_SIZE - 1); |
5cec214e BT |
470 | /* |
471 | * In order to keep each packet within a qTD transfer, | |
db191346 | 472 | * align the qTD transfer size to PKT_ALIGN. |
5cec214e | 473 | */ |
db191346 | 474 | xfr_bytes &= ~(PKT_ALIGN - 1); |
5cec214e BT |
475 | /* |
476 | * This transfer may be shorter than the available qTD | |
477 | * transfer size that has just been computed. | |
478 | */ | |
479 | xfr_bytes = min(xfr_bytes, left_length); | |
480 | ||
481 | /* | |
482 | * Setup request qTD (3.5 in ehci-r10.pdf) | |
483 | * | |
484 | * qt_next ................ 03-00 H | |
485 | * qt_altnext ............. 07-04 H | |
486 | * qt_token ............... 0B-08 H | |
487 | * | |
488 | * [ buffer, buffer_hi ] loaded with "buffer". | |
489 | */ | |
490 | qtd[qtd_counter].qt_next = | |
491 | cpu_to_hc32(QT_NEXT_TERMINATE); | |
492 | qtd[qtd_counter].qt_altnext = | |
493 | cpu_to_hc32(QT_NEXT_TERMINATE); | |
494 | token = QT_TOKEN_DT(toggle) | | |
495 | QT_TOKEN_TOTALBYTES(xfr_bytes) | | |
496 | QT_TOKEN_IOC(req == NULL) | QT_TOKEN_CPAGE(0) | | |
497 | QT_TOKEN_CERR(3) | | |
498 | QT_TOKEN_PID(usb_pipein(pipe) ? | |
499 | QT_TOKEN_PID_IN : QT_TOKEN_PID_OUT) | | |
500 | QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE); | |
501 | qtd[qtd_counter].qt_token = cpu_to_hc32(token); | |
502 | if (ehci_td_buffer(&qtd[qtd_counter], buf_ptr, | |
503 | xfr_bytes)) { | |
504 | printf("unable to construct DATA TD\n"); | |
505 | goto fail; | |
506 | } | |
507 | /* Update previous qTD! */ | |
cf7c93cd | 508 | *tdp = cpu_to_hc32(virt_to_phys(&qtd[qtd_counter])); |
5cec214e | 509 | tdp = &qtd[qtd_counter++].qt_next; |
db191346 BT |
510 | /* |
511 | * Data toggle has to be adjusted since the qTD transfer | |
512 | * size is not always an even multiple of | |
513 | * wMaxPacketSize. | |
514 | */ | |
515 | if ((xfr_bytes / maxpacket) & 1) | |
516 | toggle ^= 1; | |
5cec214e BT |
517 | buf_ptr += xfr_bytes; |
518 | left_length -= xfr_bytes; | |
519 | } while (left_length > 0); | |
aaf098cf MT |
520 | } |
521 | ||
522 | if (req != NULL) { | |
41b1f0ac MV |
523 | /* |
524 | * Setup request qTD (3.5 in ehci-r10.pdf) | |
525 | * | |
526 | * qt_next ................ 03-00 H | |
527 | * qt_altnext ............. 07-04 H | |
528 | * qt_token ............... 0B-08 H | |
529 | */ | |
de98e8b2 MV |
530 | qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); |
531 | qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); | |
db191346 | 532 | token = QT_TOKEN_DT(1) | QT_TOKEN_TOTALBYTES(0) | |
14eb79b7 BT |
533 | QT_TOKEN_IOC(1) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) | |
534 | QT_TOKEN_PID(usb_pipein(pipe) ? | |
535 | QT_TOKEN_PID_OUT : QT_TOKEN_PID_IN) | | |
536 | QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE); | |
de98e8b2 | 537 | qtd[qtd_counter].qt_token = cpu_to_hc32(token); |
41b1f0ac | 538 | /* Update previous qTD! */ |
cf7c93cd | 539 | *tdp = cpu_to_hc32(virt_to_phys(&qtd[qtd_counter])); |
de98e8b2 | 540 | tdp = &qtd[qtd_counter++].qt_next; |
aaf098cf MT |
541 | } |
542 | ||
cf7c93cd | 543 | ctrl->qh_list.qh_link = cpu_to_hc32(virt_to_phys(qh) | QH_LINK_TYPE_QH); |
aaf098cf | 544 | |
daa2dafb | 545 | /* Flush dcache */ |
98ae840a | 546 | flush_dcache_range((unsigned long)&ctrl->qh_list, |
676ae068 | 547 | ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1)); |
98ae840a RH |
548 | flush_dcache_range((unsigned long)qh, ALIGN_END_ADDR(struct QH, qh, 1)); |
549 | flush_dcache_range((unsigned long)qtd, | |
5cec214e | 550 | ALIGN_END_ADDR(struct qTD, qtd, qtd_count)); |
daa2dafb | 551 | |
c7701af5 | 552 | /* Set async. queue head pointer. */ |
cf7c93cd | 553 | ehci_writel(&ctrl->hcor->or_asynclistaddr, virt_to_phys(&ctrl->qh_list)); |
c7701af5 | 554 | |
676ae068 LS |
555 | usbsts = ehci_readl(&ctrl->hcor->or_usbsts); |
556 | ehci_writel(&ctrl->hcor->or_usbsts, (usbsts & 0x3f)); | |
aaf098cf MT |
557 | |
558 | /* Enable async. schedule. */ | |
676ae068 | 559 | cmd = ehci_readl(&ctrl->hcor->or_usbcmd); |
51ab142b | 560 | cmd |= CMD_ASE; |
676ae068 | 561 | ehci_writel(&ctrl->hcor->or_usbcmd, cmd); |
51ab142b | 562 | |
676ae068 | 563 | ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, STS_ASS, |
1ed9f9ad MT |
564 | 100 * 1000); |
565 | if (ret < 0) { | |
14eb79b7 | 566 | printf("EHCI fail timeout STS_ASS set\n"); |
1ed9f9ad | 567 | goto fail; |
51ab142b | 568 | } |
aaf098cf MT |
569 | |
570 | /* Wait for TDs to be processed. */ | |
571 | ts = get_timer(0); | |
de98e8b2 | 572 | vtd = &qtd[qtd_counter - 1]; |
96820a35 | 573 | timeout = USB_TIMEOUT_MS(pipe); |
aaf098cf | 574 | do { |
daa2dafb | 575 | /* Invalidate dcache */ |
98ae840a | 576 | invalidate_dcache_range((unsigned long)&ctrl->qh_list, |
676ae068 | 577 | ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1)); |
98ae840a | 578 | invalidate_dcache_range((unsigned long)qh, |
71c5de4f | 579 | ALIGN_END_ADDR(struct QH, qh, 1)); |
98ae840a | 580 | invalidate_dcache_range((unsigned long)qtd, |
5cec214e | 581 | ALIGN_END_ADDR(struct qTD, qtd, qtd_count)); |
b8adb120 | 582 | |
db63299b | 583 | token = hc32_to_cpu(vtd->qt_token); |
14eb79b7 | 584 | if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)) |
aaf098cf | 585 | break; |
67333f76 | 586 | WATCHDOG_RESET(); |
96820a35 SG |
587 | } while (get_timer(ts) < timeout); |
588 | ||
189a6956 IY |
589 | /* |
590 | * Invalidate the memory area occupied by buffer | |
591 | * Don't try to fix the buffer alignment, if it isn't properly | |
592 | * aligned it's upper layer's fault so let invalidate_dcache_range() | |
593 | * vow about it. But we have to fix the length as it's actual | |
594 | * transfer length and can be unaligned. This is potentially | |
595 | * dangerous operation, it's responsibility of the calling | |
596 | * code to make sure enough space is reserved. | |
597 | */ | |
98ae840a RH |
598 | invalidate_dcache_range((unsigned long)buffer, |
599 | ALIGN((unsigned long)buffer + length, ARCH_DMA_MINALIGN)); | |
b8adb120 | 600 | |
96820a35 | 601 | /* Check that the TD processing happened */ |
14eb79b7 | 602 | if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE) |
96820a35 | 603 | printf("EHCI timed out on TD - token=%#x\n", token); |
aaf098cf MT |
604 | |
605 | /* Disable async schedule. */ | |
676ae068 | 606 | cmd = ehci_readl(&ctrl->hcor->or_usbcmd); |
db63299b | 607 | cmd &= ~CMD_ASE; |
676ae068 | 608 | ehci_writel(&ctrl->hcor->or_usbcmd, cmd); |
51ab142b | 609 | |
676ae068 | 610 | ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, 0, |
1ed9f9ad MT |
611 | 100 * 1000); |
612 | if (ret < 0) { | |
14eb79b7 | 613 | printf("EHCI fail timeout STS_ASS reset\n"); |
1ed9f9ad | 614 | goto fail; |
51ab142b | 615 | } |
aaf098cf | 616 | |
71c5de4f | 617 | token = hc32_to_cpu(qh->qh_overlay.qt_token); |
14eb79b7 | 618 | if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)) { |
db63299b | 619 | debug("TOKEN=%#x\n", token); |
14eb79b7 BT |
620 | switch (QT_TOKEN_GET_STATUS(token) & |
621 | ~(QT_TOKEN_STATUS_SPLITXSTATE | QT_TOKEN_STATUS_PERR)) { | |
aaf098cf | 622 | case 0: |
14eb79b7 | 623 | toggle = QT_TOKEN_GET_DT(token); |
aaf098cf MT |
624 | usb_settoggle(dev, usb_pipeendpoint(pipe), |
625 | usb_pipeout(pipe), toggle); | |
626 | dev->status = 0; | |
627 | break; | |
14eb79b7 | 628 | case QT_TOKEN_STATUS_HALTED: |
aaf098cf MT |
629 | dev->status = USB_ST_STALLED; |
630 | break; | |
14eb79b7 BT |
631 | case QT_TOKEN_STATUS_ACTIVE | QT_TOKEN_STATUS_DATBUFERR: |
632 | case QT_TOKEN_STATUS_DATBUFERR: | |
aaf098cf MT |
633 | dev->status = USB_ST_BUF_ERR; |
634 | break; | |
14eb79b7 BT |
635 | case QT_TOKEN_STATUS_HALTED | QT_TOKEN_STATUS_BABBLEDET: |
636 | case QT_TOKEN_STATUS_BABBLEDET: | |
aaf098cf MT |
637 | dev->status = USB_ST_BABBLE_DET; |
638 | break; | |
639 | default: | |
640 | dev->status = USB_ST_CRC_ERR; | |
14eb79b7 | 641 | if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_HALTED) |
222d6dff | 642 | dev->status |= USB_ST_STALLED; |
aaf098cf MT |
643 | break; |
644 | } | |
14eb79b7 | 645 | dev->act_len = length - QT_TOKEN_GET_TOTALBYTES(token); |
aaf098cf MT |
646 | } else { |
647 | dev->act_len = 0; | |
e82a316d | 648 | #ifndef CONFIG_USB_EHCI_FARADAY |
db63299b | 649 | debug("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\n", |
676ae068 LS |
650 | dev->devnum, ehci_readl(&ctrl->hcor->or_usbsts), |
651 | ehci_readl(&ctrl->hcor->or_portsc[0]), | |
652 | ehci_readl(&ctrl->hcor->or_portsc[1])); | |
e82a316d | 653 | #endif |
aaf098cf MT |
654 | } |
655 | ||
5cec214e | 656 | free(qtd); |
aaf098cf MT |
657 | return (dev->status != USB_ST_NOT_PROC) ? 0 : -1; |
658 | ||
659 | fail: | |
5cec214e | 660 | free(qtd); |
aaf098cf MT |
661 | return -1; |
662 | } | |
663 | ||
24ed894f SG |
664 | static int ehci_submit_root(struct usb_device *dev, unsigned long pipe, |
665 | void *buffer, int length, struct devrequest *req) | |
aaf098cf MT |
666 | { |
667 | uint8_t tmpbuf[4]; | |
668 | u16 typeReq; | |
db63299b | 669 | void *srcptr = NULL; |
aaf098cf MT |
670 | int len, srclen; |
671 | uint32_t reg; | |
c0d722fe | 672 | uint32_t *status_reg; |
7d9aa8fd | 673 | int port = le16_to_cpu(req->index) & 0xff; |
24ed894f | 674 | struct ehci_ctrl *ctrl = ehci_get_ctrl(dev); |
aaf098cf MT |
675 | |
676 | srclen = 0; | |
aaf098cf | 677 | |
db63299b | 678 | debug("req=%u (%#x), type=%u (%#x), value=%u, index=%u\n", |
aaf098cf MT |
679 | req->request, req->request, |
680 | req->requesttype, req->requesttype, | |
681 | le16_to_cpu(req->value), le16_to_cpu(req->index)); | |
682 | ||
44259bb9 | 683 | typeReq = req->request | req->requesttype << 8; |
aaf098cf | 684 | |
9c6a9d7c KJS |
685 | switch (typeReq) { |
686 | case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8): | |
687 | case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8): | |
688 | case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8): | |
deb8508c | 689 | status_reg = ctrl->ops.get_portsc_register(ctrl, port - 1); |
1dde1423 | 690 | if (!status_reg) |
9c6a9d7c | 691 | return -1; |
9c6a9d7c KJS |
692 | break; |
693 | default: | |
694 | status_reg = NULL; | |
695 | break; | |
696 | } | |
697 | ||
44259bb9 | 698 | switch (typeReq) { |
aaf098cf MT |
699 | case DeviceRequest | USB_REQ_GET_DESCRIPTOR: |
700 | switch (le16_to_cpu(req->value) >> 8) { | |
701 | case USB_DT_DEVICE: | |
db63299b | 702 | debug("USB_DT_DEVICE request\n"); |
703 | srcptr = &descriptor.device; | |
14eb79b7 | 704 | srclen = descriptor.device.bLength; |
aaf098cf MT |
705 | break; |
706 | case USB_DT_CONFIG: | |
db63299b | 707 | debug("USB_DT_CONFIG config\n"); |
708 | srcptr = &descriptor.config; | |
14eb79b7 BT |
709 | srclen = descriptor.config.bLength + |
710 | descriptor.interface.bLength + | |
711 | descriptor.endpoint.bLength; | |
aaf098cf MT |
712 | break; |
713 | case USB_DT_STRING: | |
db63299b | 714 | debug("USB_DT_STRING config\n"); |
aaf098cf MT |
715 | switch (le16_to_cpu(req->value) & 0xff) { |
716 | case 0: /* Language */ | |
717 | srcptr = "\4\3\1\0"; | |
718 | srclen = 4; | |
719 | break; | |
720 | case 1: /* Vendor */ | |
721 | srcptr = "\16\3u\0-\0b\0o\0o\0t\0"; | |
722 | srclen = 14; | |
723 | break; | |
724 | case 2: /* Product */ | |
725 | srcptr = "\52\3E\0H\0C\0I\0 " | |
726 | "\0H\0o\0s\0t\0 " | |
727 | "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0"; | |
728 | srclen = 42; | |
729 | break; | |
730 | default: | |
db63299b | 731 | debug("unknown value DT_STRING %x\n", |
732 | le16_to_cpu(req->value)); | |
aaf098cf MT |
733 | goto unknown; |
734 | } | |
735 | break; | |
736 | default: | |
db63299b | 737 | debug("unknown value %x\n", le16_to_cpu(req->value)); |
aaf098cf MT |
738 | goto unknown; |
739 | } | |
740 | break; | |
741 | case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8): | |
742 | switch (le16_to_cpu(req->value) >> 8) { | |
743 | case USB_DT_HUB: | |
db63299b | 744 | debug("USB_DT_HUB config\n"); |
745 | srcptr = &descriptor.hub; | |
14eb79b7 | 746 | srclen = descriptor.hub.bLength; |
aaf098cf MT |
747 | break; |
748 | default: | |
db63299b | 749 | debug("unknown value %x\n", le16_to_cpu(req->value)); |
aaf098cf MT |
750 | goto unknown; |
751 | } | |
752 | break; | |
753 | case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8): | |
db63299b | 754 | debug("USB_REQ_SET_ADDRESS\n"); |
676ae068 | 755 | ctrl->rootdev = le16_to_cpu(req->value); |
aaf098cf MT |
756 | break; |
757 | case DeviceOutRequest | USB_REQ_SET_CONFIGURATION: | |
db63299b | 758 | debug("USB_REQ_SET_CONFIGURATION\n"); |
aaf098cf MT |
759 | /* Nothing to do */ |
760 | break; | |
761 | case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8): | |
762 | tmpbuf[0] = 1; /* USB_STATUS_SELFPOWERED */ | |
763 | tmpbuf[1] = 0; | |
764 | srcptr = tmpbuf; | |
765 | srclen = 2; | |
766 | break; | |
db63299b | 767 | case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8): |
aaf098cf | 768 | memset(tmpbuf, 0, 4); |
c0d722fe | 769 | reg = ehci_readl(status_reg); |
aaf098cf MT |
770 | if (reg & EHCI_PS_CS) |
771 | tmpbuf[0] |= USB_PORT_STAT_CONNECTION; | |
772 | if (reg & EHCI_PS_PE) | |
773 | tmpbuf[0] |= USB_PORT_STAT_ENABLE; | |
774 | if (reg & EHCI_PS_SUSP) | |
775 | tmpbuf[0] |= USB_PORT_STAT_SUSPEND; | |
776 | if (reg & EHCI_PS_OCA) | |
777 | tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT; | |
c8b2d1dc SS |
778 | if (reg & EHCI_PS_PR) |
779 | tmpbuf[0] |= USB_PORT_STAT_RESET; | |
aaf098cf MT |
780 | if (reg & EHCI_PS_PP) |
781 | tmpbuf[1] |= USB_PORT_STAT_POWER >> 8; | |
597eb28b SR |
782 | |
783 | if (ehci_is_TDI()) { | |
deb8508c | 784 | switch (ctrl->ops.get_port_speed(ctrl, reg)) { |
14eb79b7 | 785 | case PORTSC_PSPD_FS: |
597eb28b | 786 | break; |
14eb79b7 | 787 | case PORTSC_PSPD_LS: |
597eb28b SR |
788 | tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8; |
789 | break; | |
14eb79b7 | 790 | case PORTSC_PSPD_HS: |
597eb28b SR |
791 | default: |
792 | tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8; | |
793 | break; | |
794 | } | |
795 | } else { | |
796 | tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8; | |
797 | } | |
aaf098cf MT |
798 | |
799 | if (reg & EHCI_PS_CSC) | |
800 | tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION; | |
801 | if (reg & EHCI_PS_PEC) | |
802 | tmpbuf[2] |= USB_PORT_STAT_C_ENABLE; | |
803 | if (reg & EHCI_PS_OCC) | |
804 | tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT; | |
7d9aa8fd | 805 | if (ctrl->portreset & (1 << port)) |
aaf098cf | 806 | tmpbuf[2] |= USB_PORT_STAT_C_RESET; |
c0d722fe | 807 | |
aaf098cf MT |
808 | srcptr = tmpbuf; |
809 | srclen = 4; | |
810 | break; | |
db63299b | 811 | case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8): |
c0d722fe | 812 | reg = ehci_readl(status_reg); |
aaf098cf MT |
813 | reg &= ~EHCI_PS_CLEAR; |
814 | switch (le16_to_cpu(req->value)) { | |
51ab142b | 815 | case USB_PORT_FEAT_ENABLE: |
816 | reg |= EHCI_PS_PE; | |
c0d722fe | 817 | ehci_writel(status_reg, reg); |
51ab142b | 818 | break; |
aaf098cf | 819 | case USB_PORT_FEAT_POWER: |
676ae068 | 820 | if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams))) { |
c0d722fe RB |
821 | reg |= EHCI_PS_PP; |
822 | ehci_writel(status_reg, reg); | |
823 | } | |
aaf098cf MT |
824 | break; |
825 | case USB_PORT_FEAT_RESET: | |
c0d722fe RB |
826 | if ((reg & (EHCI_PS_PE | EHCI_PS_CS)) == EHCI_PS_CS && |
827 | !ehci_is_TDI() && | |
828 | EHCI_PS_IS_LOWSPEED(reg)) { | |
aaf098cf | 829 | /* Low speed device, give up ownership. */ |
c0d722fe | 830 | debug("port %d low speed --> companion\n", |
7d9aa8fd | 831 | port - 1); |
aaf098cf | 832 | reg |= EHCI_PS_PO; |
c0d722fe | 833 | ehci_writel(status_reg, reg); |
45b9ea1d | 834 | return -ENXIO; |
c0d722fe | 835 | } else { |
c8b2d1dc SS |
836 | int ret; |
837 | ||
c0d722fe RB |
838 | reg |= EHCI_PS_PR; |
839 | reg &= ~EHCI_PS_PE; | |
840 | ehci_writel(status_reg, reg); | |
841 | /* | |
842 | * caller must wait, then call GetPortStatus | |
843 | * usb 2.0 specification say 50 ms resets on | |
844 | * root | |
845 | */ | |
deb8508c | 846 | ctrl->ops.powerup_fixup(ctrl, status_reg, ®); |
3874b6d6 | 847 | |
b416191a | 848 | ehci_writel(status_reg, reg & ~EHCI_PS_PR); |
c8b2d1dc SS |
849 | /* |
850 | * A host controller must terminate the reset | |
851 | * and stabilize the state of the port within | |
852 | * 2 milliseconds | |
853 | */ | |
854 | ret = handshake(status_reg, EHCI_PS_PR, 0, | |
855 | 2 * 1000); | |
71b94526 HG |
856 | if (!ret) { |
857 | reg = ehci_readl(status_reg); | |
858 | if ((reg & (EHCI_PS_PE | EHCI_PS_CS)) | |
859 | == EHCI_PS_CS && !ehci_is_TDI()) { | |
860 | debug("port %d full speed --> companion\n", port - 1); | |
861 | reg &= ~EHCI_PS_CLEAR; | |
862 | reg |= EHCI_PS_PO; | |
863 | ehci_writel(status_reg, reg); | |
45b9ea1d | 864 | return -ENXIO; |
71b94526 HG |
865 | } else { |
866 | ctrl->portreset |= 1 << port; | |
867 | } | |
868 | } else { | |
c8b2d1dc | 869 | printf("port(%d) reset error\n", |
7d9aa8fd | 870 | port - 1); |
71b94526 | 871 | } |
aaf098cf | 872 | } |
aaf098cf | 873 | break; |
7d9aa8fd | 874 | case USB_PORT_FEAT_TEST: |
5077f96f | 875 | ehci_shutdown(ctrl); |
7d9aa8fd JW |
876 | reg &= ~(0xf << 16); |
877 | reg |= ((le16_to_cpu(req->index) >> 8) & 0xf) << 16; | |
878 | ehci_writel(status_reg, reg); | |
879 | break; | |
aaf098cf | 880 | default: |
db63299b | 881 | debug("unknown feature %x\n", le16_to_cpu(req->value)); |
aaf098cf MT |
882 | goto unknown; |
883 | } | |
c0d722fe | 884 | /* unblock posted writes */ |
676ae068 | 885 | (void) ehci_readl(&ctrl->hcor->or_usbcmd); |
aaf098cf | 886 | break; |
db63299b | 887 | case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8): |
c0d722fe | 888 | reg = ehci_readl(status_reg); |
ed10e66a | 889 | reg &= ~EHCI_PS_CLEAR; |
aaf098cf MT |
890 | switch (le16_to_cpu(req->value)) { |
891 | case USB_PORT_FEAT_ENABLE: | |
892 | reg &= ~EHCI_PS_PE; | |
893 | break; | |
c0d722fe | 894 | case USB_PORT_FEAT_C_ENABLE: |
ed10e66a | 895 | reg |= EHCI_PS_PE; |
c0d722fe RB |
896 | break; |
897 | case USB_PORT_FEAT_POWER: | |
676ae068 | 898 | if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams))) |
ed10e66a SG |
899 | reg &= ~EHCI_PS_PP; |
900 | break; | |
aaf098cf | 901 | case USB_PORT_FEAT_C_CONNECTION: |
ed10e66a | 902 | reg |= EHCI_PS_CSC; |
aaf098cf | 903 | break; |
51ab142b | 904 | case USB_PORT_FEAT_OVER_CURRENT: |
ed10e66a | 905 | reg |= EHCI_PS_OCC; |
51ab142b | 906 | break; |
aaf098cf | 907 | case USB_PORT_FEAT_C_RESET: |
7d9aa8fd | 908 | ctrl->portreset &= ~(1 << port); |
aaf098cf MT |
909 | break; |
910 | default: | |
db63299b | 911 | debug("unknown feature %x\n", le16_to_cpu(req->value)); |
aaf098cf MT |
912 | goto unknown; |
913 | } | |
c0d722fe RB |
914 | ehci_writel(status_reg, reg); |
915 | /* unblock posted write */ | |
676ae068 | 916 | (void) ehci_readl(&ctrl->hcor->or_usbcmd); |
aaf098cf MT |
917 | break; |
918 | default: | |
db63299b | 919 | debug("Unknown request\n"); |
aaf098cf MT |
920 | goto unknown; |
921 | } | |
922 | ||
5b84dd67 | 923 | mdelay(1); |
b4141195 | 924 | len = min3(srclen, (int)le16_to_cpu(req->length), length); |
aaf098cf MT |
925 | if (srcptr != NULL && len > 0) |
926 | memcpy(buffer, srcptr, len); | |
db63299b | 927 | else |
928 | debug("Len is 0\n"); | |
929 | ||
aaf098cf MT |
930 | dev->act_len = len; |
931 | dev->status = 0; | |
932 | return 0; | |
933 | ||
934 | unknown: | |
db63299b | 935 | debug("requesttype=%x, request=%x, value=%x, index=%x, length=%x\n", |
aaf098cf MT |
936 | req->requesttype, req->request, le16_to_cpu(req->value), |
937 | le16_to_cpu(req->index), le16_to_cpu(req->length)); | |
938 | ||
939 | dev->act_len = 0; | |
940 | dev->status = USB_ST_STALLED; | |
941 | return -1; | |
942 | } | |
943 | ||
121a4d13 | 944 | static const struct ehci_ops default_ehci_ops = { |
deb8508c SG |
945 | .set_usb_mode = ehci_set_usbmode, |
946 | .get_port_speed = ehci_get_port_speed, | |
947 | .powerup_fixup = ehci_powerup_fixup, | |
948 | .get_portsc_register = ehci_get_portsc_register, | |
949 | }; | |
950 | ||
951 | static void ehci_setup_ops(struct ehci_ctrl *ctrl, const struct ehci_ops *ops) | |
952 | { | |
953 | if (!ops) { | |
954 | ctrl->ops = default_ehci_ops; | |
955 | } else { | |
956 | ctrl->ops = *ops; | |
957 | if (!ctrl->ops.set_usb_mode) | |
958 | ctrl->ops.set_usb_mode = ehci_set_usbmode; | |
959 | if (!ctrl->ops.get_port_speed) | |
960 | ctrl->ops.get_port_speed = ehci_get_port_speed; | |
961 | if (!ctrl->ops.powerup_fixup) | |
962 | ctrl->ops.powerup_fixup = ehci_powerup_fixup; | |
963 | if (!ctrl->ops.get_portsc_register) | |
964 | ctrl->ops.get_portsc_register = | |
965 | ehci_get_portsc_register; | |
966 | } | |
967 | } | |
968 | ||
46b01797 | 969 | #ifndef CONFIG_DM_USB |
deb8508c | 970 | void ehci_set_controller_priv(int index, void *priv, const struct ehci_ops *ops) |
c4a3141d | 971 | { |
deb8508c SG |
972 | struct ehci_ctrl *ctrl = &ehcic[index]; |
973 | ||
974 | ctrl->priv = priv; | |
975 | ehci_setup_ops(ctrl, ops); | |
c4a3141d SG |
976 | } |
977 | ||
978 | void *ehci_get_controller_priv(int index) | |
979 | { | |
980 | return ehcic[index].priv; | |
981 | } | |
46b01797 | 982 | #endif |
c4a3141d | 983 | |
7372b5bd | 984 | static int ehci_common_init(struct ehci_ctrl *ctrl, uint tweaks) |
aaf098cf | 985 | { |
676ae068 | 986 | struct QH *qh_list; |
8f62ca64 | 987 | struct QH *periodic; |
7372b5bd SG |
988 | uint32_t reg; |
989 | uint32_t cmd; | |
8f62ca64 | 990 | int i; |
51ab142b | 991 | |
2982837e | 992 | /* Set the high address word (aka segment) for 64-bit controller */ |
7372b5bd SG |
993 | if (ehci_readl(&ctrl->hccr->cr_hccparams) & 1) |
994 | ehci_writel(&ctrl->hcor->or_ctrldssegment, 0); | |
832e6141 | 995 | |
7372b5bd | 996 | qh_list = &ctrl->qh_list; |
676ae068 | 997 | |
aaf098cf | 998 | /* Set head of reclaim list */ |
71c5de4f | 999 | memset(qh_list, 0, sizeof(*qh_list)); |
cf7c93cd | 1000 | qh_list->qh_link = cpu_to_hc32(virt_to_phys(qh_list) | QH_LINK_TYPE_QH); |
14eb79b7 BT |
1001 | qh_list->qh_endpt1 = cpu_to_hc32(QH_ENDPT1_H(1) | |
1002 | QH_ENDPT1_EPS(USB_SPEED_HIGH)); | |
71c5de4f TR |
1003 | qh_list->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); |
1004 | qh_list->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); | |
14eb79b7 BT |
1005 | qh_list->qh_overlay.qt_token = |
1006 | cpu_to_hc32(QT_TOKEN_STATUS(QT_TOKEN_STATUS_HALTED)); | |
aaf098cf | 1007 | |
98ae840a | 1008 | flush_dcache_range((unsigned long)qh_list, |
d3e07478 SW |
1009 | ALIGN_END_ADDR(struct QH, qh_list, 1)); |
1010 | ||
8f62ca64 | 1011 | /* Set async. queue head pointer. */ |
cf7c93cd | 1012 | ehci_writel(&ctrl->hcor->or_asynclistaddr, virt_to_phys(qh_list)); |
8f62ca64 PG |
1013 | |
1014 | /* | |
1015 | * Set up periodic list | |
1016 | * Step 1: Parent QH for all periodic transfers. | |
1017 | */ | |
7372b5bd SG |
1018 | ctrl->periodic_schedules = 0; |
1019 | periodic = &ctrl->periodic_queue; | |
8f62ca64 PG |
1020 | memset(periodic, 0, sizeof(*periodic)); |
1021 | periodic->qh_link = cpu_to_hc32(QH_LINK_TERMINATE); | |
1022 | periodic->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); | |
1023 | periodic->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); | |
1024 | ||
98ae840a | 1025 | flush_dcache_range((unsigned long)periodic, |
d3e07478 SW |
1026 | ALIGN_END_ADDR(struct QH, periodic, 1)); |
1027 | ||
8f62ca64 PG |
1028 | /* |
1029 | * Step 2: Setup frame-list: Every microframe, USB tries the same list. | |
1030 | * In particular, device specifications on polling frequency | |
1031 | * are disregarded. Keyboards seem to send NAK/NYet reliably | |
1032 | * when polled with an empty buffer. | |
1033 | * | |
1034 | * Split Transactions will be spread across microframes using | |
1035 | * S-mask and C-mask. | |
1036 | */ | |
7372b5bd SG |
1037 | if (ctrl->periodic_list == NULL) |
1038 | ctrl->periodic_list = memalign(4096, 1024 * 4); | |
8bc36036 | 1039 | |
7372b5bd | 1040 | if (!ctrl->periodic_list) |
8f62ca64 PG |
1041 | return -ENOMEM; |
1042 | for (i = 0; i < 1024; i++) { | |
7372b5bd | 1043 | ctrl->periodic_list[i] = cpu_to_hc32((unsigned long)periodic |
ea427775 | 1044 | | QH_LINK_TYPE_QH); |
8f62ca64 PG |
1045 | } |
1046 | ||
7372b5bd SG |
1047 | flush_dcache_range((unsigned long)ctrl->periodic_list, |
1048 | ALIGN_END_ADDR(uint32_t, ctrl->periodic_list, | |
d3e07478 SW |
1049 | 1024)); |
1050 | ||
8f62ca64 | 1051 | /* Set periodic list base address */ |
7372b5bd SG |
1052 | ehci_writel(&ctrl->hcor->or_periodiclistbase, |
1053 | (unsigned long)ctrl->periodic_list); | |
8f62ca64 | 1054 | |
7372b5bd | 1055 | reg = ehci_readl(&ctrl->hccr->cr_hcsparams); |
51ab142b | 1056 | descriptor.hub.bNbrPorts = HCS_N_PORTS(reg); |
7a46b2c7 | 1057 | debug("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts); |
c0d722fe RB |
1058 | /* Port Indicators */ |
1059 | if (HCS_INDICATOR(reg)) | |
93ad908c LS |
1060 | put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics) |
1061 | | 0x80, &descriptor.hub.wHubCharacteristics); | |
c0d722fe RB |
1062 | /* Port Power Control */ |
1063 | if (HCS_PPC(reg)) | |
93ad908c LS |
1064 | put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics) |
1065 | | 0x01, &descriptor.hub.wHubCharacteristics); | |
aaf098cf | 1066 | |
aaf098cf | 1067 | /* Start the host controller. */ |
7372b5bd | 1068 | cmd = ehci_readl(&ctrl->hcor->or_usbcmd); |
f15c6515 WD |
1069 | /* |
1070 | * Philips, Intel, and maybe others need CMD_RUN before the | |
1071 | * root hub will detect new devices (why?); NEC doesn't | |
1072 | */ | |
51ab142b | 1073 | cmd &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET); |
1074 | cmd |= CMD_RUN; | |
7372b5bd | 1075 | ehci_writel(&ctrl->hcor->or_usbcmd, cmd); |
51ab142b | 1076 | |
7372b5bd SG |
1077 | if (!(tweaks & EHCI_TWEAK_NO_INIT_CF)) { |
1078 | /* take control over the ports */ | |
1079 | cmd = ehci_readl(&ctrl->hcor->or_configflag); | |
1080 | cmd |= FLAG_CF; | |
1081 | ehci_writel(&ctrl->hcor->or_configflag, cmd); | |
1082 | } | |
e82a316d | 1083 | |
c0d722fe | 1084 | /* unblock posted write */ |
7372b5bd | 1085 | cmd = ehci_readl(&ctrl->hcor->or_usbcmd); |
5b84dd67 | 1086 | mdelay(5); |
7372b5bd | 1087 | reg = HC_VERSION(ehci_readl(&ctrl->hccr->cr_capbase)); |
c0d722fe | 1088 | printf("USB EHCI %x.%02x\n", reg >> 8, reg & 0xff); |
aaf098cf | 1089 | |
7372b5bd SG |
1090 | return 0; |
1091 | } | |
1092 | ||
46b01797 | 1093 | #ifndef CONFIG_DM_USB |
7372b5bd SG |
1094 | int usb_lowlevel_stop(int index) |
1095 | { | |
1096 | ehci_shutdown(&ehcic[index]); | |
1097 | return ehci_hcd_stop(index); | |
1098 | } | |
1099 | ||
1100 | int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) | |
1101 | { | |
1102 | struct ehci_ctrl *ctrl = &ehcic[index]; | |
1103 | uint tweaks = 0; | |
1104 | int rc; | |
1105 | ||
deb8508c SG |
1106 | /** |
1107 | * Set ops to default_ehci_ops, ehci_hcd_init should call | |
1108 | * ehci_set_controller_priv to change any of these function pointers. | |
1109 | */ | |
1110 | ctrl->ops = default_ehci_ops; | |
1111 | ||
7372b5bd SG |
1112 | rc = ehci_hcd_init(index, init, &ctrl->hccr, &ctrl->hcor); |
1113 | if (rc) | |
1114 | return rc; | |
1115 | if (init == USB_INIT_DEVICE) | |
1116 | goto done; | |
1117 | ||
1118 | /* EHCI spec section 4.1 */ | |
aeca43e3 | 1119 | if (ehci_reset(ctrl)) |
7372b5bd SG |
1120 | return -1; |
1121 | ||
1122 | #if defined(CONFIG_EHCI_HCD_INIT_AFTER_RESET) | |
1123 | rc = ehci_hcd_init(index, init, &ctrl->hccr, &ctrl->hcor); | |
1124 | if (rc) | |
1125 | return rc; | |
1126 | #endif | |
1127 | #ifdef CONFIG_USB_EHCI_FARADAY | |
1128 | tweaks |= EHCI_TWEAK_NO_INIT_CF; | |
1129 | #endif | |
1130 | rc = ehci_common_init(ctrl, tweaks); | |
1131 | if (rc) | |
1132 | return rc; | |
1133 | ||
1134 | ctrl->rootdev = 0; | |
127efc4f | 1135 | done: |
676ae068 | 1136 | *controller = &ehcic[index]; |
aaf098cf MT |
1137 | return 0; |
1138 | } | |
46b01797 | 1139 | #endif |
aaf098cf | 1140 | |
24ed894f SG |
1141 | static int _ehci_submit_bulk_msg(struct usb_device *dev, unsigned long pipe, |
1142 | void *buffer, int length) | |
aaf098cf MT |
1143 | { |
1144 | ||
1145 | if (usb_pipetype(pipe) != PIPE_BULK) { | |
1146 | debug("non-bulk pipe (type=%lu)", usb_pipetype(pipe)); | |
1147 | return -1; | |
1148 | } | |
1149 | return ehci_submit_async(dev, pipe, buffer, length, NULL); | |
1150 | } | |
1151 | ||
24ed894f SG |
1152 | static int _ehci_submit_control_msg(struct usb_device *dev, unsigned long pipe, |
1153 | void *buffer, int length, | |
1154 | struct devrequest *setup) | |
aaf098cf | 1155 | { |
24ed894f | 1156 | struct ehci_ctrl *ctrl = ehci_get_ctrl(dev); |
aaf098cf MT |
1157 | |
1158 | if (usb_pipetype(pipe) != PIPE_CONTROL) { | |
1159 | debug("non-control pipe (type=%lu)", usb_pipetype(pipe)); | |
1160 | return -1; | |
1161 | } | |
1162 | ||
676ae068 LS |
1163 | if (usb_pipedevice(pipe) == ctrl->rootdev) { |
1164 | if (!ctrl->rootdev) | |
aaf098cf MT |
1165 | dev->speed = USB_SPEED_HIGH; |
1166 | return ehci_submit_root(dev, pipe, buffer, length, setup); | |
1167 | } | |
1168 | return ehci_submit_async(dev, pipe, buffer, length, setup); | |
1169 | } | |
1170 | ||
8f62ca64 | 1171 | struct int_queue { |
8aa26b8e | 1172 | int elementsize; |
7f59d16a | 1173 | unsigned long pipe; |
8f62ca64 PG |
1174 | struct QH *first; |
1175 | struct QH *current; | |
1176 | struct QH *last; | |
1177 | struct qTD *tds; | |
1178 | }; | |
1179 | ||
98ae840a | 1180 | #define NEXT_QH(qh) (struct QH *)((unsigned long)hc32_to_cpu((qh)->qh_link) & ~0x1f) |
8f62ca64 PG |
1181 | |
1182 | static int | |
1183 | enable_periodic(struct ehci_ctrl *ctrl) | |
1184 | { | |
1185 | uint32_t cmd; | |
1186 | struct ehci_hcor *hcor = ctrl->hcor; | |
1187 | int ret; | |
1188 | ||
1189 | cmd = ehci_readl(&hcor->or_usbcmd); | |
1190 | cmd |= CMD_PSE; | |
1191 | ehci_writel(&hcor->or_usbcmd, cmd); | |
1192 | ||
1193 | ret = handshake((uint32_t *)&hcor->or_usbsts, | |
1194 | STS_PSS, STS_PSS, 100 * 1000); | |
1195 | if (ret < 0) { | |
1196 | printf("EHCI failed: timeout when enabling periodic list\n"); | |
1197 | return -ETIMEDOUT; | |
1198 | } | |
1199 | udelay(1000); | |
1200 | return 0; | |
1201 | } | |
1202 | ||
1203 | static int | |
1204 | disable_periodic(struct ehci_ctrl *ctrl) | |
1205 | { | |
1206 | uint32_t cmd; | |
1207 | struct ehci_hcor *hcor = ctrl->hcor; | |
1208 | int ret; | |
1209 | ||
1210 | cmd = ehci_readl(&hcor->or_usbcmd); | |
1211 | cmd &= ~CMD_PSE; | |
1212 | ehci_writel(&hcor->or_usbcmd, cmd); | |
1213 | ||
1214 | ret = handshake((uint32_t *)&hcor->or_usbsts, | |
1215 | STS_PSS, 0, 100 * 1000); | |
1216 | if (ret < 0) { | |
1217 | printf("EHCI failed: timeout when disabling periodic list\n"); | |
1218 | return -ETIMEDOUT; | |
1219 | } | |
1220 | return 0; | |
1221 | } | |
1222 | ||
029fd8ea HG |
1223 | static struct int_queue *_ehci_create_int_queue(struct usb_device *dev, |
1224 | unsigned long pipe, int queuesize, int elementsize, | |
1225 | void *buffer, int interval) | |
8f62ca64 | 1226 | { |
24ed894f | 1227 | struct ehci_ctrl *ctrl = ehci_get_ctrl(dev); |
8f62ca64 | 1228 | struct int_queue *result = NULL; |
7f59d16a | 1229 | uint32_t i, toggle; |
8f62ca64 | 1230 | |
bd818d81 HG |
1231 | /* |
1232 | * Interrupt transfers requiring several transactions are not supported | |
1233 | * because bInterval is ignored. | |
1234 | * | |
1235 | * Also, ehci_submit_async() relies on wMaxPacketSize being a power of 2 | |
1236 | * <= PKT_ALIGN if several qTDs are required, while the USB | |
1237 | * specification does not constrain this for interrupt transfers. That | |
1238 | * means that ehci_submit_async() would support interrupt transfers | |
1239 | * requiring several transactions only as long as the transfer size does | |
1240 | * not require more than a single qTD. | |
1241 | */ | |
1242 | if (elementsize > usb_maxpacket(dev, pipe)) { | |
1243 | printf("%s: xfers requiring several transactions are not supported.\n", | |
1244 | __func__); | |
1245 | return NULL; | |
1246 | } | |
1247 | ||
8f62ca64 PG |
1248 | debug("Enter create_int_queue\n"); |
1249 | if (usb_pipetype(pipe) != PIPE_INTERRUPT) { | |
1250 | debug("non-interrupt pipe (type=%lu)", usb_pipetype(pipe)); | |
1251 | return NULL; | |
1252 | } | |
1253 | ||
1254 | /* limit to 4 full pages worth of data - | |
1255 | * we can safely fit them in a single TD, | |
1256 | * no matter the alignment | |
1257 | */ | |
1258 | if (elementsize >= 16384) { | |
1259 | debug("too large elements for interrupt transfers\n"); | |
1260 | return NULL; | |
1261 | } | |
1262 | ||
1263 | result = malloc(sizeof(*result)); | |
1264 | if (!result) { | |
1265 | debug("ehci intr queue: out of memory\n"); | |
1266 | goto fail1; | |
1267 | } | |
8aa26b8e | 1268 | result->elementsize = elementsize; |
7f59d16a | 1269 | result->pipe = pipe; |
8165e34b SW |
1270 | result->first = memalign(USB_DMA_MINALIGN, |
1271 | sizeof(struct QH) * queuesize); | |
8f62ca64 PG |
1272 | if (!result->first) { |
1273 | debug("ehci intr queue: out of memory\n"); | |
1274 | goto fail2; | |
1275 | } | |
1276 | result->current = result->first; | |
1277 | result->last = result->first + queuesize - 1; | |
8165e34b SW |
1278 | result->tds = memalign(USB_DMA_MINALIGN, |
1279 | sizeof(struct qTD) * queuesize); | |
8f62ca64 PG |
1280 | if (!result->tds) { |
1281 | debug("ehci intr queue: out of memory\n"); | |
1282 | goto fail3; | |
1283 | } | |
1284 | memset(result->first, 0, sizeof(struct QH) * queuesize); | |
1285 | memset(result->tds, 0, sizeof(struct qTD) * queuesize); | |
1286 | ||
7f59d16a HG |
1287 | toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe)); |
1288 | ||
8f62ca64 PG |
1289 | for (i = 0; i < queuesize; i++) { |
1290 | struct QH *qh = result->first + i; | |
1291 | struct qTD *td = result->tds + i; | |
1292 | void **buf = &qh->buffer; | |
1293 | ||
98ae840a | 1294 | qh->qh_link = cpu_to_hc32((unsigned long)(qh+1) | QH_LINK_TYPE_QH); |
8f62ca64 | 1295 | if (i == queuesize - 1) |
ea427775 | 1296 | qh->qh_link = cpu_to_hc32(QH_LINK_TERMINATE); |
8f62ca64 | 1297 | |
98ae840a | 1298 | qh->qh_overlay.qt_next = cpu_to_hc32((unsigned long)td); |
ea427775 AC |
1299 | qh->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); |
1300 | qh->qh_endpt1 = | |
1301 | cpu_to_hc32((0 << 28) | /* No NAK reload (ehci 4.9) */ | |
8f62ca64 PG |
1302 | (usb_maxpacket(dev, pipe) << 16) | /* MPS */ |
1303 | (1 << 14) | | |
1304 | QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)) | | |
1305 | (usb_pipeendpoint(pipe) << 8) | /* Endpoint Number */ | |
ea427775 AC |
1306 | (usb_pipedevice(pipe) << 0)); |
1307 | qh->qh_endpt2 = cpu_to_hc32((1 << 30) | /* 1 Tx per mframe */ | |
1308 | (1 << 0)); /* S-mask: microframe 0 */ | |
8f62ca64 PG |
1309 | if (dev->speed == USB_SPEED_LOW || |
1310 | dev->speed == USB_SPEED_FULL) { | |
4e2c4ad3 HG |
1311 | /* C-mask: microframes 2-4 */ |
1312 | qh->qh_endpt2 |= cpu_to_hc32((0x1c << 8)); | |
8f62ca64 | 1313 | } |
4e2c4ad3 | 1314 | ehci_update_endpt2_dev_n_port(dev, qh); |
8f62ca64 | 1315 | |
ea427775 AC |
1316 | td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); |
1317 | td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); | |
8f62ca64 PG |
1318 | debug("communication direction is '%s'\n", |
1319 | usb_pipein(pipe) ? "in" : "out"); | |
7f59d16a HG |
1320 | td->qt_token = cpu_to_hc32( |
1321 | QT_TOKEN_DT(toggle) | | |
1322 | (elementsize << 16) | | |
8f62ca64 | 1323 | ((usb_pipein(pipe) ? 1 : 0) << 8) | /* IN/OUT token */ |
ea427775 AC |
1324 | 0x80); /* active */ |
1325 | td->qt_buffer[0] = | |
98ae840a | 1326 | cpu_to_hc32((unsigned long)buffer + i * elementsize); |
ea427775 AC |
1327 | td->qt_buffer[1] = |
1328 | cpu_to_hc32((td->qt_buffer[0] + 0x1000) & ~0xfff); | |
1329 | td->qt_buffer[2] = | |
1330 | cpu_to_hc32((td->qt_buffer[0] + 0x2000) & ~0xfff); | |
1331 | td->qt_buffer[3] = | |
1332 | cpu_to_hc32((td->qt_buffer[0] + 0x3000) & ~0xfff); | |
1333 | td->qt_buffer[4] = | |
1334 | cpu_to_hc32((td->qt_buffer[0] + 0x4000) & ~0xfff); | |
8f62ca64 PG |
1335 | |
1336 | *buf = buffer + i * elementsize; | |
7f59d16a | 1337 | toggle ^= 1; |
8f62ca64 PG |
1338 | } |
1339 | ||
98ae840a | 1340 | flush_dcache_range((unsigned long)buffer, |
d3e07478 SW |
1341 | ALIGN_END_ADDR(char, buffer, |
1342 | queuesize * elementsize)); | |
98ae840a | 1343 | flush_dcache_range((unsigned long)result->first, |
d3e07478 SW |
1344 | ALIGN_END_ADDR(struct QH, result->first, |
1345 | queuesize)); | |
98ae840a | 1346 | flush_dcache_range((unsigned long)result->tds, |
d3e07478 SW |
1347 | ALIGN_END_ADDR(struct qTD, result->tds, |
1348 | queuesize)); | |
1349 | ||
32f2eac1 HG |
1350 | if (ctrl->periodic_schedules > 0) { |
1351 | if (disable_periodic(ctrl) < 0) { | |
1352 | debug("FATAL: periodic should never fail, but did"); | |
1353 | goto fail3; | |
1354 | } | |
8f62ca64 PG |
1355 | } |
1356 | ||
1357 | /* hook up to periodic list */ | |
1358 | struct QH *list = &ctrl->periodic_queue; | |
1359 | result->last->qh_link = list->qh_link; | |
98ae840a | 1360 | list->qh_link = cpu_to_hc32((unsigned long)result->first | QH_LINK_TYPE_QH); |
8f62ca64 | 1361 | |
98ae840a | 1362 | flush_dcache_range((unsigned long)result->last, |
d3e07478 | 1363 | ALIGN_END_ADDR(struct QH, result->last, 1)); |
98ae840a | 1364 | flush_dcache_range((unsigned long)list, |
d3e07478 SW |
1365 | ALIGN_END_ADDR(struct QH, list, 1)); |
1366 | ||
8f62ca64 PG |
1367 | if (enable_periodic(ctrl) < 0) { |
1368 | debug("FATAL: periodic should never fail, but did"); | |
1369 | goto fail3; | |
1370 | } | |
36b73109 | 1371 | ctrl->periodic_schedules++; |
8f62ca64 PG |
1372 | |
1373 | debug("Exit create_int_queue\n"); | |
1374 | return result; | |
1375 | fail3: | |
1376 | if (result->tds) | |
1377 | free(result->tds); | |
1378 | fail2: | |
1379 | if (result->first) | |
1380 | free(result->first); | |
1381 | if (result) | |
1382 | free(result); | |
1383 | fail1: | |
1384 | return NULL; | |
1385 | } | |
1386 | ||
029fd8ea HG |
1387 | static void *_ehci_poll_int_queue(struct usb_device *dev, |
1388 | struct int_queue *queue) | |
8f62ca64 PG |
1389 | { |
1390 | struct QH *cur = queue->current; | |
415548d8 | 1391 | struct qTD *cur_td; |
7f59d16a HG |
1392 | uint32_t token, toggle; |
1393 | unsigned long pipe = queue->pipe; | |
8f62ca64 PG |
1394 | |
1395 | /* depleted queue */ | |
1396 | if (cur == NULL) { | |
1397 | debug("Exit poll_int_queue with completed queue\n"); | |
1398 | return NULL; | |
1399 | } | |
1400 | /* still active */ | |
415548d8 | 1401 | cur_td = &queue->tds[queue->current - queue->first]; |
98ae840a | 1402 | invalidate_dcache_range((unsigned long)cur_td, |
415548d8 | 1403 | ALIGN_END_ADDR(struct qTD, cur_td, 1)); |
7f59d16a HG |
1404 | token = hc32_to_cpu(cur_td->qt_token); |
1405 | if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE) { | |
1406 | debug("Exit poll_int_queue with no completed intr transfer. token is %x\n", token); | |
8f62ca64 PG |
1407 | return NULL; |
1408 | } | |
7f59d16a HG |
1409 | |
1410 | toggle = QT_TOKEN_GET_DT(token); | |
1411 | usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), toggle); | |
1412 | ||
8f62ca64 PG |
1413 | if (!(cur->qh_link & QH_LINK_TERMINATE)) |
1414 | queue->current++; | |
1415 | else | |
1416 | queue->current = NULL; | |
8aa26b8e | 1417 | |
98ae840a | 1418 | invalidate_dcache_range((unsigned long)cur->buffer, |
8aa26b8e HG |
1419 | ALIGN_END_ADDR(char, cur->buffer, |
1420 | queue->elementsize)); | |
1421 | ||
415548d8 | 1422 | debug("Exit poll_int_queue with completed intr transfer. token is %x at %p (first at %p)\n", |
7f59d16a | 1423 | token, cur, queue->first); |
8f62ca64 PG |
1424 | return cur->buffer; |
1425 | } | |
1426 | ||
1427 | /* Do not free buffers associated with QHs, they're owned by someone else */ | |
029fd8ea HG |
1428 | static int _ehci_destroy_int_queue(struct usb_device *dev, |
1429 | struct int_queue *queue) | |
8f62ca64 | 1430 | { |
24ed894f | 1431 | struct ehci_ctrl *ctrl = ehci_get_ctrl(dev); |
8f62ca64 PG |
1432 | int result = -1; |
1433 | unsigned long timeout; | |
1434 | ||
1435 | if (disable_periodic(ctrl) < 0) { | |
1436 | debug("FATAL: periodic should never fail, but did"); | |
1437 | goto out; | |
1438 | } | |
36b73109 | 1439 | ctrl->periodic_schedules--; |
8f62ca64 PG |
1440 | |
1441 | struct QH *cur = &ctrl->periodic_queue; | |
1442 | timeout = get_timer(0) + 500; /* abort after 500ms */ | |
ea427775 | 1443 | while (!(cur->qh_link & cpu_to_hc32(QH_LINK_TERMINATE))) { |
8f62ca64 PG |
1444 | debug("considering %p, with qh_link %x\n", cur, cur->qh_link); |
1445 | if (NEXT_QH(cur) == queue->first) { | |
1446 | debug("found candidate. removing from chain\n"); | |
1447 | cur->qh_link = queue->last->qh_link; | |
98ae840a | 1448 | flush_dcache_range((unsigned long)cur, |
ea7b30c5 | 1449 | ALIGN_END_ADDR(struct QH, cur, 1)); |
8f62ca64 PG |
1450 | result = 0; |
1451 | break; | |
1452 | } | |
1453 | cur = NEXT_QH(cur); | |
1454 | if (get_timer(0) > timeout) { | |
1455 | printf("Timeout destroying interrupt endpoint queue\n"); | |
1456 | result = -1; | |
1457 | goto out; | |
1458 | } | |
1459 | } | |
1460 | ||
36b73109 | 1461 | if (ctrl->periodic_schedules > 0) { |
8f62ca64 PG |
1462 | result = enable_periodic(ctrl); |
1463 | if (result < 0) | |
1464 | debug("FATAL: periodic should never fail, but did"); | |
1465 | } | |
1466 | ||
1467 | out: | |
1468 | free(queue->tds); | |
1469 | free(queue->first); | |
1470 | free(queue); | |
1471 | ||
1472 | return result; | |
1473 | } | |
1474 | ||
24ed894f SG |
1475 | static int _ehci_submit_int_msg(struct usb_device *dev, unsigned long pipe, |
1476 | void *buffer, int length, int interval) | |
aaf098cf | 1477 | { |
8f62ca64 PG |
1478 | void *backbuffer; |
1479 | struct int_queue *queue; | |
1480 | unsigned long timeout; | |
1481 | int result = 0, ret; | |
1482 | ||
aaf098cf MT |
1483 | debug("dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d", |
1484 | dev, pipe, buffer, length, interval); | |
44ae0be7 | 1485 | |
029fd8ea | 1486 | queue = _ehci_create_int_queue(dev, pipe, 1, length, buffer, interval); |
bd818d81 HG |
1487 | if (!queue) |
1488 | return -1; | |
8f62ca64 PG |
1489 | |
1490 | timeout = get_timer(0) + USB_TIMEOUT_MS(pipe); | |
029fd8ea | 1491 | while ((backbuffer = _ehci_poll_int_queue(dev, queue)) == NULL) |
8f62ca64 PG |
1492 | if (get_timer(0) > timeout) { |
1493 | printf("Timeout poll on interrupt endpoint\n"); | |
1494 | result = -ETIMEDOUT; | |
1495 | break; | |
1496 | } | |
1497 | ||
1498 | if (backbuffer != buffer) { | |
98ae840a RH |
1499 | debug("got wrong buffer back (%p instead of %p)\n", |
1500 | backbuffer, buffer); | |
8f62ca64 PG |
1501 | return -EINVAL; |
1502 | } | |
1503 | ||
029fd8ea | 1504 | ret = _ehci_destroy_int_queue(dev, queue); |
8f62ca64 PG |
1505 | if (ret < 0) |
1506 | return ret; | |
1507 | ||
1508 | /* everything worked out fine */ | |
1509 | return result; | |
7555d5ec | 1510 | } |
24ed894f | 1511 | |
46b01797 | 1512 | #ifndef CONFIG_DM_USB |
24ed894f SG |
1513 | int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, |
1514 | void *buffer, int length) | |
1515 | { | |
1516 | return _ehci_submit_bulk_msg(dev, pipe, buffer, length); | |
1517 | } | |
1518 | ||
1519 | int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, | |
1520 | int length, struct devrequest *setup) | |
1521 | { | |
1522 | return _ehci_submit_control_msg(dev, pipe, buffer, length, setup); | |
1523 | } | |
1524 | ||
1525 | int submit_int_msg(struct usb_device *dev, unsigned long pipe, | |
1526 | void *buffer, int length, int interval) | |
1527 | { | |
1528 | return _ehci_submit_int_msg(dev, pipe, buffer, length, interval); | |
1529 | } | |
029fd8ea HG |
1530 | |
1531 | struct int_queue *create_int_queue(struct usb_device *dev, | |
1532 | unsigned long pipe, int queuesize, int elementsize, | |
1533 | void *buffer, int interval) | |
1534 | { | |
1535 | return _ehci_create_int_queue(dev, pipe, queuesize, elementsize, | |
1536 | buffer, interval); | |
1537 | } | |
1538 | ||
1539 | void *poll_int_queue(struct usb_device *dev, struct int_queue *queue) | |
1540 | { | |
1541 | return _ehci_poll_int_queue(dev, queue); | |
1542 | } | |
1543 | ||
1544 | int destroy_int_queue(struct usb_device *dev, struct int_queue *queue) | |
1545 | { | |
1546 | return _ehci_destroy_int_queue(dev, queue); | |
1547 | } | |
46b01797 SG |
1548 | #endif |
1549 | ||
1550 | #ifdef CONFIG_DM_USB | |
1551 | static int ehci_submit_control_msg(struct udevice *dev, struct usb_device *udev, | |
1552 | unsigned long pipe, void *buffer, int length, | |
1553 | struct devrequest *setup) | |
1554 | { | |
1555 | debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__, | |
1556 | dev->name, udev, udev->dev->name, udev->portnr); | |
1557 | ||
1558 | return _ehci_submit_control_msg(udev, pipe, buffer, length, setup); | |
1559 | } | |
1560 | ||
1561 | static int ehci_submit_bulk_msg(struct udevice *dev, struct usb_device *udev, | |
1562 | unsigned long pipe, void *buffer, int length) | |
1563 | { | |
1564 | debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev); | |
1565 | return _ehci_submit_bulk_msg(udev, pipe, buffer, length); | |
1566 | } | |
1567 | ||
1568 | static int ehci_submit_int_msg(struct udevice *dev, struct usb_device *udev, | |
1569 | unsigned long pipe, void *buffer, int length, | |
1570 | int interval) | |
1571 | { | |
1572 | debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev); | |
1573 | return _ehci_submit_int_msg(udev, pipe, buffer, length, interval); | |
1574 | } | |
1575 | ||
8a5f0665 HG |
1576 | static struct int_queue *ehci_create_int_queue(struct udevice *dev, |
1577 | struct usb_device *udev, unsigned long pipe, int queuesize, | |
1578 | int elementsize, void *buffer, int interval) | |
1579 | { | |
1580 | debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev); | |
1581 | return _ehci_create_int_queue(udev, pipe, queuesize, elementsize, | |
1582 | buffer, interval); | |
1583 | } | |
1584 | ||
1585 | static void *ehci_poll_int_queue(struct udevice *dev, struct usb_device *udev, | |
1586 | struct int_queue *queue) | |
1587 | { | |
1588 | debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev); | |
1589 | return _ehci_poll_int_queue(udev, queue); | |
1590 | } | |
1591 | ||
1592 | static int ehci_destroy_int_queue(struct udevice *dev, struct usb_device *udev, | |
1593 | struct int_queue *queue) | |
1594 | { | |
1595 | debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev); | |
1596 | return _ehci_destroy_int_queue(udev, queue); | |
1597 | } | |
1598 | ||
46b01797 SG |
1599 | int ehci_register(struct udevice *dev, struct ehci_hccr *hccr, |
1600 | struct ehci_hcor *hcor, const struct ehci_ops *ops, | |
1601 | uint tweaks, enum usb_init_type init) | |
1602 | { | |
cb8a2c14 | 1603 | struct usb_bus_priv *priv = dev_get_uclass_priv(dev); |
46b01797 SG |
1604 | struct ehci_ctrl *ctrl = dev_get_priv(dev); |
1605 | int ret; | |
1606 | ||
1607 | debug("%s: dev='%s', ctrl=%p, hccr=%p, hcor=%p, init=%d\n", __func__, | |
1608 | dev->name, ctrl, hccr, hcor, init); | |
1609 | ||
cb8a2c14 HG |
1610 | priv->desc_before_addr = true; |
1611 | ||
46b01797 SG |
1612 | ehci_setup_ops(ctrl, ops); |
1613 | ctrl->hccr = hccr; | |
1614 | ctrl->hcor = hcor; | |
1615 | ctrl->priv = ctrl; | |
1616 | ||
49b4c5c7 SW |
1617 | ctrl->init = init; |
1618 | if (ctrl->init == USB_INIT_DEVICE) | |
46b01797 | 1619 | goto done; |
49b4c5c7 | 1620 | |
46b01797 SG |
1621 | ret = ehci_reset(ctrl); |
1622 | if (ret) | |
1623 | goto err; | |
1624 | ||
cfb3f1cd MK |
1625 | if (ctrl->ops.init_after_reset) { |
1626 | ret = ctrl->ops.init_after_reset(ctrl); | |
3f9f8a5b MK |
1627 | if (ret) |
1628 | goto err; | |
1629 | } | |
1630 | ||
46b01797 SG |
1631 | ret = ehci_common_init(ctrl, tweaks); |
1632 | if (ret) | |
1633 | goto err; | |
1634 | done: | |
1635 | return 0; | |
1636 | err: | |
1637 | free(ctrl); | |
1638 | debug("%s: failed, ret=%d\n", __func__, ret); | |
1639 | return ret; | |
1640 | } | |
1641 | ||
1642 | int ehci_deregister(struct udevice *dev) | |
1643 | { | |
1644 | struct ehci_ctrl *ctrl = dev_get_priv(dev); | |
1645 | ||
49b4c5c7 SW |
1646 | if (ctrl->init == USB_INIT_DEVICE) |
1647 | return 0; | |
1648 | ||
46b01797 SG |
1649 | ehci_shutdown(ctrl); |
1650 | ||
1651 | return 0; | |
1652 | } | |
1653 | ||
1654 | struct dm_usb_ops ehci_usb_ops = { | |
1655 | .control = ehci_submit_control_msg, | |
1656 | .bulk = ehci_submit_bulk_msg, | |
1657 | .interrupt = ehci_submit_int_msg, | |
8a5f0665 HG |
1658 | .create_int_queue = ehci_create_int_queue, |
1659 | .poll_int_queue = ehci_poll_int_queue, | |
1660 | .destroy_int_queue = ehci_destroy_int_queue, | |
46b01797 SG |
1661 | }; |
1662 | ||
1663 | #endif |