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1d8937a4 PW |
1 | /* |
2 | * (C) Copyright 2009 | |
3 | * Marvell Semiconductor <www.marvell.com> | |
4 | * Written-by: Prafulla Wadaskar <prafulla@marvell.com> | |
5 | * | |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
1d8937a4 PW |
7 | */ |
8 | ||
9 | #include <common.h> | |
10 | #include <asm/io.h> | |
11 | #include <usb.h> | |
12 | #include "ehci.h" | |
fe11ae24 | 13 | #include <linux/mbus.h> |
a7efd719 | 14 | #include <asm/arch/cpu.h> |
cd48225b | 15 | #include <dm.h> |
805ad7ee AA |
16 | |
17 | #if defined(CONFIG_KIRKWOOD) | |
3dc23f78 | 18 | #include <asm/arch/soc.h> |
805ad7ee AA |
19 | #elif defined(CONFIG_ORION5X) |
20 | #include <asm/arch/orion5x.h> | |
21 | #endif | |
1d8937a4 | 22 | |
74d34421 AA |
23 | DECLARE_GLOBAL_DATA_PTR; |
24 | ||
1d8937a4 PW |
25 | #define USB_WINDOW_CTRL(i) (0x320 + ((i) << 4)) |
26 | #define USB_WINDOW_BASE(i) (0x324 + ((i) << 4)) | |
27 | #define USB_TARGET_DRAM 0x0 | |
28 | ||
c6cfcc91 SR |
29 | #define USB2_SBUSCFG_OFF 0x90 |
30 | ||
31 | #define USB_SBUSCFG_BAWR_OFF 0x6 | |
32 | #define USB_SBUSCFG_BARD_OFF 0x3 | |
33 | #define USB_SBUSCFG_AHBBRST_OFF 0x0 | |
34 | ||
35 | #define USB_SBUSCFG_BAWR_ALIGN_64B 0x4 | |
36 | #define USB_SBUSCFG_BARD_ALIGN_64B 0x4 | |
37 | #define USB_SBUSCFG_AHBBRST_INCR16 0x7 | |
38 | ||
1d8937a4 PW |
39 | /* |
40 | * USB 2.0 Bridge Address Decoding registers setup | |
41 | */ | |
cd48225b | 42 | #ifdef CONFIG_DM_USB |
fe11ae24 | 43 | |
cd48225b SR |
44 | struct ehci_mvebu_priv { |
45 | struct ehci_ctrl ehci; | |
46 | fdt_addr_t hcd_base; | |
47 | }; | |
fe11ae24 SR |
48 | |
49 | /* | |
50 | * Once all the older Marvell SoC's (Orion, Kirkwood) are converted | |
51 | * to the common mvebu archticture including the mbus setup, this | |
52 | * will be the only function needed to configure the access windows | |
53 | */ | |
c6cfcc91 | 54 | static void usb_brg_adrdec_setup(void *base) |
fe11ae24 SR |
55 | { |
56 | const struct mbus_dram_target_info *dram; | |
57 | int i; | |
58 | ||
59 | dram = mvebu_mbus_dram_info(); | |
60 | ||
61 | for (i = 0; i < 4; i++) { | |
cd48225b SR |
62 | writel(0, base + USB_WINDOW_CTRL(i)); |
63 | writel(0, base + USB_WINDOW_BASE(i)); | |
fe11ae24 SR |
64 | } |
65 | ||
66 | for (i = 0; i < dram->num_cs; i++) { | |
67 | const struct mbus_dram_window *cs = dram->cs + i; | |
68 | ||
69 | /* Write size, attributes and target id to control register */ | |
82b9143b SR |
70 | writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) | |
71 | (dram->mbus_dram_target_id << 4) | 1, | |
cd48225b | 72 | base + USB_WINDOW_CTRL(i)); |
fe11ae24 SR |
73 | |
74 | /* Write base address to base register */ | |
cd48225b | 75 | writel(cs->base, base + USB_WINDOW_BASE(i)); |
fe11ae24 SR |
76 | } |
77 | } | |
cd48225b | 78 | |
c6cfcc91 SR |
79 | static void marvell_ehci_powerup_fixup(struct ehci_ctrl *ctrl, |
80 | uint32_t *status_reg, uint32_t *reg) | |
81 | { | |
82 | struct ehci_mvebu_priv *priv = ctrl->priv; | |
83 | ||
84 | /* | |
85 | * Set default value for reg SBUSCFG, which is Control for the AMBA | |
86 | * system bus interface: | |
87 | * BAWR = BARD = 4 : Align rd/wr bursts packets larger than 64 bytes | |
88 | * AHBBRST = 7 : Align AHB burst for packets larger than 64 bytes | |
89 | */ | |
90 | writel((USB_SBUSCFG_BAWR_ALIGN_64B << USB_SBUSCFG_BAWR_OFF) | | |
91 | (USB_SBUSCFG_BARD_ALIGN_64B << USB_SBUSCFG_BARD_OFF) | | |
92 | (USB_SBUSCFG_AHBBRST_INCR16 << USB_SBUSCFG_AHBBRST_OFF), | |
93 | priv->hcd_base + USB2_SBUSCFG_OFF); | |
94 | ||
95 | mdelay(50); | |
96 | } | |
97 | ||
98 | static struct ehci_ops marvell_ehci_ops = { | |
99 | .powerup_fixup = NULL, | |
100 | }; | |
101 | ||
cd48225b SR |
102 | static int ehci_mvebu_probe(struct udevice *dev) |
103 | { | |
104 | struct ehci_mvebu_priv *priv = dev_get_priv(dev); | |
105 | struct ehci_hccr *hccr; | |
106 | struct ehci_hcor *hcor; | |
107 | ||
108 | /* | |
109 | * Get the base address for EHCI controller from the device node | |
110 | */ | |
a821c4af | 111 | priv->hcd_base = devfdt_get_addr(dev); |
cd48225b SR |
112 | if (priv->hcd_base == FDT_ADDR_T_NONE) { |
113 | debug("Can't get the EHCI register base address\n"); | |
114 | return -ENXIO; | |
115 | } | |
116 | ||
c6cfcc91 SR |
117 | /* |
118 | * For SoCs without hlock like Armada3700 we need to program the sbuscfg | |
119 | * reg to guarantee AHB master's burst will not overrun or underrun | |
120 | * the FIFO. Otherwise all USB2 write option will fail. | |
121 | * Also, the address decoder doesn't need to get setup with this | |
122 | * SoC, so don't call usb_brg_adrdec_setup(). | |
123 | */ | |
124 | if (of_device_is_compatible(dev, "marvell,armada3700-ehci")) | |
125 | marvell_ehci_ops.powerup_fixup = marvell_ehci_powerup_fixup; | |
126 | else | |
127 | usb_brg_adrdec_setup((void *)priv->hcd_base); | |
cd48225b SR |
128 | |
129 | hccr = (struct ehci_hccr *)(priv->hcd_base + 0x100); | |
130 | hcor = (struct ehci_hcor *) | |
c6cfcc91 | 131 | ((uintptr_t)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); |
cd48225b | 132 | |
c6cfcc91 SR |
133 | debug("ehci-marvell: init hccr %lx and hcor %lx hc_length %ld\n", |
134 | (uintptr_t)hccr, (uintptr_t)hcor, | |
135 | (uintptr_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase))); | |
cd48225b | 136 | |
c6cfcc91 SR |
137 | return ehci_register(dev, hccr, hcor, &marvell_ehci_ops, 0, |
138 | USB_INIT_HOST); | |
cd48225b SR |
139 | } |
140 | ||
cd48225b SR |
141 | static const struct udevice_id ehci_usb_ids[] = { |
142 | { .compatible = "marvell,orion-ehci", }, | |
c6cfcc91 | 143 | { .compatible = "marvell,armada3700-ehci", }, |
cd48225b SR |
144 | { } |
145 | }; | |
146 | ||
147 | U_BOOT_DRIVER(ehci_mvebu) = { | |
148 | .name = "ehci_mvebu", | |
149 | .id = UCLASS_USB, | |
150 | .of_match = ehci_usb_ids, | |
151 | .probe = ehci_mvebu_probe, | |
40527342 | 152 | .remove = ehci_deregister, |
cd48225b SR |
153 | .ops = &ehci_usb_ops, |
154 | .platdata_auto_alloc_size = sizeof(struct usb_platdata), | |
155 | .priv_auto_alloc_size = sizeof(struct ehci_mvebu_priv), | |
156 | .flags = DM_FLAG_ALLOC_PRIV_DMA, | |
157 | }; | |
158 | ||
fe11ae24 | 159 | #else |
8a333716 AS |
160 | #define MVUSB_BASE(port) MVUSB0_BASE |
161 | ||
162 | static void usb_brg_adrdec_setup(int index) | |
1d8937a4 PW |
163 | { |
164 | int i; | |
74d34421 | 165 | u32 size, base, attrib; |
1d8937a4 PW |
166 | |
167 | for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { | |
168 | ||
169 | /* Enable DRAM bank */ | |
170 | switch (i) { | |
171 | case 0: | |
74d34421 | 172 | attrib = MVUSB0_CPU_ATTR_DRAM_CS0; |
1d8937a4 PW |
173 | break; |
174 | case 1: | |
74d34421 | 175 | attrib = MVUSB0_CPU_ATTR_DRAM_CS1; |
1d8937a4 PW |
176 | break; |
177 | case 2: | |
74d34421 | 178 | attrib = MVUSB0_CPU_ATTR_DRAM_CS2; |
1d8937a4 PW |
179 | break; |
180 | case 3: | |
74d34421 | 181 | attrib = MVUSB0_CPU_ATTR_DRAM_CS3; |
1d8937a4 PW |
182 | break; |
183 | default: | |
184 | /* invalide bank, disable access */ | |
185 | attrib = 0; | |
186 | break; | |
187 | } | |
188 | ||
74d34421 AA |
189 | size = gd->bd->bi_dram[i].size; |
190 | base = gd->bd->bi_dram[i].start; | |
1d8937a4 | 191 | if ((size) && (attrib)) |
82b9143b SR |
192 | writel(MVCPU_WIN_CTRL_DATA(size, USB_TARGET_DRAM, |
193 | attrib, MVCPU_WIN_ENABLE), | |
194 | MVUSB0_BASE + USB_WINDOW_CTRL(i)); | |
1d8937a4 | 195 | else |
82b9143b SR |
196 | writel(MVCPU_WIN_DISABLE, |
197 | MVUSB0_BASE + USB_WINDOW_CTRL(i)); | |
1d8937a4 | 198 | |
82b9143b | 199 | writel(base, MVUSB0_BASE + USB_WINDOW_BASE(i)); |
1d8937a4 PW |
200 | } |
201 | } | |
202 | ||
203 | /* | |
204 | * Create the appropriate control structures to manage | |
205 | * a new EHCI host controller. | |
206 | */ | |
127efc4f TK |
207 | int ehci_hcd_init(int index, enum usb_init_type init, |
208 | struct ehci_hccr **hccr, struct ehci_hcor **hcor) | |
1d8937a4 | 209 | { |
8a333716 | 210 | usb_brg_adrdec_setup(index); |
1d8937a4 | 211 | |
8a333716 | 212 | *hccr = (struct ehci_hccr *)(MVUSB_BASE(index) + 0x100); |
676ae068 LS |
213 | *hcor = (struct ehci_hcor *)((uint32_t) *hccr |
214 | + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); | |
1d8937a4 | 215 | |
74d34421 | 216 | debug("ehci-marvell: init hccr %x and hcor %x hc_length %d\n", |
676ae068 LS |
217 | (uint32_t)*hccr, (uint32_t)*hcor, |
218 | (uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); | |
1d8937a4 PW |
219 | |
220 | return 0; | |
221 | } | |
222 | ||
223 | /* | |
224 | * Destroy the appropriate control structures corresponding | |
225 | * the the EHCI host controller. | |
226 | */ | |
676ae068 | 227 | int ehci_hcd_stop(int index) |
1d8937a4 PW |
228 | { |
229 | return 0; | |
230 | } | |
cd48225b SR |
231 | |
232 | #endif /* CONFIG_DM_USB */ |