[people/ms/u-boot.git] / drivers / usb / host / ehci-mx5.c

/*
 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
 * Copyright (C) 2010 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <usb.h>
#include <errno.h>
#include <linux/compiler.h>
#include <usb/ehci-fsl.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>

#include "ehci.h"

#define MX5_USBOTHER_REGS_OFFSET 0x800


#define MXC_OTG_OFFSET			0
#define MXC_H1_OFFSET			0x200
#define MXC_H2_OFFSET			0x400
#define MXC_H3_OFFSET			0x600

#define MXC_USBCTRL_OFFSET		0
#define MXC_USB_PHY_CTR_FUNC_OFFSET	0x8
#define MXC_USB_PHY_CTR_FUNC2_OFFSET	0xc
#define MXC_USB_CTRL_1_OFFSET		0x10
#define MXC_USBH2CTRL_OFFSET		0x14
#define MXC_USBH3CTRL_OFFSET		0x18

/* USB_CTRL */
/* OTG wakeup intr enable */
#define MXC_OTG_UCTRL_OWIE_BIT		(1 << 27)
/* OTG power mask */
#define MXC_OTG_UCTRL_OPM_BIT		(1 << 24)
/* OTG power pin polarity */
#define MXC_OTG_UCTRL_O_PWR_POL_BIT	(1 << 24)
/* Host1 ULPI interrupt enable */
#define MXC_H1_UCTRL_H1UIE_BIT		(1 << 12)
/* HOST1 wakeup intr enable */
#define MXC_H1_UCTRL_H1WIE_BIT		(1 << 11)
/* HOST1 power mask */
#define MXC_H1_UCTRL_H1PM_BIT		(1 << 8)
/* HOST1 power pin polarity */
#define MXC_H1_UCTRL_H1_PWR_POL_BIT	(1 << 8)

/* USB_PHY_CTRL_FUNC */
/* OTG Polarity of Overcurrent */
#define MXC_OTG_PHYCTRL_OC_POL_BIT	(1 << 9)
/* OTG Disable Overcurrent Event */
#define MXC_OTG_PHYCTRL_OC_DIS_BIT	(1 << 8)
/* UH1 Polarity of Overcurrent */
#define MXC_H1_OC_POL_BIT		(1 << 6)
/* UH1 Disable Overcurrent Event */
#define MXC_H1_OC_DIS_BIT		(1 << 5)
/* OTG Power Pin Polarity */
#define MXC_OTG_PHYCTRL_PWR_POL_BIT	(1 << 3)

/* USBH2CTRL */
#define MXC_H2_UCTRL_H2_OC_POL_BIT	(1 << 31)
#define MXC_H2_UCTRL_H2_OC_DIS_BIT	(1 << 30)
#define MXC_H2_UCTRL_H2UIE_BIT		(1 << 8)
#define MXC_H2_UCTRL_H2WIE_BIT		(1 << 7)
#define MXC_H2_UCTRL_H2PM_BIT		(1 << 4)
#define MXC_H2_UCTRL_H2_PWR_POL_BIT	(1 << 4)

/* USBH3CTRL */
#define MXC_H3_UCTRL_H3_OC_POL_BIT	(1 << 31)
#define MXC_H3_UCTRL_H3_OC_DIS_BIT	(1 << 30)
#define MXC_H3_UCTRL_H3UIE_BIT		(1 << 8)
#define MXC_H3_UCTRL_H3WIE_BIT		(1 << 7)
#define MXC_H3_UCTRL_H3_PWR_POL_BIT	(1 << 4)

/* USB_CTRL_1 */
#define MXC_USB_CTRL_UH1_EXT_CLK_EN	(1 << 25)

int mxc_set_usbcontrol(int port, unsigned int flags)
{
	unsigned int v;
	void __iomem *usb_base = (void __iomem *)OTG_BASE_ADDR;
	void __iomem *usbother_base;
	int ret = 0;

	usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;

	switch (port) {
	case 0:	/* OTG port */
		if (flags & MXC_EHCI_INTERNAL_PHY) {
			v = __raw_readl(usbother_base +
					MXC_USB_PHY_CTR_FUNC_OFFSET);
			if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
				v |= MXC_OTG_PHYCTRL_OC_POL_BIT;
			else
				v &= ~MXC_OTG_PHYCTRL_OC_POL_BIT;
			if (flags & MXC_EHCI_POWER_PINS_ENABLED)
				/* OC/USBPWR is used */
				v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
			else
				/* OC/USBPWR is not used */
				v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
#ifdef CONFIG_MX51
			if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
				v |= MXC_OTG_PHYCTRL_PWR_POL_BIT;
			else
				v &= ~MXC_OTG_PHYCTRL_PWR_POL_BIT;
#endif
			__raw_writel(v, usbother_base +
					MXC_USB_PHY_CTR_FUNC_OFFSET);

			v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
#ifdef CONFIG_MX51
			if (flags & MXC_EHCI_POWER_PINS_ENABLED)
				v &= ~MXC_OTG_UCTRL_OPM_BIT;
			else
				v |= MXC_OTG_UCTRL_OPM_BIT;
#endif
#ifdef CONFIG_MX53
			if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
				v |= MXC_OTG_UCTRL_O_PWR_POL_BIT;
			else
				v &= ~MXC_OTG_UCTRL_O_PWR_POL_BIT;
#endif
			__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
		}
		break;
	case 1:	/* Host 1 ULPI */
#ifdef CONFIG_MX51
		/* The clock for the USBH1 ULPI port will come externally
		   from the PHY. */
		v = __raw_readl(usbother_base + MXC_USB_CTRL_1_OFFSET);
		__raw_writel(v | MXC_USB_CTRL_UH1_EXT_CLK_EN, usbother_base +
				MXC_USB_CTRL_1_OFFSET);
#endif

		v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
#ifdef CONFIG_MX51
		if (flags & MXC_EHCI_POWER_PINS_ENABLED)
			v &= ~MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask unused */
		else
			v |= MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask used */
#endif
#ifdef CONFIG_MX53
		if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
			v |= MXC_H1_UCTRL_H1_PWR_POL_BIT;
		else
			v &= ~MXC_H1_UCTRL_H1_PWR_POL_BIT;
#endif
		__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);

		v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
		if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
			v |= MXC_H1_OC_POL_BIT;
		else
			v &= ~MXC_H1_OC_POL_BIT;
		if (flags & MXC_EHCI_POWER_PINS_ENABLED)
			v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */
		else
			v |= MXC_H1_OC_DIS_BIT; /* OC is not used */
		__raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);

		break;
	case 2: /* Host 2 ULPI */
		v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
#ifdef CONFIG_MX51
		if (flags & MXC_EHCI_POWER_PINS_ENABLED)
			v &= ~MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask unused */
		else
			v |= MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask used */
#endif
#ifdef CONFIG_MX53
		if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
			v |= MXC_H2_UCTRL_H2_OC_POL_BIT;
		else
			v &= ~MXC_H2_UCTRL_H2_OC_POL_BIT;
		if (flags & MXC_EHCI_POWER_PINS_ENABLED)
			v &= ~MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is used */
		else
			v |= MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is not used */
		if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
			v |= MXC_H2_UCTRL_H2_PWR_POL_BIT;
		else
			v &= ~MXC_H2_UCTRL_H2_PWR_POL_BIT;
#endif
		__raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
		break;
#ifdef CONFIG_MX53
	case 3: /* Host 3 ULPI */
		v = __raw_readl(usbother_base + MXC_USBH3CTRL_OFFSET);
		if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
			v |= MXC_H3_UCTRL_H3_OC_POL_BIT;
		else
			v &= ~MXC_H3_UCTRL_H3_OC_POL_BIT;
		if (flags & MXC_EHCI_POWER_PINS_ENABLED)
			v &= ~MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is used */
		else
			v |= MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is not used */
		if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
			v |= MXC_H3_UCTRL_H3_PWR_POL_BIT;
		else
			v &= ~MXC_H3_UCTRL_H3_PWR_POL_BIT;
		__raw_writel(v, usbother_base + MXC_USBH3CTRL_OFFSET);
		break;
#endif
	}

	return ret;
}

int __weak board_ehci_hcd_init(int port)
{
	return 0;
}

void __weak board_ehci_hcd_postinit(struct usb_ehci *ehci, int port)
{
}

int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
	struct usb_ehci *ehci;
#ifdef CONFIG_MX53
	struct clkctl *sc_regs = (struct clkctl *)CCM_BASE_ADDR;
	u32 reg;

	reg = __raw_readl(&sc_regs->cscmr1) & ~(1 << 26);
	/* derive USB PHY clock multiplexer from PLL3 */
	reg |= 1 << 26;
	__raw_writel(reg, &sc_regs->cscmr1);
#endif

	set_usboh3_clk();
	enable_usboh3_clk(1);
	set_usb_phy_clk();
	enable_usb_phy1_clk(1);
	enable_usb_phy2_clk(1);
	mdelay(1);

	/* Do board specific initialization */
	board_ehci_hcd_init(CONFIG_MXC_USB_PORT);

	ehci = (struct usb_ehci *)(OTG_BASE_ADDR +
		(0x200 * CONFIG_MXC_USB_PORT));
	*hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
	*hcor = (struct ehci_hcor *)((uint32_t)*hccr +
			HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
	setbits_le32(&ehci->usbmode, CM_HOST);

	__raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
	setbits_le32(&ehci->portsc, USB_EN);

	mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);
	mdelay(10);

	/* Do board specific post-initialization */
	board_ehci_hcd_postinit(ehci, CONFIG_MXC_USB_PORT);

	return 0;
}

int ehci_hcd_stop(int index)
{
	return 0;
}
Commit	Line	Data
1ca56202 WG	1	/*
	2	* Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
	3	* Copyright (C) 2010 Freescale Semiconductor, Inc.
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
1ca56202 WG	6	*/
	7
	8	#include <common.h>
	9	#include <usb.h>
	10	#include <errno.h>
	11	#include <linux/compiler.h>
	12	#include <usb/ehci-fsl.h>
	13	#include <asm/io.h>
	14	#include <asm/arch/imx-regs.h>
	15	#include <asm/arch/clock.h>
1ca56202 WG	16
1ca56202 WG	17	#include "ehci.h"
1ca56202 WG	18
	19	#define MX5_USBOTHER_REGS_OFFSET 0x800
	20
	21
bdc52020 BT	22	#define MXC_OTG_OFFSET 0
	23	#define MXC_H1_OFFSET 0x200
	24	#define MXC_H2_OFFSET 0x400
2cfe0b8f	25	#define MXC_H3_OFFSET 0x600
1ca56202 WG	26
	27	#define MXC_USBCTRL_OFFSET 0
	28	#define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8
	29	#define MXC_USB_PHY_CTR_FUNC2_OFFSET 0xc
	30	#define MXC_USB_CTRL_1_OFFSET 0x10
	31	#define MXC_USBH2CTRL_OFFSET 0x14
2cfe0b8f	32	#define MXC_USBH3CTRL_OFFSET 0x18
1ca56202 WG	33
1ca56202 WG	34	/* USB_CTRL */
bdc52020 BT	35	/* OTG wakeup intr enable */
	36	#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27)
	37	/* OTG power mask */
	38	#define MXC_OTG_UCTRL_OPM_BIT (1 << 24)
31ac2d0c BT	39	/* OTG power pin polarity */
31ac2d0c BT	40	#define MXC_OTG_UCTRL_O_PWR_POL_BIT (1 << 24)
bdc52020 BT	41	/* Host1 ULPI interrupt enable */
	42	#define MXC_H1_UCTRL_H1UIE_BIT (1 << 12)
	43	/* HOST1 wakeup intr enable */
	44	#define MXC_H1_UCTRL_H1WIE_BIT (1 << 11)
	45	/* HOST1 power mask */
	46	#define MXC_H1_UCTRL_H1PM_BIT (1 << 8)
31ac2d0c BT	47	/* HOST1 power pin polarity */
31ac2d0c BT	48	#define MXC_H1_UCTRL_H1_PWR_POL_BIT (1 << 8)
1ca56202 WG	49
1ca56202 WG	50	/* USB_PHY_CTRL_FUNC */
31ac2d0c BT	51	/* OTG Polarity of Overcurrent */
31ac2d0c BT	52	#define MXC_OTG_PHYCTRL_OC_POL_BIT (1 << 9)
bdc52020 BT	53	/* OTG Disable Overcurrent Event */
bdc52020 BT	54	#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8)
31ac2d0c BT	55	/* UH1 Polarity of Overcurrent */
31ac2d0c BT	56	#define MXC_H1_OC_POL_BIT (1 << 6)
bdc52020 BT	57	/* UH1 Disable Overcurrent Event */
bdc52020 BT	58	#define MXC_H1_OC_DIS_BIT (1 << 5)
31ac2d0c BT	59	/* OTG Power Pin Polarity */
31ac2d0c BT	60	#define MXC_OTG_PHYCTRL_PWR_POL_BIT (1 << 3)
1ca56202 WG	61
1ca56202 WG	62	/* USBH2CTRL */
31ac2d0c	63	#define MXC_H2_UCTRL_H2_OC_POL_BIT (1 << 31)
2cfe0b8f	64	#define MXC_H2_UCTRL_H2_OC_DIS_BIT (1 << 30)
bdc52020 BT	65	#define MXC_H2_UCTRL_H2UIE_BIT (1 << 8)
	66	#define MXC_H2_UCTRL_H2WIE_BIT (1 << 7)
	67	#define MXC_H2_UCTRL_H2PM_BIT (1 << 4)
31ac2d0c	68	#define MXC_H2_UCTRL_H2_PWR_POL_BIT (1 << 4)
1ca56202	69
2cfe0b8f	70	/* USBH3CTRL */
31ac2d0c	71	#define MXC_H3_UCTRL_H3_OC_POL_BIT (1 << 31)
2cfe0b8f BT	72	#define MXC_H3_UCTRL_H3_OC_DIS_BIT (1 << 30)
	73	#define MXC_H3_UCTRL_H3UIE_BIT (1 << 8)
	74	#define MXC_H3_UCTRL_H3WIE_BIT (1 << 7)
31ac2d0c	75	#define MXC_H3_UCTRL_H3_PWR_POL_BIT (1 << 4)
2cfe0b8f	76
1ca56202	77	/* USB_CTRL_1 */
bdc52020	78	#define MXC_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
1ca56202 WG	79
	80	int mxc_set_usbcontrol(int port, unsigned int flags)
	81	{
	82	unsigned int v;
	83	void __iomem usb_base = (void __iomem )OTG_BASE_ADDR;
	84	void __iomem *usbother_base;
	85	int ret = 0;
	86
	87	usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
	88
	89	switch (port) {
	90	case 0: /* OTG port */
	91	if (flags & MXC_EHCI_INTERNAL_PHY) {
	92	v = __raw_readl(usbother_base +
	93	MXC_USB_PHY_CTR_FUNC_OFFSET);
31ac2d0c BT	94	if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
	95	v \|= MXC_OTG_PHYCTRL_OC_POL_BIT;
	96	else
	97	v &= ~MXC_OTG_PHYCTRL_OC_POL_BIT;
1ca56202	98	if (flags & MXC_EHCI_POWER_PINS_ENABLED)
1ca56202 WG	99	/* OC/USBPWR is used */
1ca56202 WG	100	v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
7d42432d BT	101	else
	102	/* OC/USBPWR is not used */
	103	v \|= MXC_OTG_PHYCTRL_OC_DIS_BIT;
31ac2d0c BT	104	#ifdef CONFIG_MX51
	105	if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
	106	v \|= MXC_OTG_PHYCTRL_PWR_POL_BIT;
	107	else
	108	v &= ~MXC_OTG_PHYCTRL_PWR_POL_BIT;
	109	#endif
1ca56202 WG	110	__raw_writel(v, usbother_base +
	111	MXC_USB_PHY_CTR_FUNC_OFFSET);
	112
	113	v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
661052f4	114	#ifdef CONFIG_MX51
1ca56202	115	if (flags & MXC_EHCI_POWER_PINS_ENABLED)
1ca56202	116	v &= ~MXC_OTG_UCTRL_OPM_BIT;
394c00dc BT	117	else
394c00dc BT	118	v \|= MXC_OTG_UCTRL_OPM_BIT;
31ac2d0c BT	119	#endif
	120	#ifdef CONFIG_MX53
	121	if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
	122	v \|= MXC_OTG_UCTRL_O_PWR_POL_BIT;
	123	else
	124	v &= ~MXC_OTG_UCTRL_O_PWR_POL_BIT;
661052f4	125	#endif
1ca56202 WG	126	__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
	127	}
	128	break;
bdc52020	129	case 1: /* Host 1 ULPI */
1ca56202 WG	130	#ifdef CONFIG_MX51
	131	/* The clock for the USBH1 ULPI port will come externally
	132	from the PHY. */
	133	v = __raw_readl(usbother_base + MXC_USB_CTRL_1_OFFSET);
	134	__raw_writel(v \| MXC_USB_CTRL_UH1_EXT_CLK_EN, usbother_base +
	135	MXC_USB_CTRL_1_OFFSET);
	136	#endif
	137
	138	v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
661052f4	139	#ifdef CONFIG_MX51
1ca56202	140	if (flags & MXC_EHCI_POWER_PINS_ENABLED)
bdc52020	141	v &= ~MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask unused */
1ca56202	142	else
bdc52020	143	v \|= MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask used */
31ac2d0c BT	144	#endif
	145	#ifdef CONFIG_MX53
	146	if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
	147	v \|= MXC_H1_UCTRL_H1_PWR_POL_BIT;
	148	else
	149	v &= ~MXC_H1_UCTRL_H1_PWR_POL_BIT;
661052f4	150	#endif
1ca56202 WG	151	__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
	152
	153	v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
31ac2d0c BT	154	if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
	155	v \|= MXC_H1_OC_POL_BIT;
	156	else
	157	v &= ~MXC_H1_OC_POL_BIT;
1ca56202 WG	158	if (flags & MXC_EHCI_POWER_PINS_ENABLED)
	159	v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */
	160	else
	161	v \|= MXC_H1_OC_DIS_BIT; /* OC is not used */
	162	__raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
	163
	164	break;
	165	case 2: /* Host 2 ULPI */
	166	v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
661052f4	167	#ifdef CONFIG_MX51
1ca56202	168	if (flags & MXC_EHCI_POWER_PINS_ENABLED)
bdc52020	169	v &= ~MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask unused */
1ca56202	170	else
bdc52020	171	v \|= MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask used */
2cfe0b8f BT	172	#endif
2cfe0b8f BT	173	#ifdef CONFIG_MX53
31ac2d0c BT	174	if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
	175	v \|= MXC_H2_UCTRL_H2_OC_POL_BIT;
	176	else
	177	v &= ~MXC_H2_UCTRL_H2_OC_POL_BIT;
2cfe0b8f BT	178	if (flags & MXC_EHCI_POWER_PINS_ENABLED)
	179	v &= ~MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is used */
	180	else
	181	v \|= MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is not used */
31ac2d0c BT	182	if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
	183	v \|= MXC_H2_UCTRL_H2_PWR_POL_BIT;
	184	else
	185	v &= ~MXC_H2_UCTRL_H2_PWR_POL_BIT;
661052f4	186	#endif
1ca56202 WG	187	__raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
1ca56202 WG	188	break;
2cfe0b8f BT	189	#ifdef CONFIG_MX53
	190	case 3: /* Host 3 ULPI */
	191	v = __raw_readl(usbother_base + MXC_USBH3CTRL_OFFSET);
31ac2d0c BT	192	if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
	193	v \|= MXC_H3_UCTRL_H3_OC_POL_BIT;
	194	else
	195	v &= ~MXC_H3_UCTRL_H3_OC_POL_BIT;
2cfe0b8f BT	196	if (flags & MXC_EHCI_POWER_PINS_ENABLED)
	197	v &= ~MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is used */
	198	else
	199	v \|= MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is not used */
31ac2d0c BT	200	if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
	201	v \|= MXC_H3_UCTRL_H3_PWR_POL_BIT;
	202	else
	203	v &= ~MXC_H3_UCTRL_H3_PWR_POL_BIT;
2cfe0b8f BT	204	__raw_writel(v, usbother_base + MXC_USBH3CTRL_OFFSET);
	205	break;
	206	#endif
1ca56202 WG	207	}
	208
	209	return ret;
	210	}
	211
f22e4fae	212	int __weak board_ehci_hcd_init(int port)
1b80f270	213	{
f22e4fae	214	return 0;
1b80f270 MV	215	}
1b80f270 MV	216
f22e4fae BT	217	void __weak board_ehci_hcd_postinit(struct usb_ehci *ehci, int port)
	218	{
	219	}
1b80f270	220
676ae068	221	int ehci_hcd_init(int index, struct ehci_hccr hccr, struct ehci_hcor hcor)
1ca56202 WG	222	{
	223	struct usb_ehci *ehci;
	224	#ifdef CONFIG_MX53
	225	struct clkctl sc_regs = (struct clkctl )CCM_BASE_ADDR;
	226	u32 reg;
	227
	228	reg = __raw_readl(&sc_regs->cscmr1) & ~(1 << 26);
	229	/* derive USB PHY clock multiplexer from PLL3 */
	230	reg \|= 1 << 26;
	231	__raw_writel(reg, &sc_regs->cscmr1);
	232	#endif
	233
	234	set_usboh3_clk();
	235	enable_usboh3_clk(1);
414e1660 BT	236	set_usb_phy_clk();
414e1660 BT	237	enable_usb_phy1_clk(1);
1ca56202 WG	238	enable_usb_phy2_clk(1);
	239	mdelay(1);
	240
1b80f270	241	/* Do board specific initialization */
1ca56202 WG	242	board_ehci_hcd_init(CONFIG_MXC_USB_PORT);
	243
	244	ehci = (struct usb_ehci *)(OTG_BASE_ADDR +
	245	(0x200 * CONFIG_MXC_USB_PORT));
676ae068 LS	246	hccr = (struct ehci_hccr )((uint32_t)&ehci->caplength);
	247	hcor = (struct ehci_hcor )((uint32_t)*hccr +
	248	HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
1ca56202 WG	249	setbits_le32(&ehci->usbmode, CM_HOST);
	250
	251	__raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
	252	setbits_le32(&ehci->portsc, USB_EN);
	253
	254	mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);
1ca56202 WG	255	mdelay(10);
1ca56202 WG	256
1b80f270 MV	257	/* Do board specific post-initialization */
	258	board_ehci_hcd_postinit(ehci, CONFIG_MXC_USB_PORT);
	259
1ca56202 WG	260	return 0;
	261	}
	262
676ae068	263	int ehci_hcd_stop(int index)
1ca56202 WG	264	{
	265	return 0;
	266	}