]>
Commit | Line | Data |
---|---|---|
aaf098cf MT |
1 | /*- |
2 | * Copyright (c) 2007-2008, Juniper Networks, Inc. | |
c0d722fe | 3 | * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it> |
aaf098cf MT |
4 | * All rights reserved. |
5 | * | |
e62b5266 | 6 | * SPDX-License-Identifier: GPL-2.0 |
aaf098cf MT |
7 | */ |
8 | ||
9 | #ifndef USB_EHCI_H | |
10 | #define USB_EHCI_H | |
11 | ||
b959655f MV |
12 | #include <usb.h> |
13 | ||
99c22556 BM |
14 | /* Section 2.2.3 - N_PORTS */ |
15 | #define MAX_HC_PORTS 15 | |
c0d722fe | 16 | |
aaf098cf MT |
17 | /* |
18 | * Register Space. | |
19 | */ | |
20 | struct ehci_hccr { | |
db63299b | 21 | uint32_t cr_capbase; |
22 | #define HC_LENGTH(p) (((p) >> 0) & 0x00ff) | |
23 | #define HC_VERSION(p) (((p) >> 16) & 0xffff) | |
aaf098cf | 24 | uint32_t cr_hcsparams; |
c0d722fe RB |
25 | #define HCS_PPC(p) ((p) & (1 << 4)) |
26 | #define HCS_INDICATOR(p) ((p) & (1 << 16)) /* Port indicators */ | |
51ab142b | 27 | #define HCS_N_PORTS(p) (((p) >> 0) & 0xf) |
aaf098cf MT |
28 | uint32_t cr_hccparams; |
29 | uint8_t cr_hcsp_portrt[8]; | |
69716c19 | 30 | } __attribute__ ((packed, aligned(4))); |
aaf098cf MT |
31 | |
32 | struct ehci_hcor { | |
33 | uint32_t or_usbcmd; | |
51ab142b | 34 | #define CMD_PARK (1 << 11) /* enable "park" */ |
35 | #define CMD_PARK_CNT(c) (((c) >> 8) & 3) /* how many transfers to park */ | |
51ab142b | 36 | #define CMD_LRESET (1 << 7) /* partial reset */ |
c02bf458 MY |
37 | #define CMD_IAAD (1 << 6) /* "doorbell" interrupt */ |
38 | #define CMD_ASE (1 << 5) /* async schedule enable */ | |
51ab142b | 39 | #define CMD_PSE (1 << 4) /* periodic schedule enable */ |
40 | #define CMD_RESET (1 << 1) /* reset HC not bus */ | |
41 | #define CMD_RUN (1 << 0) /* start/stop HC */ | |
aaf098cf | 42 | uint32_t or_usbsts; |
14eb79b7 | 43 | #define STS_ASS (1 << 15) |
8f62ca64 | 44 | #define STS_PSS (1 << 14) |
51ab142b | 45 | #define STS_HALT (1 << 12) |
aaf098cf | 46 | uint32_t or_usbintr; |
29c6fbe0 DD |
47 | #define INTR_UE (1 << 0) /* USB interrupt enable */ |
48 | #define INTR_UEE (1 << 1) /* USB error interrupt enable */ | |
49 | #define INTR_PCE (1 << 2) /* Port change detect enable */ | |
50 | #define INTR_SEE (1 << 4) /* system error enable */ | |
51 | #define INTR_AAE (1 << 5) /* Interrupt on async adavance enable */ | |
aaf098cf MT |
52 | uint32_t or_frindex; |
53 | uint32_t or_ctrldssegment; | |
54 | uint32_t or_periodiclistbase; | |
55 | uint32_t or_asynclistaddr; | |
9ab4ce22 SG |
56 | uint32_t _reserved_0_; |
57 | uint32_t or_burstsize; | |
58 | uint32_t or_txfilltuning; | |
14eb79b7 | 59 | #define TXFIFO_THRESH_MASK (0x3f << 16) |
9ab4ce22 SG |
60 | #define TXFIFO_THRESH(p) ((p & 0x3f) << 16) |
61 | uint32_t _reserved_1_[6]; | |
aaf098cf | 62 | uint32_t or_configflag; |
51ab142b | 63 | #define FLAG_CF (1 << 0) /* true: we'll support "high speed" */ |
99c22556 | 64 | uint32_t or_portsc[MAX_HC_PORTS]; |
14eb79b7 BT |
65 | #define PORTSC_PSPD(x) (((x) >> 26) & 0x3) |
66 | #define PORTSC_PSPD_FS 0x0 | |
67 | #define PORTSC_PSPD_LS 0x1 | |
68 | #define PORTSC_PSPD_HS 0x2 | |
aaf098cf | 69 | uint32_t or_systune; |
69716c19 | 70 | } __attribute__ ((packed, aligned(4))); |
aaf098cf | 71 | |
51ab142b | 72 | #define USBMODE 0x68 /* USB Device mode */ |
73 | #define USBMODE_SDIS (1 << 3) /* Stream disable */ | |
74 | #define USBMODE_BE (1 << 2) /* BE/LE endiannes select */ | |
75 | #define USBMODE_CM_HC (3 << 0) /* host controller mode */ | |
76 | #define USBMODE_CM_IDLE (0 << 0) /* idle state */ | |
77 | ||
db63299b | 78 | /* Interface descriptor */ |
79 | struct usb_linux_interface_descriptor { | |
80 | unsigned char bLength; | |
81 | unsigned char bDescriptorType; | |
82 | unsigned char bInterfaceNumber; | |
83 | unsigned char bAlternateSetting; | |
84 | unsigned char bNumEndpoints; | |
85 | unsigned char bInterfaceClass; | |
86 | unsigned char bInterfaceSubClass; | |
87 | unsigned char bInterfaceProtocol; | |
88 | unsigned char iInterface; | |
89 | } __attribute__ ((packed)); | |
90 | ||
91 | /* Configuration descriptor information.. */ | |
92 | struct usb_linux_config_descriptor { | |
93 | unsigned char bLength; | |
94 | unsigned char bDescriptorType; | |
95 | unsigned short wTotalLength; | |
96 | unsigned char bNumInterfaces; | |
97 | unsigned char bConfigurationValue; | |
98 | unsigned char iConfiguration; | |
99 | unsigned char bmAttributes; | |
100 | unsigned char MaxPower; | |
101 | } __attribute__ ((packed)); | |
102 | ||
103 | #if defined CONFIG_EHCI_DESC_BIG_ENDIAN | |
9000eddb AB |
104 | #define ehci_readl(x) cpu_to_be32(readl(x)) |
105 | #define ehci_writel(a, b) writel(cpu_to_be32(b), a) | |
db63299b | 106 | #else |
9000eddb AB |
107 | #define ehci_readl(x) cpu_to_le32(readl(x)) |
108 | #define ehci_writel(a, b) writel(cpu_to_le32(b), a) | |
db63299b | 109 | #endif |
110 | ||
111 | #if defined CONFIG_EHCI_MMIO_BIG_ENDIAN | |
112 | #define hc32_to_cpu(x) be32_to_cpu((x)) | |
113 | #define cpu_to_hc32(x) cpu_to_be32((x)) | |
114 | #else | |
115 | #define hc32_to_cpu(x) le32_to_cpu((x)) | |
116 | #define cpu_to_hc32(x) cpu_to_le32((x)) | |
117 | #endif | |
118 | ||
c0d722fe RB |
119 | #define EHCI_PS_WKOC_E (1 << 22) /* RW wake on over current */ |
120 | #define EHCI_PS_WKDSCNNT_E (1 << 21) /* RW wake on disconnect */ | |
121 | #define EHCI_PS_WKCNNT_E (1 << 20) /* RW wake on connect */ | |
122 | #define EHCI_PS_PO (1 << 13) /* RW port owner */ | |
123 | #define EHCI_PS_PP (1 << 12) /* RW,RO port power */ | |
124 | #define EHCI_PS_LS (3 << 10) /* RO line status */ | |
125 | #define EHCI_PS_PR (1 << 8) /* RW port reset */ | |
126 | #define EHCI_PS_SUSP (1 << 7) /* RW suspend */ | |
127 | #define EHCI_PS_FPR (1 << 6) /* RW force port resume */ | |
128 | #define EHCI_PS_OCC (1 << 5) /* RWC over current change */ | |
129 | #define EHCI_PS_OCA (1 << 4) /* RO over current active */ | |
130 | #define EHCI_PS_PEC (1 << 3) /* RWC port enable change */ | |
131 | #define EHCI_PS_PE (1 << 2) /* RW port enable */ | |
132 | #define EHCI_PS_CSC (1 << 1) /* RWC connect status change */ | |
133 | #define EHCI_PS_CS (1 << 0) /* RO connect status */ | |
aaf098cf MT |
134 | #define EHCI_PS_CLEAR (EHCI_PS_OCC | EHCI_PS_PEC | EHCI_PS_CSC) |
135 | ||
c0d722fe | 136 | #define EHCI_PS_IS_LOWSPEED(x) (((x) & EHCI_PS_LS) == (1 << 10)) |
aaf098cf MT |
137 | |
138 | /* | |
139 | * Schedule Interface Space. | |
140 | * | |
141 | * IMPORTANT: Software must ensure that no interface data structure | |
142 | * reachable by the EHCI host controller spans a 4K page boundary! | |
143 | * | |
144 | * Periodic transfers (i.e. isochronous and interrupt transfers) are | |
145 | * not supported. | |
146 | */ | |
147 | ||
148 | /* Queue Element Transfer Descriptor (qTD). */ | |
149 | struct qTD { | |
3ed16071 | 150 | /* this part defined by EHCI spec */ |
cdeb9161 | 151 | uint32_t qt_next; /* see EHCI 3.5.1 */ |
aaf098cf | 152 | #define QT_NEXT_TERMINATE 1 |
cdeb9161 BT |
153 | uint32_t qt_altnext; /* see EHCI 3.5.2 */ |
154 | uint32_t qt_token; /* see EHCI 3.5.3 */ | |
14eb79b7 BT |
155 | #define QT_TOKEN_DT(x) (((x) & 0x1) << 31) /* Data Toggle */ |
156 | #define QT_TOKEN_GET_DT(x) (((x) >> 31) & 0x1) | |
157 | #define QT_TOKEN_TOTALBYTES(x) (((x) & 0x7fff) << 16) /* Total Bytes to Transfer */ | |
158 | #define QT_TOKEN_GET_TOTALBYTES(x) (((x) >> 16) & 0x7fff) | |
159 | #define QT_TOKEN_IOC(x) (((x) & 0x1) << 15) /* Interrupt On Complete */ | |
160 | #define QT_TOKEN_CPAGE(x) (((x) & 0x7) << 12) /* Current Page */ | |
161 | #define QT_TOKEN_CERR(x) (((x) & 0x3) << 10) /* Error Counter */ | |
162 | #define QT_TOKEN_PID(x) (((x) & 0x3) << 8) /* PID Code */ | |
163 | #define QT_TOKEN_PID_OUT 0x0 | |
164 | #define QT_TOKEN_PID_IN 0x1 | |
165 | #define QT_TOKEN_PID_SETUP 0x2 | |
166 | #define QT_TOKEN_STATUS(x) (((x) & 0xff) << 0) /* Status */ | |
167 | #define QT_TOKEN_GET_STATUS(x) (((x) >> 0) & 0xff) | |
168 | #define QT_TOKEN_STATUS_ACTIVE 0x80 | |
169 | #define QT_TOKEN_STATUS_HALTED 0x40 | |
170 | #define QT_TOKEN_STATUS_DATBUFERR 0x20 | |
171 | #define QT_TOKEN_STATUS_BABBLEDET 0x10 | |
172 | #define QT_TOKEN_STATUS_XACTERR 0x08 | |
173 | #define QT_TOKEN_STATUS_MISSEDUFRAME 0x04 | |
174 | #define QT_TOKEN_STATUS_SPLITXSTATE 0x02 | |
175 | #define QT_TOKEN_STATUS_PERR 0x01 | |
cdeb9161 BT |
176 | #define QT_BUFFER_CNT 5 |
177 | uint32_t qt_buffer[QT_BUFFER_CNT]; /* see EHCI 3.5.4 */ | |
178 | uint32_t qt_buffer_hi[QT_BUFFER_CNT]; /* Appendix B */ | |
3ed16071 WD |
179 | /* pad struct for 32 byte alignment */ |
180 | uint32_t unused[3]; | |
8b675fe1 | 181 | }; |
aaf098cf | 182 | |
14eb79b7 BT |
183 | #define EHCI_PAGE_SIZE 4096 |
184 | ||
aaf098cf MT |
185 | /* Queue Head (QH). */ |
186 | struct QH { | |
187 | uint32_t qh_link; | |
188 | #define QH_LINK_TERMINATE 1 | |
189 | #define QH_LINK_TYPE_ITD 0 | |
190 | #define QH_LINK_TYPE_QH 2 | |
191 | #define QH_LINK_TYPE_SITD 4 | |
192 | #define QH_LINK_TYPE_FSTN 6 | |
193 | uint32_t qh_endpt1; | |
14eb79b7 BT |
194 | #define QH_ENDPT1_RL(x) (((x) & 0xf) << 28) /* NAK Count Reload */ |
195 | #define QH_ENDPT1_C(x) (((x) & 0x1) << 27) /* Control Endpoint Flag */ | |
196 | #define QH_ENDPT1_MAXPKTLEN(x) (((x) & 0x7ff) << 16) /* Maximum Packet Length */ | |
197 | #define QH_ENDPT1_H(x) (((x) & 0x1) << 15) /* Head of Reclamation List Flag */ | |
198 | #define QH_ENDPT1_DTC(x) (((x) & 0x1) << 14) /* Data Toggle Control */ | |
199 | #define QH_ENDPT1_DTC_IGNORE_QTD_TD 0x0 | |
200 | #define QH_ENDPT1_DTC_DT_FROM_QTD 0x1 | |
201 | #define QH_ENDPT1_EPS(x) (((x) & 0x3) << 12) /* Endpoint Speed */ | |
202 | #define QH_ENDPT1_EPS_FS 0x0 | |
203 | #define QH_ENDPT1_EPS_LS 0x1 | |
204 | #define QH_ENDPT1_EPS_HS 0x2 | |
205 | #define QH_ENDPT1_ENDPT(x) (((x) & 0xf) << 8) /* Endpoint Number */ | |
206 | #define QH_ENDPT1_I(x) (((x) & 0x1) << 7) /* Inactivate on Next Transaction */ | |
207 | #define QH_ENDPT1_DEVADDR(x) (((x) & 0x7f) << 0) /* Device Address */ | |
aaf098cf | 208 | uint32_t qh_endpt2; |
14eb79b7 BT |
209 | #define QH_ENDPT2_MULT(x) (((x) & 0x3) << 30) /* High-Bandwidth Pipe Multiplier */ |
210 | #define QH_ENDPT2_PORTNUM(x) (((x) & 0x7f) << 23) /* Port Number */ | |
211 | #define QH_ENDPT2_HUBADDR(x) (((x) & 0x7f) << 16) /* Hub Address */ | |
212 | #define QH_ENDPT2_UFCMASK(x) (((x) & 0xff) << 8) /* Split Completion Mask */ | |
213 | #define QH_ENDPT2_UFSMASK(x) (((x) & 0xff) << 0) /* Interrupt Schedule Mask */ | |
aaf098cf MT |
214 | uint32_t qh_curtd; |
215 | struct qTD qh_overlay; | |
daa2dafb SR |
216 | /* |
217 | * Add dummy fill value to make the size of this struct | |
218 | * aligned to 32 bytes | |
219 | */ | |
8f62ca64 | 220 | union { |
61755c79 | 221 | uint32_t fill[4]; |
8f62ca64 PG |
222 | void *buffer; |
223 | }; | |
aaf098cf MT |
224 | }; |
225 | ||
7372b5bd SG |
226 | /* Tweak flags for EHCI, used to control operation */ |
227 | enum { | |
228 | /* don't use or_configflag in init */ | |
229 | EHCI_TWEAK_NO_INIT_CF = 1 << 0, | |
230 | }; | |
231 | ||
deb8508c SG |
232 | struct ehci_ctrl; |
233 | ||
234 | struct ehci_ops { | |
235 | void (*set_usb_mode)(struct ehci_ctrl *ctrl); | |
236 | int (*get_port_speed)(struct ehci_ctrl *ctrl, uint32_t reg); | |
237 | void (*powerup_fixup)(struct ehci_ctrl *ctrl, uint32_t *status_reg, | |
238 | uint32_t *reg); | |
239 | uint32_t *(*get_portsc_register)(struct ehci_ctrl *ctrl, int port); | |
3f9f8a5b | 240 | int (*init_after_reset)(struct ehci_ctrl *ctrl); |
deb8508c SG |
241 | }; |
242 | ||
b959655f | 243 | struct ehci_ctrl { |
49b4c5c7 | 244 | enum usb_init_type init; |
b959655f MV |
245 | struct ehci_hccr *hccr; /* R/O registers, not need for volatile */ |
246 | struct ehci_hcor *hcor; | |
247 | int rootdev; | |
248 | uint16_t portreset; | |
249 | struct QH qh_list __aligned(USB_DMA_MINALIGN); | |
250 | struct QH periodic_queue __aligned(USB_DMA_MINALIGN); | |
251 | uint32_t *periodic_list; | |
36b73109 | 252 | int periodic_schedules; |
b959655f | 253 | int ntds; |
deb8508c | 254 | struct ehci_ops ops; |
c4a3141d | 255 | void *priv; /* client's private data */ |
b959655f MV |
256 | }; |
257 | ||
c4a3141d | 258 | /** |
deb8508c | 259 | * ehci_set_controller_info() - Set up private data for the controller |
c4a3141d SG |
260 | * |
261 | * This function can be called in ehci_hcd_init() to tell the EHCI layer | |
262 | * about the controller's private data pointer. Then in the above functions | |
deb8508c SG |
263 | * this can be accessed given the struct ehci_ctrl pointer. Also special |
264 | * EHCI operation methods can be provided if required | |
c4a3141d SG |
265 | * |
266 | * @index: Controller number to set | |
267 | * @priv: Controller pointer | |
deb8508c | 268 | * @ops: Controller operations, or NULL to use default |
c4a3141d | 269 | */ |
deb8508c SG |
270 | void ehci_set_controller_priv(int index, void *priv, |
271 | const struct ehci_ops *ops); | |
c4a3141d SG |
272 | |
273 | /** | |
274 | * ehci_get_controller_priv() - Get controller private data | |
275 | * | |
276 | * @index Controller number to get | |
277 | * @return controller pointer for this index | |
278 | */ | |
279 | void *ehci_get_controller_priv(int index); | |
280 | ||
c0d722fe | 281 | /* Low level init functions */ |
127efc4f TK |
282 | int ehci_hcd_init(int index, enum usb_init_type init, |
283 | struct ehci_hccr **hccr, struct ehci_hcor **hcor); | |
676ae068 | 284 | int ehci_hcd_stop(int index); |
c0d722fe | 285 | |
46b01797 SG |
286 | int ehci_register(struct udevice *dev, struct ehci_hccr *hccr, |
287 | struct ehci_hcor *hcor, const struct ehci_ops *ops, | |
288 | uint tweaks, enum usb_init_type init); | |
289 | int ehci_deregister(struct udevice *dev); | |
290 | extern struct dm_usb_ops ehci_usb_ops; | |
291 | ||
aaf098cf | 292 | #endif /* USB_EHCI_H */ |