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Commit | Line | Data |
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3e326ece | 1 | /* |
4dae14ce ZW |
2 | * URB OHCI HCD (Host Controller Driver) for USB on the AT91RM9200 and PCI bus. |
3 | * | |
4 | * Interrupt support is added. Now, it has been tested | |
5 | * on ULI1575 chip and works well with USB keyboard. | |
6 | * | |
7 | * (C) Copyright 2007 | |
8 | * Zhang Wei, Freescale Semiconductor, Inc. <wei.zhang@freescale.com> | |
3e326ece MK |
9 | * |
10 | * (C) Copyright 2003 | |
792a09eb | 11 | * Gary Jennejohn, DENX Software Engineering <garyj@denx.de> |
3e326ece MK |
12 | * |
13 | * Note: Much of this code has been derived from Linux 2.4 | |
14 | * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> | |
15 | * (C) Copyright 2000-2002 David Brownell | |
16 | * | |
17 | * Modified for the MP2USB by (C) Copyright 2005 Eric Benard | |
18 | * ebenard@eukrea.com - based on s3c24x0's driver | |
19 | * | |
1a459660 | 20 | * SPDX-License-Identifier: GPL-2.0+ |
3e326ece MK |
21 | */ |
22 | /* | |
23 | * IMPORTANT NOTES | |
fc43be47 | 24 | * 1 - Read doc/README.generic_usb_ohci |
3e326ece | 25 | * 2 - this driver is intended for use with USB Mass Storage Devices |
4dae14ce | 26 | * (BBB) and USB keyboard. There is NO support for Isochronous pipes! |
fc43be47 | 27 | * 2 - when running on a PQFP208 AT91RM9200, define CONFIG_AT91C_PQFP_UHPBUG |
3e326ece MK |
28 | * to activate workaround for bug #41 or this driver will NOT work! |
29 | */ | |
30 | ||
31 | #include <common.h> | |
fc43be47 | 32 | #include <asm/byteorder.h> |
58b4048f HG |
33 | #include <dm.h> |
34 | #include <errno.h> | |
fc43be47 MK |
35 | |
36 | #if defined(CONFIG_PCI_OHCI) | |
4dae14ce | 37 | # include <pci.h> |
477434c6 SP |
38 | #if !defined(CONFIG_PCI_OHCI_DEVNO) |
39 | #define CONFIG_PCI_OHCI_DEVNO 0 | |
40 | #endif | |
ddf83a2f | 41 | #endif |
3e326ece MK |
42 | |
43 | #include <malloc.h> | |
cf92e05c | 44 | #include <memalign.h> |
3e326ece | 45 | #include <usb.h> |
2731b9a8 JCPV |
46 | |
47 | #include "ohci.h" | |
3e326ece | 48 | |
e8da58f2 WD |
49 | #ifdef CONFIG_AT91RM9200 |
50 | #include <asm/arch/hardware.h> /* needed for AT91_USB_HOST_BASE */ | |
51 | #endif | |
52 | ||
f2168440 | 53 | #if defined(CONFIG_CPU_ARM920T) || \ |
4dae14ce | 54 | defined(CONFIG_PCI_OHCI) || \ |
6d0f6bcf | 55 | defined(CONFIG_SYS_OHCI_USE_NPS) |
24e37645 MK |
56 | # define OHCI_USE_NPS /* force NoPowerSwitching mode */ |
57 | #endif | |
58 | ||
3e326ece | 59 | #undef OHCI_VERBOSE_DEBUG /* not always helpful */ |
ae3b770e MK |
60 | #undef DEBUG |
61 | #undef SHOW_INFO | |
62 | #undef OHCI_FILL_TRACE | |
3e326ece MK |
63 | |
64 | /* For initializing controller (mask in an HCFS mode too) */ | |
65 | #define OHCI_CONTROL_INIT \ | |
66 | (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE | |
67 | ||
4dae14ce ZW |
68 | #ifdef CONFIG_PCI_OHCI |
69 | static struct pci_device_id ohci_pci_ids[] = { | |
70 | {0x10b9, 0x5237}, /* ULI1575 PCI OHCI module ids */ | |
97213f32 | 71 | {0x1033, 0x0035}, /* NEC PCI OHCI module ids */ |
3afac79e | 72 | {0x1131, 0x1561}, /* Philips 1561 PCI OHCI module ids */ |
4dae14ce ZW |
73 | /* Please add supported PCI OHCI controller ids here */ |
74 | {0, 0} | |
75 | }; | |
76 | #endif | |
77 | ||
e90fb6af YT |
78 | #ifdef CONFIG_PCI_EHCI_DEVNO |
79 | static struct pci_device_id ehci_pci_ids[] = { | |
80 | {0x1131, 0x1562}, /* Philips 1562 PCI EHCI module ids */ | |
81 | /* Please add supported PCI EHCI controller ids here */ | |
82 | {0, 0} | |
83 | }; | |
84 | #endif | |
85 | ||
3e326ece MK |
86 | #ifdef DEBUG |
87 | #define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg) | |
88 | #else | |
6f5794a6 | 89 | #define dbg(format, arg...) do {} while (0) |
3e326ece MK |
90 | #endif /* DEBUG */ |
91 | #define err(format, arg...) printf("ERROR: " format "\n", ## arg) | |
3e326ece MK |
92 | #ifdef SHOW_INFO |
93 | #define info(format, arg...) printf("INFO: " format "\n", ## arg) | |
94 | #else | |
6f5794a6 | 95 | #define info(format, arg...) do {} while (0) |
3e326ece MK |
96 | #endif |
97 | ||
6d0f6bcf | 98 | #ifdef CONFIG_SYS_OHCI_BE_CONTROLLER |
fc43be47 MK |
99 | # define m16_swap(x) cpu_to_be16(x) |
100 | # define m32_swap(x) cpu_to_be32(x) | |
ae3b770e | 101 | #else |
fc43be47 MK |
102 | # define m16_swap(x) cpu_to_le16(x) |
103 | # define m32_swap(x) cpu_to_le32(x) | |
6d0f6bcf | 104 | #endif /* CONFIG_SYS_OHCI_BE_CONTROLLER */ |
3e326ece | 105 | |
e0266f49 | 106 | /* We really should do proper cache flushing everywhere */ |
8d005ef8 HG |
107 | #define flush_dcache_buffer(addr, size) \ |
108 | flush_dcache_range((unsigned long)(addr), \ | |
109 | ALIGN((unsigned long)(addr) + size, ARCH_DMA_MINALIGN)) | |
110 | #define invalidate_dcache_buffer(addr, size) \ | |
111 | invalidate_dcache_range((unsigned long)(addr), \ | |
112 | ALIGN((unsigned long)(addr) + size, ARCH_DMA_MINALIGN)) | |
8d005ef8 HG |
113 | |
114 | /* Do not use sizeof(ed / td) as our ed / td structs contain extra members */ | |
115 | #define flush_dcache_ed(addr) flush_dcache_buffer(addr, 16) | |
116 | #define flush_dcache_td(addr) flush_dcache_buffer(addr, 16) | |
117 | #define flush_dcache_iso_td(addr) flush_dcache_buffer(addr, 32) | |
118 | #define flush_dcache_hcca(addr) flush_dcache_buffer(addr, 256) | |
119 | #define invalidate_dcache_ed(addr) invalidate_dcache_buffer(addr, 16) | |
120 | #define invalidate_dcache_td(addr) invalidate_dcache_buffer(addr, 16) | |
121 | #define invalidate_dcache_iso_td(addr) invalidate_dcache_buffer(addr, 32) | |
122 | #define invalidate_dcache_hcca(addr) invalidate_dcache_buffer(addr, 256) | |
123 | ||
8f761f02 HG |
124 | #ifdef CONFIG_DM_USB |
125 | /* | |
126 | * The various ohci_mdelay(1) calls in the code seem unnecessary. We keep | |
127 | * them around when building for older boards not yet converted to the dm | |
128 | * just in case (to avoid regressions), for dm this turns them into nops. | |
129 | */ | |
130 | #define ohci_mdelay(x) | |
131 | #else | |
132 | #define ohci_mdelay(x) mdelay(x) | |
133 | #endif | |
134 | ||
58b4048f | 135 | #ifndef CONFIG_DM_USB |
3e326ece MK |
136 | /* global ohci_t */ |
137 | static ohci_t gohci; | |
138 | /* this must be aligned to a 256 byte boundary */ | |
139 | struct ohci_hcca ghcca[1]; | |
58b4048f | 140 | #endif |
3e326ece | 141 | |
6651c140 HG |
142 | /* mapping of the OHCI CC status to error codes */ |
143 | static int cc_to_error[16] = { | |
144 | /* No Error */ 0, | |
145 | /* CRC Error */ USB_ST_CRC_ERR, | |
146 | /* Bit Stuff */ USB_ST_BIT_ERR, | |
147 | /* Data Togg */ USB_ST_CRC_ERR, | |
148 | /* Stall */ USB_ST_STALLED, | |
149 | /* DevNotResp */ -1, | |
150 | /* PIDCheck */ USB_ST_BIT_ERR, | |
151 | /* UnExpPID */ USB_ST_BIT_ERR, | |
152 | /* DataOver */ USB_ST_BUF_ERR, | |
153 | /* DataUnder */ USB_ST_BUF_ERR, | |
154 | /* reservd */ -1, | |
155 | /* reservd */ -1, | |
156 | /* BufferOver */ USB_ST_BUF_ERR, | |
157 | /* BuffUnder */ USB_ST_BUF_ERR, | |
158 | /* Not Access */ -1, | |
159 | /* Not Access */ -1 | |
160 | }; | |
161 | ||
162 | static const char *cc_to_string[16] = { | |
163 | "No Error", | |
164 | "CRC: Last data packet from endpoint contained a CRC error.", | |
165 | "BITSTUFFING: Last data packet from endpoint contained a bit " \ | |
166 | "stuffing violation", | |
167 | "DATATOGGLEMISMATCH: Last packet from endpoint had data toggle PID\n" \ | |
168 | "that did not match the expected value.", | |
169 | "STALL: TD was moved to the Done Queue because the endpoint returned" \ | |
170 | " a STALL PID", | |
171 | "DEVICENOTRESPONDING: Device did not respond to token (IN) or did\n" \ | |
172 | "not provide a handshake (OUT)", | |
173 | "PIDCHECKFAILURE: Check bits on PID from endpoint failed on data PID\n"\ | |
174 | "(IN) or handshake (OUT)", | |
175 | "UNEXPECTEDPID: Receive PID was not valid when encountered or PID\n" \ | |
176 | "value is not defined.", | |
177 | "DATAOVERRUN: The amount of data returned by the endpoint exceeded\n" \ | |
178 | "either the size of the maximum data packet allowed\n" \ | |
179 | "from the endpoint (found in MaximumPacketSize field\n" \ | |
180 | "of ED) or the remaining buffer size.", | |
181 | "DATAUNDERRUN: The endpoint returned less than MaximumPacketSize\n" \ | |
182 | "and that amount was not sufficient to fill the\n" \ | |
183 | "specified buffer", | |
184 | "reserved1", | |
185 | "reserved2", | |
186 | "BUFFEROVERRUN: During an IN, HC received data from endpoint faster\n" \ | |
187 | "than it could be written to system memory", | |
188 | "BUFFERUNDERRUN: During an OUT, HC could not retrieve data from\n" \ | |
189 | "system memory fast enough to keep up with data USB " \ | |
190 | "data rate.", | |
191 | "NOT ACCESSED: This code is set by software before the TD is placed" \ | |
192 | "on a list to be processed by the HC.(1)", | |
193 | "NOT ACCESSED: This code is set by software before the TD is placed" \ | |
194 | "on a list to be processed by the HC.(2)", | |
195 | }; | |
196 | ||
6f5794a6 | 197 | static inline u32 roothub_a(struct ohci *hc) |
a5496a18 | 198 | { return ohci_readl(&hc->regs->roothub.a); } |
6f5794a6 | 199 | static inline u32 roothub_b(struct ohci *hc) |
a5496a18 | 200 | { return ohci_readl(&hc->regs->roothub.b); } |
6f5794a6 | 201 | static inline u32 roothub_status(struct ohci *hc) |
a5496a18 | 202 | { return ohci_readl(&hc->regs->roothub.status); } |
6f5794a6 | 203 | static inline u32 roothub_portstatus(struct ohci *hc, int i) |
a5496a18 | 204 | { return ohci_readl(&hc->regs->roothub.portstatus[i]); } |
3e326ece | 205 | |
3e326ece | 206 | /* forward declaration */ |
c5613df5 HG |
207 | static int hc_interrupt(ohci_t *ohci); |
208 | static void td_submit_job(ohci_t *ohci, struct usb_device *dev, | |
209 | unsigned long pipe, void *buffer, int transfer_len, | |
6f5794a6 RB |
210 | struct devrequest *setup, urb_priv_t *urb, |
211 | int interval); | |
6651c140 HG |
212 | static int ep_link(ohci_t * ohci, ed_t * ed); |
213 | static int ep_unlink(ohci_t * ohci, ed_t * ed); | |
214 | static ed_t *ep_add_ed(ohci_dev_t *ohci_dev, struct usb_device *usb_dev, | |
215 | unsigned long pipe, int interval, int load); | |
216 | ||
217 | /*-------------------------------------------------------------------------*/ | |
218 | ||
219 | /* TDs ... */ | |
220 | static struct td *td_alloc(ohci_dev_t *ohci_dev, struct usb_device *usb_dev) | |
221 | { | |
222 | int i; | |
223 | struct td *td; | |
224 | ||
225 | td = NULL; | |
226 | for (i = 0; i < NUM_TD; i++) | |
227 | { | |
228 | if (ohci_dev->tds[i].usb_dev == NULL) | |
229 | { | |
230 | td = &ohci_dev->tds[i]; | |
231 | td->usb_dev = usb_dev; | |
232 | break; | |
233 | } | |
234 | } | |
235 | ||
236 | return td; | |
237 | } | |
238 | ||
239 | static inline void ed_free(struct ed *ed) | |
240 | { | |
241 | ed->usb_dev = NULL; | |
242 | } | |
3e326ece MK |
243 | |
244 | /*-------------------------------------------------------------------------* | |
245 | * URB support functions | |
246 | *-------------------------------------------------------------------------*/ | |
247 | ||
248 | /* free HCD-private data associated with this URB */ | |
249 | ||
6f5794a6 | 250 | static void urb_free_priv(urb_priv_t *urb) |
3e326ece MK |
251 | { |
252 | int i; | |
253 | int last; | |
6f5794a6 | 254 | struct td *td; |
3e326ece MK |
255 | |
256 | last = urb->length - 1; | |
257 | if (last >= 0) { | |
258 | for (i = 0; i <= last; i++) { | |
259 | td = urb->td[i]; | |
260 | if (td) { | |
261 | td->usb_dev = NULL; | |
262 | urb->td[i] = NULL; | |
263 | } | |
264 | } | |
265 | } | |
4dae14ce | 266 | free(urb); |
3e326ece MK |
267 | } |
268 | ||
269 | /*-------------------------------------------------------------------------*/ | |
270 | ||
271 | #ifdef DEBUG | |
c5613df5 | 272 | static int sohci_get_current_frame_number(ohci_t *ohci); |
3e326ece MK |
273 | |
274 | /* debug| print the main components of an URB | |
275 | * small: 0) header + data packets 1) just header */ | |
276 | ||
c5613df5 | 277 | static void pkt_print(ohci_t *ohci, urb_priv_t *purb, struct usb_device *dev, |
6f5794a6 RB |
278 | unsigned long pipe, void *buffer, int transfer_len, |
279 | struct devrequest *setup, char *str, int small) | |
3e326ece | 280 | { |
6f5794a6 | 281 | dbg("%s URB:[%4x] dev:%2lu,ep:%2lu-%c,type:%s,len:%d/%d stat:%#lx", |
3e326ece | 282 | str, |
c5613df5 | 283 | sohci_get_current_frame_number(ohci), |
6f5794a6 RB |
284 | usb_pipedevice(pipe), |
285 | usb_pipeendpoint(pipe), | |
286 | usb_pipeout(pipe)? 'O': 'I', | |
287 | usb_pipetype(pipe) < 2 ? \ | |
288 | (usb_pipeint(pipe)? "INTR": "ISOC"): \ | |
289 | (usb_pipecontrol(pipe)? "CTRL": "BULK"), | |
4dae14ce | 290 | (purb ? purb->actual_length : 0), |
3e326ece MK |
291 | transfer_len, dev->status); |
292 | #ifdef OHCI_VERBOSE_DEBUG | |
293 | if (!small) { | |
294 | int i, len; | |
295 | ||
6f5794a6 RB |
296 | if (usb_pipecontrol(pipe)) { |
297 | printf(__FILE__ ": cmd(8):"); | |
3e326ece | 298 | for (i = 0; i < 8 ; i++) |
6f5794a6 RB |
299 | printf(" %02x", ((__u8 *) setup) [i]); |
300 | printf("\n"); | |
3e326ece MK |
301 | } |
302 | if (transfer_len > 0 && buffer) { | |
6f5794a6 | 303 | printf(__FILE__ ": data(%d/%d):", |
4dae14ce | 304 | (purb ? purb->actual_length : 0), |
3e326ece | 305 | transfer_len); |
6f5794a6 | 306 | len = usb_pipeout(pipe)? transfer_len: |
4dae14ce | 307 | (purb ? purb->actual_length : 0); |
3e326ece | 308 | for (i = 0; i < 16 && i < len; i++) |
6f5794a6 RB |
309 | printf(" %02x", ((__u8 *) buffer) [i]); |
310 | printf("%s\n", i < len? "...": ""); | |
3e326ece MK |
311 | } |
312 | } | |
313 | #endif | |
314 | } | |
315 | ||
6f5794a6 RB |
316 | /* just for debugging; prints non-empty branches of the int ed tree |
317 | * inclusive iso eds */ | |
318 | void ep_print_int_eds(ohci_t *ohci, char *str) | |
319 | { | |
3e326ece | 320 | int i, j; |
6f5794a6 RB |
321 | __u32 *ed_p; |
322 | for (i = 0; i < 32; i++) { | |
3e326ece MK |
323 | j = 5; |
324 | ed_p = &(ohci->hcca->int_table [i]); | |
325 | if (*ed_p == 0) | |
326 | continue; | |
8d005ef8 | 327 | invalidate_dcache_ed(ed_p); |
6f5794a6 | 328 | printf(__FILE__ ": %s branch int %2d(%2x):", str, i, i); |
3e326ece MK |
329 | while (*ed_p != 0 && j--) { |
330 | ed_t *ed = (ed_t *)m32_swap(ed_p); | |
8d005ef8 | 331 | invalidate_dcache_ed(ed); |
6f5794a6 | 332 | printf(" ed: %4x;", ed->hwINFO); |
3e326ece MK |
333 | ed_p = &ed->hwNextED; |
334 | } | |
6f5794a6 | 335 | printf("\n"); |
3e326ece MK |
336 | } |
337 | } | |
338 | ||
6f5794a6 | 339 | static void ohci_dump_intr_mask(char *label, __u32 mask) |
3e326ece | 340 | { |
6f5794a6 | 341 | dbg("%s: 0x%08x%s%s%s%s%s%s%s%s%s", |
3e326ece MK |
342 | label, |
343 | mask, | |
344 | (mask & OHCI_INTR_MIE) ? " MIE" : "", | |
345 | (mask & OHCI_INTR_OC) ? " OC" : "", | |
346 | (mask & OHCI_INTR_RHSC) ? " RHSC" : "", | |
347 | (mask & OHCI_INTR_FNO) ? " FNO" : "", | |
348 | (mask & OHCI_INTR_UE) ? " UE" : "", | |
349 | (mask & OHCI_INTR_RD) ? " RD" : "", | |
350 | (mask & OHCI_INTR_SF) ? " SF" : "", | |
351 | (mask & OHCI_INTR_WDH) ? " WDH" : "", | |
352 | (mask & OHCI_INTR_SO) ? " SO" : "" | |
353 | ); | |
354 | } | |
355 | ||
6f5794a6 | 356 | static void maybe_print_eds(char *label, __u32 value) |
3e326ece MK |
357 | { |
358 | ed_t *edp = (ed_t *)value; | |
359 | ||
360 | if (value) { | |
6f5794a6 | 361 | dbg("%s %08x", label, value); |
8d005ef8 | 362 | invalidate_dcache_ed(edp); |
6f5794a6 RB |
363 | dbg("%08x", edp->hwINFO); |
364 | dbg("%08x", edp->hwTailP); | |
365 | dbg("%08x", edp->hwHeadP); | |
366 | dbg("%08x", edp->hwNextED); | |
3e326ece MK |
367 | } |
368 | } | |
369 | ||
6f5794a6 | 370 | static char *hcfs2string(int state) |
3e326ece MK |
371 | { |
372 | switch (state) { | |
6f5794a6 RB |
373 | case OHCI_USB_RESET: return "reset"; |
374 | case OHCI_USB_RESUME: return "resume"; | |
375 | case OHCI_USB_OPER: return "operational"; | |
376 | case OHCI_USB_SUSPEND: return "suspend"; | |
3e326ece MK |
377 | } |
378 | return "?"; | |
379 | } | |
380 | ||
381 | /* dump control and status registers */ | |
6f5794a6 | 382 | static void ohci_dump_status(ohci_t *controller) |
3e326ece MK |
383 | { |
384 | struct ohci_regs *regs = controller->regs; | |
385 | __u32 temp; | |
386 | ||
a5496a18 | 387 | temp = ohci_readl(®s->revision) & 0xff; |
3e326ece | 388 | if (temp != 0x10) |
6f5794a6 | 389 | dbg("spec %d.%d", (temp >> 4), (temp & 0x0f)); |
3e326ece | 390 | |
a5496a18 | 391 | temp = ohci_readl(®s->control); |
6f5794a6 | 392 | dbg("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp, |
3e326ece MK |
393 | (temp & OHCI_CTRL_RWE) ? " RWE" : "", |
394 | (temp & OHCI_CTRL_RWC) ? " RWC" : "", | |
395 | (temp & OHCI_CTRL_IR) ? " IR" : "", | |
6f5794a6 | 396 | hcfs2string(temp & OHCI_CTRL_HCFS), |
3e326ece MK |
397 | (temp & OHCI_CTRL_BLE) ? " BLE" : "", |
398 | (temp & OHCI_CTRL_CLE) ? " CLE" : "", | |
399 | (temp & OHCI_CTRL_IE) ? " IE" : "", | |
400 | (temp & OHCI_CTRL_PLE) ? " PLE" : "", | |
401 | temp & OHCI_CTRL_CBSR | |
402 | ); | |
403 | ||
a5496a18 | 404 | temp = ohci_readl(®s->cmdstatus); |
6f5794a6 | 405 | dbg("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp, |
3e326ece MK |
406 | (temp & OHCI_SOC) >> 16, |
407 | (temp & OHCI_OCR) ? " OCR" : "", | |
408 | (temp & OHCI_BLF) ? " BLF" : "", | |
409 | (temp & OHCI_CLF) ? " CLF" : "", | |
410 | (temp & OHCI_HCR) ? " HCR" : "" | |
411 | ); | |
412 | ||
a5496a18 BB |
413 | ohci_dump_intr_mask("intrstatus", ohci_readl(®s->intrstatus)); |
414 | ohci_dump_intr_mask("intrenable", ohci_readl(®s->intrenable)); | |
3e326ece | 415 | |
a5496a18 BB |
416 | maybe_print_eds("ed_periodcurrent", |
417 | ohci_readl(®s->ed_periodcurrent)); | |
3e326ece | 418 | |
a5496a18 BB |
419 | maybe_print_eds("ed_controlhead", ohci_readl(®s->ed_controlhead)); |
420 | maybe_print_eds("ed_controlcurrent", | |
421 | ohci_readl(®s->ed_controlcurrent)); | |
3e326ece | 422 | |
a5496a18 BB |
423 | maybe_print_eds("ed_bulkhead", ohci_readl(®s->ed_bulkhead)); |
424 | maybe_print_eds("ed_bulkcurrent", ohci_readl(®s->ed_bulkcurrent)); | |
3e326ece | 425 | |
a5496a18 | 426 | maybe_print_eds("donehead", ohci_readl(®s->donehead)); |
3e326ece MK |
427 | } |
428 | ||
6f5794a6 | 429 | static void ohci_dump_roothub(ohci_t *controller, int verbose) |
3e326ece MK |
430 | { |
431 | __u32 temp, ndp, i; | |
432 | ||
6f5794a6 | 433 | temp = roothub_a(controller); |
3e326ece MK |
434 | ndp = (temp & RH_A_NDP); |
435 | #ifdef CONFIG_AT91C_PQFP_UHPBUG | |
436 | ndp = (ndp == 2) ? 1:0; | |
3e326ece MK |
437 | #endif |
438 | if (verbose) { | |
6f5794a6 | 439 | dbg("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp, |
3e326ece MK |
440 | ((temp & RH_A_POTPGT) >> 24) & 0xff, |
441 | (temp & RH_A_NOCP) ? " NOCP" : "", | |
442 | (temp & RH_A_OCPM) ? " OCPM" : "", | |
443 | (temp & RH_A_DT) ? " DT" : "", | |
444 | (temp & RH_A_NPS) ? " NPS" : "", | |
445 | (temp & RH_A_PSM) ? " PSM" : "", | |
446 | ndp | |
447 | ); | |
6f5794a6 RB |
448 | temp = roothub_b(controller); |
449 | dbg("roothub.b: %08x PPCM=%04x DR=%04x", | |
3e326ece MK |
450 | temp, |
451 | (temp & RH_B_PPCM) >> 16, | |
452 | (temp & RH_B_DR) | |
453 | ); | |
6f5794a6 RB |
454 | temp = roothub_status(controller); |
455 | dbg("roothub.status: %08x%s%s%s%s%s%s", | |
3e326ece MK |
456 | temp, |
457 | (temp & RH_HS_CRWE) ? " CRWE" : "", | |
458 | (temp & RH_HS_OCIC) ? " OCIC" : "", | |
459 | (temp & RH_HS_LPSC) ? " LPSC" : "", | |
460 | (temp & RH_HS_DRWE) ? " DRWE" : "", | |
461 | (temp & RH_HS_OCI) ? " OCI" : "", | |
462 | (temp & RH_HS_LPS) ? " LPS" : "" | |
463 | ); | |
464 | } | |
465 | ||
466 | for (i = 0; i < ndp; i++) { | |
6f5794a6 RB |
467 | temp = roothub_portstatus(controller, i); |
468 | dbg("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s", | |
3e326ece MK |
469 | i, |
470 | temp, | |
471 | (temp & RH_PS_PRSC) ? " PRSC" : "", | |
472 | (temp & RH_PS_OCIC) ? " OCIC" : "", | |
473 | (temp & RH_PS_PSSC) ? " PSSC" : "", | |
474 | (temp & RH_PS_PESC) ? " PESC" : "", | |
475 | (temp & RH_PS_CSC) ? " CSC" : "", | |
476 | ||
477 | (temp & RH_PS_LSDA) ? " LSDA" : "", | |
478 | (temp & RH_PS_PPS) ? " PPS" : "", | |
479 | (temp & RH_PS_PRS) ? " PRS" : "", | |
480 | (temp & RH_PS_POCI) ? " POCI" : "", | |
481 | (temp & RH_PS_PSS) ? " PSS" : "", | |
482 | ||
483 | (temp & RH_PS_PES) ? " PES" : "", | |
484 | (temp & RH_PS_CCS) ? " CCS" : "" | |
485 | ); | |
486 | } | |
487 | } | |
488 | ||
6f5794a6 | 489 | static void ohci_dump(ohci_t *controller, int verbose) |
3e326ece | 490 | { |
6f5794a6 | 491 | dbg("OHCI controller usb-%s state", controller->slot_name); |
3e326ece MK |
492 | |
493 | /* dumps some of the state we know about */ | |
6f5794a6 | 494 | ohci_dump_status(controller); |
3e326ece | 495 | if (verbose) |
6f5794a6 | 496 | ep_print_int_eds(controller, "hcca"); |
8d005ef8 | 497 | invalidate_dcache_hcca(controller->hcca); |
6f5794a6 RB |
498 | dbg("hcca frame #%04x", controller->hcca->frame_no); |
499 | ohci_dump_roothub(controller, 1); | |
2596f5b9 | 500 | } |
3e326ece MK |
501 | #endif /* DEBUG */ |
502 | ||
503 | /*-------------------------------------------------------------------------* | |
504 | * Interface functions (URB) | |
505 | *-------------------------------------------------------------------------*/ | |
506 | ||
507 | /* get a transfer request */ | |
508 | ||
19d95d57 HG |
509 | int sohci_submit_job(ohci_t *ohci, ohci_dev_t *ohci_dev, urb_priv_t *urb, |
510 | struct devrequest *setup) | |
3e326ece | 511 | { |
6f5794a6 | 512 | ed_t *ed; |
4dae14ce | 513 | urb_priv_t *purb_priv = urb; |
3e326ece | 514 | int i, size = 0; |
4dae14ce ZW |
515 | struct usb_device *dev = urb->dev; |
516 | unsigned long pipe = urb->pipe; | |
517 | void *buffer = urb->transfer_buffer; | |
518 | int transfer_len = urb->transfer_buffer_length; | |
519 | int interval = urb->interval; | |
3e326ece | 520 | |
3e326ece MK |
521 | /* when controller's hung, permit only roothub cleanup attempts |
522 | * such as powering down ports */ | |
523 | if (ohci->disabled) { | |
524 | err("sohci_submit_job: EPIPE"); | |
525 | return -1; | |
526 | } | |
ae79f606 | 527 | |
6f5794a6 RB |
528 | /* we're about to begin a new transaction here so mark the |
529 | * URB unfinished */ | |
4dae14ce | 530 | urb->finished = 0; |
3e326ece MK |
531 | |
532 | /* every endpoint has a ed, locate and fill it */ | |
19d95d57 | 533 | ed = ep_add_ed(ohci_dev, dev, pipe, interval, 1); |
6f5794a6 | 534 | if (!ed) { |
3e326ece MK |
535 | err("sohci_submit_job: ENOMEM"); |
536 | return -1; | |
537 | } | |
538 | ||
539 | /* for the private part of the URB we need the number of TDs (size) */ | |
6f5794a6 RB |
540 | switch (usb_pipetype(pipe)) { |
541 | case PIPE_BULK: /* one TD for every 4096 Byte */ | |
542 | size = (transfer_len - 1) / 4096 + 1; | |
543 | break; | |
544 | case PIPE_CONTROL:/* 1 TD for setup, 1 for ACK and 1 for every 4096 B */ | |
545 | size = (transfer_len == 0)? 2: | |
546 | (transfer_len - 1) / 4096 + 3; | |
547 | break; | |
548 | case PIPE_INTERRUPT: /* 1 TD */ | |
549 | size = 1; | |
550 | break; | |
3e326ece MK |
551 | } |
552 | ||
4dae14ce ZW |
553 | ed->purb = urb; |
554 | ||
3e326ece MK |
555 | if (size >= (N_URB_TD - 1)) { |
556 | err("need %d TDs, only have %d", size, N_URB_TD); | |
557 | return -1; | |
558 | } | |
3e326ece MK |
559 | purb_priv->pipe = pipe; |
560 | ||
561 | /* fill the private part of the URB */ | |
562 | purb_priv->length = size; | |
563 | purb_priv->ed = ed; | |
564 | purb_priv->actual_length = 0; | |
565 | ||
566 | /* allocate the TDs */ | |
567 | /* note that td[0] was allocated in ep_add_ed */ | |
568 | for (i = 0; i < size; i++) { | |
3c5497d8 | 569 | purb_priv->td[i] = td_alloc(ohci_dev, dev); |
3e326ece MK |
570 | if (!purb_priv->td[i]) { |
571 | purb_priv->length = i; | |
6f5794a6 | 572 | urb_free_priv(purb_priv); |
3e326ece MK |
573 | err("sohci_submit_job: ENOMEM"); |
574 | return -1; | |
575 | } | |
576 | } | |
577 | ||
578 | if (ed->state == ED_NEW || (ed->state & ED_DEL)) { | |
6f5794a6 | 579 | urb_free_priv(purb_priv); |
3e326ece MK |
580 | err("sohci_submit_job: EINVAL"); |
581 | return -1; | |
582 | } | |
583 | ||
584 | /* link the ed into a chain if is not already */ | |
585 | if (ed->state != ED_OPER) | |
6f5794a6 | 586 | ep_link(ohci, ed); |
3e326ece MK |
587 | |
588 | /* fill the TDs and link it to the ed */ | |
c5613df5 | 589 | td_submit_job(ohci, dev, pipe, buffer, transfer_len, |
6f5794a6 | 590 | setup, purb_priv, interval); |
3e326ece MK |
591 | |
592 | return 0; | |
593 | } | |
594 | ||
595 | /*-------------------------------------------------------------------------*/ | |
596 | ||
597 | #ifdef DEBUG | |
598 | /* tell us the current USB frame number */ | |
c5613df5 | 599 | static int sohci_get_current_frame_number(ohci_t *ohci) |
3e326ece | 600 | { |
8d005ef8 | 601 | invalidate_dcache_hcca(ohci->hcca); |
6f5794a6 | 602 | return m16_swap(ohci->hcca->frame_no); |
3e326ece MK |
603 | } |
604 | #endif | |
605 | ||
4dae14ce ZW |
606 | /*-------------------------------------------------------------------------* |
607 | * ED handling functions | |
608 | *-------------------------------------------------------------------------*/ | |
609 | ||
610 | /* search for the right branch to insert an interrupt ed into the int tree | |
611 | * do some load ballancing; | |
612 | * returns the branch and | |
613 | * sets the interval to interval = 2^integer (ld (interval)) */ | |
614 | ||
6f5794a6 | 615 | static int ep_int_ballance(ohci_t *ohci, int interval, int load) |
4dae14ce ZW |
616 | { |
617 | int i, branch = 0; | |
618 | ||
619 | /* search for the least loaded interrupt endpoint | |
620 | * branch of all 32 branches | |
621 | */ | |
622 | for (i = 0; i < 32; i++) | |
623 | if (ohci->ohci_int_load [branch] > ohci->ohci_int_load [i]) | |
624 | branch = i; | |
625 | ||
626 | branch = branch % interval; | |
627 | for (i = branch; i < 32; i += interval) | |
628 | ohci->ohci_int_load [i] += load; | |
629 | ||
630 | return branch; | |
631 | } | |
632 | ||
633 | /*-------------------------------------------------------------------------*/ | |
634 | ||
635 | /* 2^int( ld (inter)) */ | |
636 | ||
6f5794a6 | 637 | static int ep_2_n_interval(int inter) |
4dae14ce ZW |
638 | { |
639 | int i; | |
6f5794a6 | 640 | for (i = 0; ((inter >> i) > 1) && (i < 5); i++); |
4dae14ce ZW |
641 | return 1 << i; |
642 | } | |
643 | ||
644 | /*-------------------------------------------------------------------------*/ | |
645 | ||
646 | /* the int tree is a binary tree | |
6f5794a6 RB |
647 | * in order to process it sequentially the indexes of the branches have to |
648 | * be mapped the mapping reverses the bits of a word of num_bits length */ | |
649 | static int ep_rev(int num_bits, int word) | |
4dae14ce ZW |
650 | { |
651 | int i, wout = 0; | |
652 | ||
653 | for (i = 0; i < num_bits; i++) | |
654 | wout |= (((word >> i) & 1) << (num_bits - i - 1)); | |
655 | return wout; | |
656 | } | |
657 | ||
3e326ece MK |
658 | /*-------------------------------------------------------------------------* |
659 | * ED handling functions | |
660 | *-------------------------------------------------------------------------*/ | |
661 | ||
662 | /* link an ed into one of the HC chains */ | |
663 | ||
6f5794a6 | 664 | static int ep_link(ohci_t *ohci, ed_t *edi) |
3e326ece MK |
665 | { |
666 | volatile ed_t *ed = edi; | |
4dae14ce ZW |
667 | int int_branch; |
668 | int i; | |
669 | int inter; | |
670 | int interval; | |
671 | int load; | |
6f5794a6 | 672 | __u32 *ed_p; |
3e326ece MK |
673 | |
674 | ed->state = ED_OPER; | |
4dae14ce | 675 | ed->int_interval = 0; |
3e326ece MK |
676 | |
677 | switch (ed->type) { | |
678 | case PIPE_CONTROL: | |
679 | ed->hwNextED = 0; | |
8d005ef8 | 680 | flush_dcache_ed(ed); |
6f5794a6 | 681 | if (ohci->ed_controltail == NULL) |
57faca19 | 682 | ohci_writel((uintptr_t)ed, &ohci->regs->ed_controlhead); |
6f5794a6 RB |
683 | else |
684 | ohci->ed_controltail->hwNextED = | |
685 | m32_swap((unsigned long)ed); | |
686 | ||
3e326ece MK |
687 | ed->ed_prev = ohci->ed_controltail; |
688 | if (!ohci->ed_controltail && !ohci->ed_rm_list[0] && | |
689 | !ohci->ed_rm_list[1] && !ohci->sleeping) { | |
690 | ohci->hc_control |= OHCI_CTRL_CLE; | |
a5496a18 | 691 | ohci_writel(ohci->hc_control, &ohci->regs->control); |
3e326ece MK |
692 | } |
693 | ohci->ed_controltail = edi; | |
694 | break; | |
695 | ||
696 | case PIPE_BULK: | |
697 | ed->hwNextED = 0; | |
8d005ef8 | 698 | flush_dcache_ed(ed); |
6f5794a6 | 699 | if (ohci->ed_bulktail == NULL) |
57faca19 | 700 | ohci_writel((uintptr_t)ed, &ohci->regs->ed_bulkhead); |
6f5794a6 RB |
701 | else |
702 | ohci->ed_bulktail->hwNextED = | |
703 | m32_swap((unsigned long)ed); | |
704 | ||
3e326ece MK |
705 | ed->ed_prev = ohci->ed_bulktail; |
706 | if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] && | |
707 | !ohci->ed_rm_list[1] && !ohci->sleeping) { | |
708 | ohci->hc_control |= OHCI_CTRL_BLE; | |
a5496a18 | 709 | ohci_writel(ohci->hc_control, &ohci->regs->control); |
3e326ece MK |
710 | } |
711 | ohci->ed_bulktail = edi; | |
712 | break; | |
4dae14ce ZW |
713 | |
714 | case PIPE_INTERRUPT: | |
715 | load = ed->int_load; | |
6f5794a6 | 716 | interval = ep_2_n_interval(ed->int_period); |
4dae14ce | 717 | ed->int_interval = interval; |
6f5794a6 | 718 | int_branch = ep_int_ballance(ohci, interval, load); |
4dae14ce ZW |
719 | ed->int_branch = int_branch; |
720 | ||
6f5794a6 | 721 | for (i = 0; i < ep_rev(6, interval); i += inter) { |
4dae14ce | 722 | inter = 1; |
6f5794a6 RB |
723 | for (ed_p = &(ohci->hcca->int_table[\ |
724 | ep_rev(5, i) + int_branch]); | |
725 | (*ed_p != 0) && | |
726 | (((ed_t *)ed_p)->int_interval >= interval); | |
4dae14ce | 727 | ed_p = &(((ed_t *)ed_p)->hwNextED)) |
6f5794a6 RB |
728 | inter = ep_rev(6, |
729 | ((ed_t *)ed_p)->int_interval); | |
4dae14ce | 730 | ed->hwNextED = *ed_p; |
8d005ef8 | 731 | flush_dcache_ed(ed); |
4a8527ef | 732 | *ed_p = m32_swap((unsigned long)ed); |
8d005ef8 | 733 | flush_dcache_hcca(ohci->hcca); |
4dae14ce ZW |
734 | } |
735 | break; | |
3e326ece MK |
736 | } |
737 | return 0; | |
738 | } | |
739 | ||
740 | /*-------------------------------------------------------------------------*/ | |
741 | ||
4dae14ce | 742 | /* scan the periodic table to find and unlink this ED */ |
6f5794a6 RB |
743 | static void periodic_unlink(struct ohci *ohci, volatile struct ed *ed, |
744 | unsigned index, unsigned period) | |
4dae14ce | 745 | { |
8d005ef8 HG |
746 | __maybe_unused unsigned long aligned_ed_p; |
747 | ||
4dae14ce ZW |
748 | for (; index < NUM_INTS; index += period) { |
749 | __u32 *ed_p = &ohci->hcca->int_table [index]; | |
750 | ||
751 | /* ED might have been unlinked through another path */ | |
752 | while (*ed_p != 0) { | |
57faca19 | 753 | if (((struct ed *)(uintptr_t) |
6f5794a6 | 754 | m32_swap((unsigned long)ed_p)) == ed) { |
4dae14ce | 755 | *ed_p = ed->hwNextED; |
8d005ef8 HG |
756 | aligned_ed_p = (unsigned long)ed_p; |
757 | aligned_ed_p &= ~(ARCH_DMA_MINALIGN - 1); | |
758 | flush_dcache_range(aligned_ed_p, | |
759 | aligned_ed_p + ARCH_DMA_MINALIGN); | |
4dae14ce ZW |
760 | break; |
761 | } | |
57faca19 | 762 | ed_p = &(((struct ed *)(uintptr_t) |
6f5794a6 | 763 | m32_swap((unsigned long)ed_p))->hwNextED); |
4dae14ce ZW |
764 | } |
765 | } | |
766 | } | |
767 | ||
3e326ece MK |
768 | /* unlink an ed from one of the HC chains. |
769 | * just the link to the ed is unlinked. | |
770 | * the link from the ed still points to another operational ed or 0 | |
771 | * so the HC can eventually finish the processing of the unlinked ed */ | |
772 | ||
6f5794a6 | 773 | static int ep_unlink(ohci_t *ohci, ed_t *edi) |
3e326ece | 774 | { |
53e336e9 | 775 | volatile ed_t *ed = edi; |
4dae14ce | 776 | int i; |
53e336e9 | 777 | |
6f5794a6 | 778 | ed->hwINFO |= m32_swap(OHCI_ED_SKIP); |
8d005ef8 | 779 | flush_dcache_ed(ed); |
3e326ece MK |
780 | |
781 | switch (ed->type) { | |
782 | case PIPE_CONTROL: | |
783 | if (ed->ed_prev == NULL) { | |
784 | if (!ed->hwNextED) { | |
785 | ohci->hc_control &= ~OHCI_CTRL_CLE; | |
a5496a18 BB |
786 | ohci_writel(ohci->hc_control, |
787 | &ohci->regs->control); | |
3e326ece | 788 | } |
a5496a18 | 789 | ohci_writel(m32_swap(*((__u32 *)&ed->hwNextED)), |
6f5794a6 | 790 | &ohci->regs->ed_controlhead); |
3e326ece MK |
791 | } else { |
792 | ed->ed_prev->hwNextED = ed->hwNextED; | |
8d005ef8 | 793 | flush_dcache_ed(ed->ed_prev); |
3e326ece MK |
794 | } |
795 | if (ohci->ed_controltail == ed) { | |
796 | ohci->ed_controltail = ed->ed_prev; | |
797 | } else { | |
57faca19 | 798 | ((ed_t *)(uintptr_t)m32_swap( |
6f5794a6 | 799 | *((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; |
3e326ece MK |
800 | } |
801 | break; | |
802 | ||
803 | case PIPE_BULK: | |
804 | if (ed->ed_prev == NULL) { | |
805 | if (!ed->hwNextED) { | |
806 | ohci->hc_control &= ~OHCI_CTRL_BLE; | |
a5496a18 BB |
807 | ohci_writel(ohci->hc_control, |
808 | &ohci->regs->control); | |
3e326ece | 809 | } |
a5496a18 | 810 | ohci_writel(m32_swap(*((__u32 *)&ed->hwNextED)), |
6f5794a6 | 811 | &ohci->regs->ed_bulkhead); |
3e326ece MK |
812 | } else { |
813 | ed->ed_prev->hwNextED = ed->hwNextED; | |
8d005ef8 | 814 | flush_dcache_ed(ed->ed_prev); |
3e326ece MK |
815 | } |
816 | if (ohci->ed_bulktail == ed) { | |
817 | ohci->ed_bulktail = ed->ed_prev; | |
818 | } else { | |
57faca19 | 819 | ((ed_t *)(uintptr_t)m32_swap( |
6f5794a6 | 820 | *((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; |
3e326ece MK |
821 | } |
822 | break; | |
4dae14ce ZW |
823 | |
824 | case PIPE_INTERRUPT: | |
6f5794a6 | 825 | periodic_unlink(ohci, ed, 0, 1); |
4dae14ce ZW |
826 | for (i = ed->int_branch; i < 32; i += ed->int_interval) |
827 | ohci->ohci_int_load[i] -= ed->int_load; | |
828 | break; | |
3e326ece MK |
829 | } |
830 | ed->state = ED_UNLINK; | |
831 | return 0; | |
832 | } | |
833 | ||
3e326ece MK |
834 | /*-------------------------------------------------------------------------*/ |
835 | ||
ddf83a2f MK |
836 | /* add/reinit an endpoint; this should be done once at the |
837 | * usb_set_configuration command, but the USB stack is a little bit | |
838 | * stateless so we do it at every transaction if the state of the ed | |
839 | * is ED_NEW then a dummy td is added and the state is changed to | |
840 | * ED_UNLINK in all other cases the state is left unchanged the ed | |
841 | * info fields are setted anyway even though most of them should not | |
842 | * change | |
843 | */ | |
19d95d57 HG |
844 | static ed_t *ep_add_ed(ohci_dev_t *ohci_dev, struct usb_device *usb_dev, |
845 | unsigned long pipe, int interval, int load) | |
3e326ece MK |
846 | { |
847 | td_t *td; | |
848 | ed_t *ed_ret; | |
849 | volatile ed_t *ed; | |
850 | ||
19d95d57 | 851 | ed = ed_ret = &ohci_dev->ed[(usb_pipeendpoint(pipe) << 1) | |
6f5794a6 | 852 | (usb_pipecontrol(pipe)? 0: usb_pipeout(pipe))]; |
3e326ece MK |
853 | |
854 | if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) { | |
855 | err("ep_add_ed: pending delete"); | |
856 | /* pending delete request */ | |
857 | return NULL; | |
858 | } | |
859 | ||
860 | if (ed->state == ED_NEW) { | |
3e326ece | 861 | /* dummy td; end of td list for ed */ |
3c5497d8 | 862 | td = td_alloc(ohci_dev, usb_dev); |
6f5794a6 | 863 | ed->hwTailP = m32_swap((unsigned long)td); |
3e326ece MK |
864 | ed->hwHeadP = ed->hwTailP; |
865 | ed->state = ED_UNLINK; | |
6f5794a6 | 866 | ed->type = usb_pipetype(pipe); |
19d95d57 | 867 | ohci_dev->ed_cnt++; |
3e326ece MK |
868 | } |
869 | ||
6f5794a6 RB |
870 | ed->hwINFO = m32_swap(usb_pipedevice(pipe) |
871 | | usb_pipeendpoint(pipe) << 7 | |
872 | | (usb_pipeisoc(pipe)? 0x8000: 0) | |
873 | | (usb_pipecontrol(pipe)? 0: \ | |
874 | (usb_pipeout(pipe)? 0x800: 0x1000)) | |
c60795f4 | 875 | | (usb_dev->speed == USB_SPEED_LOW) << 13 |
6f5794a6 | 876 | | usb_maxpacket(usb_dev, pipe) << 16); |
3e326ece | 877 | |
4dae14ce ZW |
878 | if (ed->type == PIPE_INTERRUPT && ed->state == ED_UNLINK) { |
879 | ed->int_period = interval; | |
880 | ed->int_load = load; | |
881 | } | |
882 | ||
8d005ef8 HG |
883 | flush_dcache_ed(ed); |
884 | ||
3e326ece MK |
885 | return ed_ret; |
886 | } | |
887 | ||
888 | /*-------------------------------------------------------------------------* | |
889 | * TD handling functions | |
890 | *-------------------------------------------------------------------------*/ | |
891 | ||
892 | /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */ | |
893 | ||
6f5794a6 | 894 | static void td_fill(ohci_t *ohci, unsigned int info, |
3e326ece MK |
895 | void *data, int len, |
896 | struct usb_device *dev, int index, urb_priv_t *urb_priv) | |
897 | { | |
898 | volatile td_t *td, *td_pt; | |
899 | #ifdef OHCI_FILL_TRACE | |
900 | int i; | |
901 | #endif | |
902 | ||
903 | if (index > urb_priv->length) { | |
904 | err("index > length"); | |
905 | return; | |
906 | } | |
907 | /* use this td as the next dummy */ | |
908 | td_pt = urb_priv->td [index]; | |
909 | td_pt->hwNextTD = 0; | |
8d005ef8 | 910 | flush_dcache_td(td_pt); |
3e326ece MK |
911 | |
912 | /* fill the old dummy TD */ | |
6f5794a6 | 913 | td = urb_priv->td [index] = |
57faca19 AP |
914 | (td_t *)(uintptr_t) |
915 | (m32_swap(urb_priv->ed->hwTailP) & ~0xf); | |
3e326ece MK |
916 | |
917 | td->ed = urb_priv->ed; | |
918 | td->next_dl_td = NULL; | |
919 | td->index = index; | |
57faca19 | 920 | td->data = (uintptr_t)data; |
3e326ece | 921 | #ifdef OHCI_FILL_TRACE |
48867208 | 922 | if (usb_pipebulk(urb_priv->pipe) && usb_pipeout(urb_priv->pipe)) { |
3e326ece | 923 | for (i = 0; i < len; i++) |
6f5794a6 | 924 | printf("td->data[%d] %#2x ", i, ((unsigned char *)td->data)[i]); |
3e326ece MK |
925 | printf("\n"); |
926 | } | |
927 | #endif | |
928 | if (!len) | |
929 | data = 0; | |
930 | ||
6f5794a6 RB |
931 | td->hwINFO = m32_swap(info); |
932 | td->hwCBP = m32_swap((unsigned long)data); | |
3e326ece | 933 | if (data) |
6f5794a6 | 934 | td->hwBE = m32_swap((unsigned long)(data + len - 1)); |
3e326ece MK |
935 | else |
936 | td->hwBE = 0; | |
6f5794a6 RB |
937 | |
938 | td->hwNextTD = m32_swap((unsigned long)td_pt); | |
8d005ef8 | 939 | flush_dcache_td(td); |
3e326ece MK |
940 | |
941 | /* append to queue */ | |
942 | td->ed->hwTailP = td->hwNextTD; | |
8d005ef8 | 943 | flush_dcache_ed(td->ed); |
3e326ece MK |
944 | } |
945 | ||
946 | /*-------------------------------------------------------------------------*/ | |
947 | ||
948 | /* prepare all TDs of a transfer */ | |
949 | ||
c5613df5 HG |
950 | static void td_submit_job(ohci_t *ohci, struct usb_device *dev, |
951 | unsigned long pipe, void *buffer, int transfer_len, | |
6f5794a6 RB |
952 | struct devrequest *setup, urb_priv_t *urb, |
953 | int interval) | |
3e326ece | 954 | { |
3e326ece MK |
955 | int data_len = transfer_len; |
956 | void *data; | |
957 | int cnt = 0; | |
958 | __u32 info = 0; | |
959 | unsigned int toggle = 0; | |
960 | ||
8d005ef8 HG |
961 | flush_dcache_buffer(buffer, data_len); |
962 | ||
6f5794a6 | 963 | /* OHCI handles the DATA-toggles itself, we just use the USB-toggle |
3450a859 | 964 | * bits for resetting */ |
6f5794a6 | 965 | if (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) { |
3e326ece MK |
966 | toggle = TD_T_TOGGLE; |
967 | } else { | |
968 | toggle = TD_T_DATA0; | |
6f5794a6 RB |
969 | usb_settoggle(dev, usb_pipeendpoint(pipe), |
970 | usb_pipeout(pipe), 1); | |
3e326ece MK |
971 | } |
972 | urb->td_cnt = 0; | |
973 | if (data_len) | |
974 | data = buffer; | |
975 | else | |
976 | data = 0; | |
977 | ||
6f5794a6 | 978 | switch (usb_pipetype(pipe)) { |
3e326ece | 979 | case PIPE_BULK: |
6f5794a6 | 980 | info = usb_pipeout(pipe)? |
3e326ece | 981 | TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ; |
6f5794a6 RB |
982 | while (data_len > 4096) { |
983 | td_fill(ohci, info | (cnt? TD_T_TOGGLE:toggle), | |
984 | data, 4096, dev, cnt, urb); | |
3e326ece MK |
985 | data += 4096; data_len -= 4096; cnt++; |
986 | } | |
6f5794a6 | 987 | info = usb_pipeout(pipe)? |
3e326ece | 988 | TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ; |
6f5794a6 RB |
989 | td_fill(ohci, info | (cnt? TD_T_TOGGLE:toggle), data, |
990 | data_len, dev, cnt, urb); | |
3e326ece MK |
991 | cnt++; |
992 | ||
6f5794a6 RB |
993 | if (!ohci->sleeping) { |
994 | /* start bulk list */ | |
a5496a18 | 995 | ohci_writel(OHCI_BLF, &ohci->regs->cmdstatus); |
6f5794a6 | 996 | } |
3e326ece MK |
997 | break; |
998 | ||
999 | case PIPE_CONTROL: | |
6f5794a6 | 1000 | /* Setup phase */ |
3e326ece | 1001 | info = TD_CC | TD_DP_SETUP | TD_T_DATA0; |
8d005ef8 | 1002 | flush_dcache_buffer(setup, 8); |
6f5794a6 RB |
1003 | td_fill(ohci, info, setup, 8, dev, cnt++, urb); |
1004 | ||
1005 | /* Optional Data phase */ | |
3e326ece | 1006 | if (data_len > 0) { |
6f5794a6 RB |
1007 | info = usb_pipeout(pipe)? |
1008 | TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : | |
1009 | TD_CC | TD_R | TD_DP_IN | TD_T_DATA1; | |
3e326ece | 1010 | /* NOTE: mishandles transfers >8K, some >4K */ |
6f5794a6 RB |
1011 | td_fill(ohci, info, data, data_len, dev, cnt++, urb); |
1012 | } | |
1013 | ||
1014 | /* Status phase */ | |
cae01cb2 | 1015 | info = (usb_pipeout(pipe) || data_len == 0) ? |
6f5794a6 RB |
1016 | TD_CC | TD_DP_IN | TD_T_DATA1: |
1017 | TD_CC | TD_DP_OUT | TD_T_DATA1; | |
1018 | td_fill(ohci, info, data, 0, dev, cnt++, urb); | |
1019 | ||
1020 | if (!ohci->sleeping) { | |
1021 | /* start Control list */ | |
a5496a18 | 1022 | ohci_writel(OHCI_CLF, &ohci->regs->cmdstatus); |
3e326ece | 1023 | } |
3e326ece | 1024 | break; |
4dae14ce ZW |
1025 | |
1026 | case PIPE_INTERRUPT: | |
6f5794a6 | 1027 | info = usb_pipeout(urb->pipe)? |
4dae14ce ZW |
1028 | TD_CC | TD_DP_OUT | toggle: |
1029 | TD_CC | TD_R | TD_DP_IN | toggle; | |
6f5794a6 | 1030 | td_fill(ohci, info, data, data_len, dev, cnt++, urb); |
4dae14ce | 1031 | break; |
3e326ece MK |
1032 | } |
1033 | if (urb->length != cnt) | |
1034 | dbg("TD LENGTH %d != CNT %d", urb->length, cnt); | |
1035 | } | |
1036 | ||
1037 | /*-------------------------------------------------------------------------* | |
1038 | * Done List handling functions | |
1039 | *-------------------------------------------------------------------------*/ | |
1040 | ||
3e326ece MK |
1041 | /* calculate the transfer length and update the urb */ |
1042 | ||
6f5794a6 | 1043 | static void dl_transfer_length(td_t *td) |
3e326ece | 1044 | { |
6bc52ef3 | 1045 | __u32 tdBE, tdCBP; |
4dae14ce | 1046 | urb_priv_t *lurb_priv = td->ed->purb; |
3e326ece | 1047 | |
6f5794a6 RB |
1048 | tdBE = m32_swap(td->hwBE); |
1049 | tdCBP = m32_swap(td->hwCBP); | |
3e326ece | 1050 | |
48867208 | 1051 | if (!(usb_pipecontrol(lurb_priv->pipe) && |
3e326ece MK |
1052 | ((td->index == 0) || (td->index == lurb_priv->length - 1)))) { |
1053 | if (tdBE != 0) { | |
1054 | if (td->hwCBP == 0) | |
1055 | lurb_priv->actual_length += tdBE - td->data + 1; | |
1056 | else | |
1057 | lurb_priv->actual_length += tdCBP - td->data; | |
1058 | } | |
1059 | } | |
1060 | } | |
1061 | ||
1062 | /*-------------------------------------------------------------------------*/ | |
6f5794a6 RB |
1063 | static void check_status(td_t *td_list) |
1064 | { | |
1065 | urb_priv_t *lurb_priv = td_list->ed->purb; | |
1066 | int urb_len = lurb_priv->length; | |
1067 | __u32 *phwHeadP = &td_list->ed->hwHeadP; | |
1068 | int cc; | |
1069 | ||
1070 | cc = TD_CC_GET(m32_swap(td_list->hwINFO)); | |
1071 | if (cc) { | |
1072 | err(" USB-error: %s (%x)", cc_to_string[cc], cc); | |
1073 | ||
8d005ef8 | 1074 | invalidate_dcache_ed(td_list->ed); |
6f5794a6 RB |
1075 | if (*phwHeadP & m32_swap(0x1)) { |
1076 | if (lurb_priv && | |
1077 | ((td_list->index + 1) < urb_len)) { | |
1078 | *phwHeadP = | |
1079 | (lurb_priv->td[urb_len - 1]->hwNextTD &\ | |
1080 | m32_swap(0xfffffff0)) | | |
1081 | (*phwHeadP & m32_swap(0x2)); | |
1082 | ||
1083 | lurb_priv->td_cnt += urb_len - | |
1084 | td_list->index - 1; | |
1085 | } else | |
1086 | *phwHeadP &= m32_swap(0xfffffff2); | |
8d005ef8 | 1087 | flush_dcache_ed(td_list->ed); |
6f5794a6 | 1088 | } |
6f5794a6 RB |
1089 | } |
1090 | } | |
3e326ece MK |
1091 | |
1092 | /* replies to the request have to be on a FIFO basis so | |
1093 | * we reverse the reversed done-list */ | |
6f5794a6 | 1094 | static td_t *dl_reverse_done_list(ohci_t *ohci) |
3e326ece | 1095 | { |
57faca19 | 1096 | uintptr_t td_list_hc; |
3e326ece MK |
1097 | td_t *td_rev = NULL; |
1098 | td_t *td_list = NULL; | |
3e326ece | 1099 | |
8d005ef8 | 1100 | invalidate_dcache_hcca(ohci->hcca); |
6f5794a6 | 1101 | td_list_hc = m32_swap(ohci->hcca->done_head) & 0xfffffff0; |
3e326ece | 1102 | ohci->hcca->done_head = 0; |
8d005ef8 | 1103 | flush_dcache_hcca(ohci->hcca); |
3e326ece MK |
1104 | |
1105 | while (td_list_hc) { | |
1106 | td_list = (td_t *)td_list_hc; | |
8d005ef8 | 1107 | invalidate_dcache_td(td_list); |
6f5794a6 | 1108 | check_status(td_list); |
3e326ece MK |
1109 | td_list->next_dl_td = td_rev; |
1110 | td_rev = td_list; | |
6f5794a6 | 1111 | td_list_hc = m32_swap(td_list->hwNextTD) & 0xfffffff0; |
3e326ece MK |
1112 | } |
1113 | return td_list; | |
1114 | } | |
1115 | ||
6f5794a6 | 1116 | /*-------------------------------------------------------------------------*/ |
3e326ece MK |
1117 | /*-------------------------------------------------------------------------*/ |
1118 | ||
6f5794a6 RB |
1119 | static void finish_urb(ohci_t *ohci, urb_priv_t *urb, int status) |
1120 | { | |
1121 | if ((status & (ED_OPER | ED_UNLINK)) && (urb->state != URB_DEL)) | |
47976d2c | 1122 | urb->finished = 1; |
6f5794a6 RB |
1123 | else |
1124 | dbg("finish_urb: strange.., ED state %x, \n", status); | |
1125 | } | |
1126 | ||
1127 | /* | |
1128 | * Used to take back a TD from the host controller. This would normally be | |
1129 | * called from within dl_done_list, however it may be called directly if the | |
1130 | * HC no longer sees the TD and it has not appeared on the donelist (after | |
1131 | * two frames). This bug has been observed on ZF Micro systems. | |
1132 | */ | |
1133 | static int takeback_td(ohci_t *ohci, td_t *td_list) | |
3e326ece | 1134 | { |
3e326ece | 1135 | ed_t *ed; |
6f5794a6 | 1136 | int cc; |
3e326ece MK |
1137 | int stat = 0; |
1138 | /* urb_t *urb; */ | |
1139 | urb_priv_t *lurb_priv; | |
1140 | __u32 tdINFO, edHeadP, edTailP; | |
1141 | ||
8d005ef8 | 1142 | invalidate_dcache_td(td_list); |
6f5794a6 | 1143 | tdINFO = m32_swap(td_list->hwINFO); |
3e326ece | 1144 | |
6f5794a6 RB |
1145 | ed = td_list->ed; |
1146 | lurb_priv = ed->purb; | |
3e326ece | 1147 | |
6f5794a6 | 1148 | dl_transfer_length(td_list); |
3e326ece | 1149 | |
6f5794a6 | 1150 | lurb_priv->td_cnt++; |
3e326ece | 1151 | |
6f5794a6 RB |
1152 | /* error code of transfer */ |
1153 | cc = TD_CC_GET(tdINFO); | |
1154 | if (cc) { | |
1155 | err("USB-error: %s (%x)", cc_to_string[cc], cc); | |
1156 | stat = cc_to_error[cc]; | |
1157 | } | |
ae79f606 | 1158 | |
6f5794a6 RB |
1159 | /* see if this done list makes for all TD's of current URB, |
1160 | * and mark the URB finished if so */ | |
1161 | if (lurb_priv->td_cnt == lurb_priv->length) | |
1162 | finish_urb(ohci, lurb_priv, ed->state); | |
1163 | ||
1164 | dbg("dl_done_list: processing TD %x, len %x\n", | |
1165 | lurb_priv->td_cnt, lurb_priv->length); | |
1166 | ||
48867208 | 1167 | if (ed->state != ED_NEW && (!usb_pipeint(lurb_priv->pipe))) { |
8d005ef8 | 1168 | invalidate_dcache_ed(ed); |
6f5794a6 RB |
1169 | edHeadP = m32_swap(ed->hwHeadP) & 0xfffffff0; |
1170 | edTailP = m32_swap(ed->hwTailP); | |
1171 | ||
1172 | /* unlink eds if they are not busy */ | |
1173 | if ((edHeadP == edTailP) && (ed->state == ED_OPER)) | |
1174 | ep_unlink(ohci, ed); | |
1175 | } | |
1176 | return stat; | |
1177 | } | |
3e326ece | 1178 | |
6f5794a6 RB |
1179 | static int dl_done_list(ohci_t *ohci) |
1180 | { | |
1181 | int stat = 0; | |
1182 | td_t *td_list = dl_reverse_done_list(ohci); | |
1183 | ||
1184 | while (td_list) { | |
1185 | td_t *td_next = td_list->next_dl_td; | |
1186 | stat = takeback_td(ohci, td_list); | |
1187 | td_list = td_next; | |
3e326ece MK |
1188 | } |
1189 | return stat; | |
1190 | } | |
1191 | ||
1192 | /*-------------------------------------------------------------------------* | |
1193 | * Virtual Root Hub | |
1194 | *-------------------------------------------------------------------------*/ | |
1195 | ||
eb838e7d | 1196 | #include <usbroothubdes.h> |
3e326ece MK |
1197 | |
1198 | /* Hub class-specific descriptor is constructed dynamically */ | |
1199 | ||
3e326ece MK |
1200 | /*-------------------------------------------------------------------------*/ |
1201 | ||
1202 | #define OK(x) len = (x); break | |
1203 | #ifdef DEBUG | |
a5496a18 | 1204 | #define WR_RH_STAT(x) {info("WR:status %#8x", (x)); ohci_writel((x), \ |
c5613df5 | 1205 | &ohci->regs->roothub.status); } |
6f5794a6 | 1206 | #define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, \ |
c5613df5 | 1207 | (x)); ohci_writel((x), &ohci->regs->roothub.portstatus[wIndex-1]); } |
3e326ece | 1208 | #else |
c5613df5 | 1209 | #define WR_RH_STAT(x) ohci_writel((x), &ohci->regs->roothub.status) |
a5496a18 | 1210 | #define WR_RH_PORTSTAT(x) ohci_writel((x), \ |
c5613df5 | 1211 | &ohci->regs->roothub.portstatus[wIndex-1]) |
3e326ece | 1212 | #endif |
c5613df5 HG |
1213 | #define RD_RH_STAT roothub_status(ohci) |
1214 | #define RD_RH_PORTSTAT roothub_portstatus(ohci, wIndex-1) | |
3e326ece MK |
1215 | |
1216 | /* request to virtual root hub */ | |
1217 | ||
1218 | int rh_check_port_status(ohci_t *controller) | |
1219 | { | |
1220 | __u32 temp, ndp, i; | |
1221 | int res; | |
1222 | ||
1223 | res = -1; | |
6f5794a6 | 1224 | temp = roothub_a(controller); |
3e326ece MK |
1225 | ndp = (temp & RH_A_NDP); |
1226 | #ifdef CONFIG_AT91C_PQFP_UHPBUG | |
1227 | ndp = (ndp == 2) ? 1:0; | |
1228 | #endif | |
1229 | for (i = 0; i < ndp; i++) { | |
6f5794a6 | 1230 | temp = roothub_portstatus(controller, i); |
3e326ece MK |
1231 | /* check for a device disconnect */ |
1232 | if (((temp & (RH_PS_PESC | RH_PS_CSC)) == | |
1233 | (RH_PS_PESC | RH_PS_CSC)) && | |
1234 | ((temp & RH_PS_CCS) == 0)) { | |
1235 | res = i; | |
1236 | break; | |
1237 | } | |
1238 | } | |
1239 | return res; | |
1240 | } | |
1241 | ||
c5613df5 HG |
1242 | static int ohci_submit_rh_msg(ohci_t *ohci, struct usb_device *dev, |
1243 | unsigned long pipe, void *buffer, int transfer_len, | |
1244 | struct devrequest *cmd) | |
3e326ece | 1245 | { |
6f5794a6 | 1246 | void *data = buffer; |
3e326ece MK |
1247 | int leni = transfer_len; |
1248 | int len = 0; | |
1249 | int stat = 0; | |
3e326ece MK |
1250 | __u16 bmRType_bReq; |
1251 | __u16 wValue; | |
1252 | __u16 wIndex; | |
1253 | __u16 wLength; | |
f1273f11 | 1254 | ALLOC_ALIGN_BUFFER(__u8, databuf, 16, sizeof(u32)); |
5f6aa03f | 1255 | |
3e326ece | 1256 | #ifdef DEBUG |
c5613df5 | 1257 | pkt_print(ohci, NULL, dev, pipe, buffer, transfer_len, |
6f5794a6 | 1258 | cmd, "SUB(rh)", usb_pipein(pipe)); |
3e326ece | 1259 | #else |
8f761f02 | 1260 | ohci_mdelay(1); |
3e326ece | 1261 | #endif |
48867208 | 1262 | if (usb_pipeint(pipe)) { |
3e326ece MK |
1263 | info("Root-Hub submit IRQ: NOT implemented"); |
1264 | return 0; | |
1265 | } | |
1266 | ||
1267 | bmRType_bReq = cmd->requesttype | (cmd->request << 8); | |
6f5794a6 RB |
1268 | wValue = le16_to_cpu(cmd->value); |
1269 | wIndex = le16_to_cpu(cmd->index); | |
1270 | wLength = le16_to_cpu(cmd->length); | |
3e326ece MK |
1271 | |
1272 | info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x", | |
1273 | dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength); | |
1274 | ||
1275 | switch (bmRType_bReq) { | |
1276 | /* Request Destination: | |
1277 | without flags: Device, | |
1278 | RH_INTERFACE: interface, | |
1279 | RH_ENDPOINT: endpoint, | |
1280 | RH_CLASS means HUB here, | |
1281 | RH_OTHER | RH_CLASS almost ever means HUB_PORT here | |
1282 | */ | |
1283 | ||
1284 | case RH_GET_STATUS: | |
f1273f11 | 1285 | *(u16 *)databuf = cpu_to_le16(1); |
6f5794a6 | 1286 | OK(2); |
3e326ece | 1287 | case RH_GET_STATUS | RH_INTERFACE: |
f1273f11 | 1288 | *(u16 *)databuf = cpu_to_le16(0); |
6f5794a6 | 1289 | OK(2); |
3e326ece | 1290 | case RH_GET_STATUS | RH_ENDPOINT: |
f1273f11 | 1291 | *(u16 *)databuf = cpu_to_le16(0); |
6f5794a6 | 1292 | OK(2); |
3e326ece | 1293 | case RH_GET_STATUS | RH_CLASS: |
f1273f11 | 1294 | *(u32 *)databuf = cpu_to_le32( |
3e326ece | 1295 | RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE)); |
6f5794a6 | 1296 | OK(4); |
3e326ece | 1297 | case RH_GET_STATUS | RH_OTHER | RH_CLASS: |
f1273f11 | 1298 | *(u32 *)databuf = cpu_to_le32(RD_RH_PORTSTAT); |
6f5794a6 | 1299 | OK(4); |
3e326ece MK |
1300 | |
1301 | case RH_CLEAR_FEATURE | RH_ENDPOINT: | |
1302 | switch (wValue) { | |
6f5794a6 RB |
1303 | case (RH_ENDPOINT_STALL): |
1304 | OK(0); | |
3e326ece MK |
1305 | } |
1306 | break; | |
1307 | ||
1308 | case RH_CLEAR_FEATURE | RH_CLASS: | |
1309 | switch (wValue) { | |
6f5794a6 RB |
1310 | case RH_C_HUB_LOCAL_POWER: |
1311 | OK(0); | |
1312 | case (RH_C_HUB_OVER_CURRENT): | |
1313 | WR_RH_STAT(RH_HS_OCIC); | |
1314 | OK(0); | |
3e326ece MK |
1315 | } |
1316 | break; | |
1317 | ||
1318 | case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS: | |
1319 | switch (wValue) { | |
6f5794a6 RB |
1320 | case (RH_PORT_ENABLE): WR_RH_PORTSTAT(RH_PS_CCS); OK(0); |
1321 | case (RH_PORT_SUSPEND): WR_RH_PORTSTAT(RH_PS_POCI); OK(0); | |
1322 | case (RH_PORT_POWER): WR_RH_PORTSTAT(RH_PS_LSDA); OK(0); | |
1323 | case (RH_C_PORT_CONNECTION): WR_RH_PORTSTAT(RH_PS_CSC); OK(0); | |
1324 | case (RH_C_PORT_ENABLE): WR_RH_PORTSTAT(RH_PS_PESC); OK(0); | |
1325 | case (RH_C_PORT_SUSPEND): WR_RH_PORTSTAT(RH_PS_PSSC); OK(0); | |
1326 | case (RH_C_PORT_OVER_CURRENT):WR_RH_PORTSTAT(RH_PS_OCIC); OK(0); | |
1327 | case (RH_C_PORT_RESET): WR_RH_PORTSTAT(RH_PS_PRSC); OK(0); | |
3e326ece MK |
1328 | } |
1329 | break; | |
1330 | ||
1331 | case RH_SET_FEATURE | RH_OTHER | RH_CLASS: | |
1332 | switch (wValue) { | |
6f5794a6 RB |
1333 | case (RH_PORT_SUSPEND): |
1334 | WR_RH_PORTSTAT(RH_PS_PSS); OK(0); | |
1335 | case (RH_PORT_RESET): /* BUG IN HUP CODE *********/ | |
1336 | if (RD_RH_PORTSTAT & RH_PS_CCS) | |
1337 | WR_RH_PORTSTAT(RH_PS_PRS); | |
1338 | OK(0); | |
1339 | case (RH_PORT_POWER): | |
1340 | WR_RH_PORTSTAT(RH_PS_PPS); | |
6f5794a6 RB |
1341 | OK(0); |
1342 | case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/ | |
1343 | if (RD_RH_PORTSTAT & RH_PS_CCS) | |
1344 | WR_RH_PORTSTAT(RH_PS_PES); | |
1345 | OK(0); | |
3e326ece MK |
1346 | } |
1347 | break; | |
1348 | ||
6f5794a6 | 1349 | case RH_SET_ADDRESS: |
c5613df5 | 1350 | ohci->rh.devnum = wValue; |
6f5794a6 | 1351 | OK(0); |
3e326ece MK |
1352 | |
1353 | case RH_GET_DESCRIPTOR: | |
1354 | switch ((wValue & 0xff00) >> 8) { | |
6f5794a6 RB |
1355 | case (0x01): /* device descriptor */ |
1356 | len = min_t(unsigned int, | |
1357 | leni, | |
1358 | min_t(unsigned int, | |
1359 | sizeof(root_hub_dev_des), | |
1360 | wLength)); | |
f1273f11 | 1361 | databuf = root_hub_dev_des; OK(len); |
6f5794a6 RB |
1362 | case (0x02): /* configuration descriptor */ |
1363 | len = min_t(unsigned int, | |
1364 | leni, | |
1365 | min_t(unsigned int, | |
1366 | sizeof(root_hub_config_des), | |
1367 | wLength)); | |
f1273f11 | 1368 | databuf = root_hub_config_des; OK(len); |
6f5794a6 RB |
1369 | case (0x03): /* string descriptors */ |
1370 | if (wValue == 0x0300) { | |
3e326ece | 1371 | len = min_t(unsigned int, |
6f5794a6 RB |
1372 | leni, |
1373 | min_t(unsigned int, | |
1374 | sizeof(root_hub_str_index0), | |
1375 | wLength)); | |
f1273f11 | 1376 | databuf = root_hub_str_index0; |
6f5794a6 | 1377 | OK(len); |
3e326ece | 1378 | } |
6f5794a6 RB |
1379 | if (wValue == 0x0301) { |
1380 | len = min_t(unsigned int, | |
1381 | leni, | |
1382 | min_t(unsigned int, | |
1383 | sizeof(root_hub_str_index1), | |
1384 | wLength)); | |
f1273f11 | 1385 | databuf = root_hub_str_index1; |
6f5794a6 RB |
1386 | OK(len); |
1387 | } | |
1388 | default: | |
1389 | stat = USB_ST_STALLED; | |
3e326ece MK |
1390 | } |
1391 | break; | |
1392 | ||
1393 | case RH_GET_DESCRIPTOR | RH_CLASS: | |
1394 | { | |
c5613df5 | 1395 | __u32 temp = roothub_a(ohci); |
3e326ece | 1396 | |
f1273f11 TK |
1397 | databuf[0] = 9; /* min length; */ |
1398 | databuf[1] = 0x29; | |
1399 | databuf[2] = temp & RH_A_NDP; | |
3e326ece | 1400 | #ifdef CONFIG_AT91C_PQFP_UHPBUG |
f1273f11 | 1401 | databuf[2] = (databuf[2] == 2) ? 1 : 0; |
3e326ece | 1402 | #endif |
f1273f11 | 1403 | databuf[3] = 0; |
3e326ece | 1404 | if (temp & RH_A_PSM) /* per-port power switching? */ |
f1273f11 | 1405 | databuf[3] |= 0x1; |
3e326ece | 1406 | if (temp & RH_A_NOCP) /* no overcurrent reporting? */ |
f1273f11 | 1407 | databuf[3] |= 0x10; |
6f5794a6 | 1408 | else if (temp & RH_A_OCPM)/* per-port overcurrent reporting? */ |
f1273f11 | 1409 | databuf[3] |= 0x8; |
3e326ece | 1410 | |
f1273f11 TK |
1411 | databuf[4] = 0; |
1412 | databuf[5] = (temp & RH_A_POTPGT) >> 24; | |
1413 | databuf[6] = 0; | |
c5613df5 | 1414 | temp = roothub_b(ohci); |
f1273f11 TK |
1415 | databuf[7] = temp & RH_B_DR; |
1416 | if (databuf[2] < 7) { | |
1417 | databuf[8] = 0xff; | |
3e326ece | 1418 | } else { |
f1273f11 TK |
1419 | databuf[0] += 2; |
1420 | databuf[8] = (temp & RH_B_DR) >> 8; | |
1421 | databuf[10] = databuf[9] = 0xff; | |
3e326ece MK |
1422 | } |
1423 | ||
1424 | len = min_t(unsigned int, leni, | |
f1273f11 | 1425 | min_t(unsigned int, databuf[0], wLength)); |
6f5794a6 | 1426 | OK(len); |
3e326ece MK |
1427 | } |
1428 | ||
5f6aa03f | 1429 | case RH_GET_CONFIGURATION: |
f1273f11 | 1430 | databuf[0] = 0x01; |
5f6aa03f | 1431 | OK(1); |
3e326ece | 1432 | |
5f6aa03f MV |
1433 | case RH_SET_CONFIGURATION: |
1434 | WR_RH_STAT(0x10000); | |
1435 | OK(0); | |
3e326ece MK |
1436 | |
1437 | default: | |
6f5794a6 | 1438 | dbg("unsupported root hub command"); |
3e326ece MK |
1439 | stat = USB_ST_STALLED; |
1440 | } | |
1441 | ||
1442 | #ifdef DEBUG | |
c5613df5 | 1443 | ohci_dump_roothub(ohci, 1); |
3e326ece | 1444 | #else |
8f761f02 | 1445 | ohci_mdelay(1); |
3e326ece MK |
1446 | #endif |
1447 | ||
1448 | len = min_t(int, len, leni); | |
f1273f11 TK |
1449 | if (data != databuf) |
1450 | memcpy(data, databuf, len); | |
3e326ece MK |
1451 | dev->act_len = len; |
1452 | dev->status = stat; | |
1453 | ||
1454 | #ifdef DEBUG | |
c5613df5 | 1455 | pkt_print(ohci, NULL, dev, pipe, buffer, |
6f5794a6 | 1456 | transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/); |
3e326ece | 1457 | #else |
8f761f02 | 1458 | ohci_mdelay(1); |
3e326ece MK |
1459 | #endif |
1460 | ||
1461 | return stat; | |
1462 | } | |
1463 | ||
1464 | /*-------------------------------------------------------------------------*/ | |
1465 | ||
44dbc330 HG |
1466 | static ohci_dev_t *ohci_get_ohci_dev(ohci_t *ohci, int devnum, int intr) |
1467 | { | |
1468 | int i; | |
1469 | ||
1470 | if (!intr) | |
1471 | return &ohci->ohci_dev; | |
1472 | ||
1473 | /* First see if we already have an ohci_dev for this dev. */ | |
1474 | for (i = 0; i < NUM_INT_DEVS; i++) { | |
1475 | if (ohci->int_dev[i].devnum == devnum) | |
1476 | return &ohci->int_dev[i]; | |
1477 | } | |
1478 | ||
1479 | /* If not then find a free one. */ | |
1480 | for (i = 0; i < NUM_INT_DEVS; i++) { | |
1481 | if (ohci->int_dev[i].devnum == -1) { | |
1482 | ohci->int_dev[i].devnum = devnum; | |
1483 | return &ohci->int_dev[i]; | |
1484 | } | |
1485 | } | |
1486 | ||
1487 | printf("ohci: Error out of ohci_devs for interrupt endpoints\n"); | |
1488 | return NULL; | |
1489 | } | |
1490 | ||
3e326ece MK |
1491 | /* common code for handling submit messages - used for all but root hub */ |
1492 | /* accesses. */ | |
d563e62c HG |
1493 | static urb_priv_t *ohci_alloc_urb(struct usb_device *dev, unsigned long pipe, |
1494 | void *buffer, int transfer_len, int interval) | |
1495 | { | |
1496 | urb_priv_t *urb; | |
1497 | ||
1498 | urb = calloc(1, sizeof(urb_priv_t)); | |
1499 | if (!urb) { | |
1500 | printf("ohci: Error out of memory allocating urb\n"); | |
1501 | return NULL; | |
1502 | } | |
1503 | ||
1504 | urb->dev = dev; | |
1505 | urb->pipe = pipe; | |
1506 | urb->transfer_buffer = buffer; | |
1507 | urb->transfer_buffer_length = transfer_len; | |
1508 | urb->interval = interval; | |
1509 | ||
1510 | return urb; | |
1511 | } | |
1512 | ||
c5613df5 HG |
1513 | static int submit_common_msg(ohci_t *ohci, struct usb_device *dev, |
1514 | unsigned long pipe, void *buffer, int transfer_len, | |
1515 | struct devrequest *setup, int interval) | |
3e326ece MK |
1516 | { |
1517 | int stat = 0; | |
1518 | int maxsize = usb_maxpacket(dev, pipe); | |
1519 | int timeout; | |
4dae14ce | 1520 | urb_priv_t *urb; |
44dbc330 | 1521 | ohci_dev_t *ohci_dev; |
4dae14ce | 1522 | |
d563e62c HG |
1523 | urb = ohci_alloc_urb(dev, pipe, buffer, transfer_len, interval); |
1524 | if (!urb) | |
1525 | return -ENOMEM; | |
3e326ece | 1526 | |
3e326ece | 1527 | #ifdef DEBUG |
4dae14ce | 1528 | urb->actual_length = 0; |
c5613df5 | 1529 | pkt_print(ohci, urb, dev, pipe, buffer, transfer_len, |
6f5794a6 | 1530 | setup, "SUB", usb_pipein(pipe)); |
3e326ece | 1531 | #else |
8f761f02 | 1532 | ohci_mdelay(1); |
3e326ece MK |
1533 | #endif |
1534 | if (!maxsize) { | |
1535 | err("submit_common_message: pipesize for pipe %lx is zero", | |
1536 | pipe); | |
1537 | return -1; | |
1538 | } | |
1539 | ||
44dbc330 HG |
1540 | ohci_dev = ohci_get_ohci_dev(ohci, dev->devnum, usb_pipeint(pipe)); |
1541 | if (!ohci_dev) | |
1542 | return -ENOMEM; | |
1543 | ||
1544 | if (sohci_submit_job(ohci, ohci_dev, urb, setup) < 0) { | |
3e326ece MK |
1545 | err("sohci_submit_job failed"); |
1546 | return -1; | |
1547 | } | |
1548 | ||
ae3b770e | 1549 | #if 0 |
5b84dd67 | 1550 | mdelay(10); |
c5613df5 | 1551 | /* ohci_dump_status(ohci); */ |
ae3b770e | 1552 | #endif |
3e326ece | 1553 | |
96820a35 | 1554 | timeout = USB_TIMEOUT_MS(pipe); |
3e326ece MK |
1555 | |
1556 | /* wait for it to complete */ | |
1557 | for (;;) { | |
1558 | /* check whether the controller is done */ | |
c5613df5 | 1559 | stat = hc_interrupt(ohci); |
3e326ece MK |
1560 | if (stat < 0) { |
1561 | stat = USB_ST_CRC_ERR; | |
1562 | break; | |
1563 | } | |
ddf83a2f | 1564 | |
ddf83a2f MK |
1565 | /* NOTE: since we are not interrupt driven in U-Boot and always |
1566 | * handle only one URB at a time, we cannot assume the | |
1567 | * transaction finished on the first successful return from | |
1568 | * hc_interrupt().. unless the flag for current URB is set, | |
1569 | * meaning that all TD's to/from device got actually | |
1570 | * transferred and processed. If the current URB is not | |
1571 | * finished we need to re-iterate this loop so as | |
1572 | * hc_interrupt() gets called again as there needs to be some | |
1573 | * more TD's to process still */ | |
4dae14ce | 1574 | if ((stat >= 0) && (stat != 0xff) && (urb->finished)) { |
3e326ece MK |
1575 | /* 0xff is returned for an SF-interrupt */ |
1576 | break; | |
1577 | } | |
ddf83a2f | 1578 | |
3e326ece | 1579 | if (--timeout) { |
5b84dd67 | 1580 | mdelay(1); |
4dae14ce | 1581 | if (!urb->finished) |
6f5794a6 | 1582 | dbg("*"); |
4dae14ce | 1583 | |
3e326ece | 1584 | } else { |
fa5b9baa HG |
1585 | if (!usb_pipeint(pipe)) |
1586 | err("CTL:TIMEOUT "); | |
ddf83a2f | 1587 | dbg("submit_common_msg: TO status %x\n", stat); |
4dae14ce | 1588 | urb->finished = 1; |
3e326ece MK |
1589 | stat = USB_ST_CRC_ERR; |
1590 | break; | |
1591 | } | |
1592 | } | |
3e326ece MK |
1593 | |
1594 | dev->status = stat; | |
522c9564 | 1595 | dev->act_len = urb->actual_length; |
3e326ece | 1596 | |
8d005ef8 HG |
1597 | if (usb_pipein(pipe) && dev->status == 0 && dev->act_len) |
1598 | invalidate_dcache_buffer(buffer, dev->act_len); | |
1599 | ||
3e326ece | 1600 | #ifdef DEBUG |
c5613df5 | 1601 | pkt_print(ohci, urb, dev, pipe, buffer, transfer_len, |
6f5794a6 | 1602 | setup, "RET(ctlr)", usb_pipein(pipe)); |
3e326ece | 1603 | #else |
8f761f02 | 1604 | ohci_mdelay(1); |
3e326ece | 1605 | #endif |
47976d2c | 1606 | urb_free_priv(urb); |
3e326ece MK |
1607 | return 0; |
1608 | } | |
1609 | ||
bf495712 HG |
1610 | #define MAX_INT_QUEUESIZE 8 |
1611 | ||
1612 | struct int_queue { | |
1613 | int queuesize; | |
1614 | int curr_urb; | |
1615 | urb_priv_t *urb[MAX_INT_QUEUESIZE]; | |
1616 | }; | |
1617 | ||
1618 | static struct int_queue *_ohci_create_int_queue(ohci_t *ohci, | |
1619 | struct usb_device *udev, unsigned long pipe, int queuesize, | |
1620 | int elementsize, void *buffer, int interval) | |
1621 | { | |
1622 | struct int_queue *queue; | |
1623 | ohci_dev_t *ohci_dev; | |
1624 | int i; | |
1625 | ||
1626 | if (queuesize > MAX_INT_QUEUESIZE) | |
1627 | return NULL; | |
1628 | ||
1629 | ohci_dev = ohci_get_ohci_dev(ohci, udev->devnum, 1); | |
1630 | if (!ohci_dev) | |
1631 | return NULL; | |
1632 | ||
1633 | queue = malloc(sizeof(*queue)); | |
1634 | if (!queue) { | |
1635 | printf("ohci: Error out of memory allocating int queue\n"); | |
1636 | return NULL; | |
1637 | } | |
1638 | ||
1639 | for (i = 0; i < queuesize; i++) { | |
1640 | queue->urb[i] = ohci_alloc_urb(udev, pipe, | |
1641 | buffer + i * elementsize, | |
1642 | elementsize, interval); | |
1643 | if (!queue->urb[i]) | |
1644 | break; | |
1645 | ||
1646 | if (sohci_submit_job(ohci, ohci_dev, queue->urb[i], NULL)) { | |
1647 | printf("ohci: Error submitting int queue job\n"); | |
1648 | urb_free_priv(queue->urb[i]); | |
1649 | break; | |
1650 | } | |
1651 | } | |
1652 | if (i == 0) { | |
1653 | /* We did not succeed in submitting even 1 urb */ | |
1654 | free(queue); | |
1655 | return NULL; | |
1656 | } | |
1657 | ||
1658 | queue->queuesize = i; | |
1659 | queue->curr_urb = 0; | |
1660 | ||
1661 | return queue; | |
1662 | } | |
1663 | ||
1664 | static void *_ohci_poll_int_queue(ohci_t *ohci, struct usb_device *udev, | |
1665 | struct int_queue *queue) | |
1666 | { | |
1667 | if (queue->curr_urb == queue->queuesize) | |
1668 | return NULL; /* Queue depleted */ | |
1669 | ||
1670 | if (hc_interrupt(ohci) < 0) | |
1671 | return NULL; | |
1672 | ||
1673 | if (queue->urb[queue->curr_urb]->finished) { | |
1674 | void *ret = queue->urb[queue->curr_urb]->transfer_buffer; | |
1675 | queue->curr_urb++; | |
1676 | return ret; | |
1677 | } | |
1678 | ||
1679 | return NULL; | |
1680 | } | |
1681 | ||
1682 | static int _ohci_destroy_int_queue(ohci_t *ohci, struct usb_device *dev, | |
1683 | struct int_queue *queue) | |
1684 | { | |
1685 | int i; | |
1686 | ||
1687 | for (i = 0; i < queue->queuesize; i++) | |
1688 | urb_free_priv(queue->urb[i]); | |
1689 | ||
1690 | free(queue); | |
1691 | ||
1692 | return 0; | |
1693 | } | |
1694 | ||
58b4048f | 1695 | #ifndef CONFIG_DM_USB |
3e326ece MK |
1696 | /* submit routines called from usb.c */ |
1697 | int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, | |
1698 | int transfer_len) | |
1699 | { | |
1700 | info("submit_bulk_msg"); | |
c5613df5 HG |
1701 | return submit_common_msg(&gohci, dev, pipe, buffer, transfer_len, |
1702 | NULL, 0); | |
1703 | } | |
1704 | ||
1705 | int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, | |
1706 | int transfer_len, int interval) | |
1707 | { | |
1708 | info("submit_int_msg"); | |
1709 | return submit_common_msg(&gohci, dev, pipe, buffer, transfer_len, NULL, | |
1710 | interval); | |
3e326ece | 1711 | } |
bf495712 HG |
1712 | |
1713 | struct int_queue *create_int_queue(struct usb_device *dev, | |
1714 | unsigned long pipe, int queuesize, int elementsize, | |
1715 | void *buffer, int interval) | |
1716 | { | |
1717 | return _ohci_create_int_queue(&gohci, dev, pipe, queuesize, | |
1718 | elementsize, buffer, interval); | |
1719 | } | |
1720 | ||
1721 | void *poll_int_queue(struct usb_device *dev, struct int_queue *queue) | |
1722 | { | |
1723 | return _ohci_poll_int_queue(&gohci, dev, queue); | |
1724 | } | |
1725 | ||
1726 | int destroy_int_queue(struct usb_device *dev, struct int_queue *queue) | |
1727 | { | |
1728 | return _ohci_destroy_int_queue(&gohci, dev, queue); | |
1729 | } | |
58b4048f | 1730 | #endif |
3e326ece | 1731 | |
c5613df5 HG |
1732 | static int _ohci_submit_control_msg(ohci_t *ohci, struct usb_device *dev, |
1733 | unsigned long pipe, void *buffer, int transfer_len, | |
1734 | struct devrequest *setup) | |
3e326ece MK |
1735 | { |
1736 | int maxsize = usb_maxpacket(dev, pipe); | |
1737 | ||
1738 | info("submit_control_msg"); | |
1739 | #ifdef DEBUG | |
c5613df5 | 1740 | pkt_print(ohci, NULL, dev, pipe, buffer, transfer_len, |
6f5794a6 | 1741 | setup, "SUB", usb_pipein(pipe)); |
3e326ece | 1742 | #else |
8f761f02 | 1743 | ohci_mdelay(1); |
3e326ece MK |
1744 | #endif |
1745 | if (!maxsize) { | |
1746 | err("submit_control_message: pipesize for pipe %lx is zero", | |
1747 | pipe); | |
1748 | return -1; | |
1749 | } | |
c5613df5 HG |
1750 | if (((pipe >> 8) & 0x7f) == ohci->rh.devnum) { |
1751 | ohci->rh.dev = dev; | |
3e326ece | 1752 | /* root hub - redirect */ |
c5613df5 HG |
1753 | return ohci_submit_rh_msg(ohci, dev, pipe, buffer, |
1754 | transfer_len, setup); | |
3e326ece MK |
1755 | } |
1756 | ||
c5613df5 HG |
1757 | return submit_common_msg(ohci, dev, pipe, buffer, transfer_len, |
1758 | setup, 0); | |
3e326ece MK |
1759 | } |
1760 | ||
1761 | /*-------------------------------------------------------------------------* | |
1762 | * HC functions | |
1763 | *-------------------------------------------------------------------------*/ | |
1764 | ||
1765 | /* reset the HC and BUS */ | |
1766 | ||
6f5794a6 | 1767 | static int hc_reset(ohci_t *ohci) |
3e326ece | 1768 | { |
e90fb6af YT |
1769 | #ifdef CONFIG_PCI_EHCI_DEVNO |
1770 | pci_dev_t pdev; | |
1771 | #endif | |
3e326ece MK |
1772 | int timeout = 30; |
1773 | int smm_timeout = 50; /* 0,5 sec */ | |
1774 | ||
1775 | dbg("%s\n", __FUNCTION__); | |
1776 | ||
e90fb6af YT |
1777 | #ifdef CONFIG_PCI_EHCI_DEVNO |
1778 | /* | |
1779 | * Some multi-function controllers (e.g. ISP1562) allow root hub | |
1780 | * resetting via EHCI registers only. | |
1781 | */ | |
1782 | pdev = pci_find_devices(ehci_pci_ids, CONFIG_PCI_EHCI_DEVNO); | |
1783 | if (pdev != -1) { | |
1784 | u32 base; | |
1785 | int timeout = 1000; | |
1786 | ||
1787 | pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base); | |
a5496a18 BB |
1788 | base += EHCI_USBCMD_OFF; |
1789 | ohci_writel(ohci_readl(base) | EHCI_USBCMD_HCRESET, base); | |
e90fb6af | 1790 | |
a5496a18 | 1791 | while (ohci_readl(base) & EHCI_USBCMD_HCRESET) { |
e90fb6af YT |
1792 | if (timeout-- <= 0) { |
1793 | printf("USB RootHub reset timed out!"); | |
1794 | break; | |
1795 | } | |
1796 | udelay(1); | |
1797 | } | |
1798 | } else | |
1799 | printf("No EHCI func at %d index!\n", CONFIG_PCI_EHCI_DEVNO); | |
1800 | #endif | |
a5496a18 BB |
1801 | if (ohci_readl(&ohci->regs->control) & OHCI_CTRL_IR) { |
1802 | /* SMM owns the HC, request ownership */ | |
1803 | ohci_writel(OHCI_OCR, &ohci->regs->cmdstatus); | |
3e326ece | 1804 | info("USB HC TakeOver from SMM"); |
a5496a18 | 1805 | while (ohci_readl(&ohci->regs->control) & OHCI_CTRL_IR) { |
5b84dd67 | 1806 | mdelay(10); |
3e326ece MK |
1807 | if (--smm_timeout == 0) { |
1808 | err("USB HC TakeOver failed!"); | |
1809 | return -1; | |
1810 | } | |
1811 | } | |
1812 | } | |
1813 | ||
1814 | /* Disable HC interrupts */ | |
a5496a18 | 1815 | ohci_writel(OHCI_INTR_MIE, &ohci->regs->intrdisable); |
3e326ece MK |
1816 | |
1817 | dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;\n", | |
1818 | ohci->slot_name, | |
a5496a18 | 1819 | ohci_readl(&ohci->regs->control)); |
3e326ece MK |
1820 | |
1821 | /* Reset USB (needed by some controllers) */ | |
53e336e9 | 1822 | ohci->hc_control = 0; |
a5496a18 | 1823 | ohci_writel(ohci->hc_control, &ohci->regs->control); |
3e326ece MK |
1824 | |
1825 | /* HC Reset requires max 10 us delay */ | |
a5496a18 BB |
1826 | ohci_writel(OHCI_HCR, &ohci->regs->cmdstatus); |
1827 | while ((ohci_readl(&ohci->regs->cmdstatus) & OHCI_HCR) != 0) { | |
3e326ece MK |
1828 | if (--timeout == 0) { |
1829 | err("USB HC reset timed out!"); | |
1830 | return -1; | |
1831 | } | |
6f5794a6 | 1832 | udelay(1); |
3e326ece MK |
1833 | } |
1834 | return 0; | |
1835 | } | |
1836 | ||
1837 | /*-------------------------------------------------------------------------*/ | |
1838 | ||
1839 | /* Start an OHCI controller, set the BUS operational | |
1840 | * enable interrupts | |
1841 | * connect the virtual root hub */ | |
1842 | ||
6f5794a6 | 1843 | static int hc_start(ohci_t *ohci) |
3e326ece MK |
1844 | { |
1845 | __u32 mask; | |
1846 | unsigned int fminterval; | |
44dbc330 | 1847 | int i; |
3e326ece MK |
1848 | |
1849 | ohci->disabled = 1; | |
44dbc330 HG |
1850 | for (i = 0; i < NUM_INT_DEVS; i++) |
1851 | ohci->int_dev[i].devnum = -1; | |
3e326ece MK |
1852 | |
1853 | /* Tell the controller where the control and bulk lists are | |
1854 | * The lists are empty now. */ | |
1855 | ||
a5496a18 BB |
1856 | ohci_writel(0, &ohci->regs->ed_controlhead); |
1857 | ohci_writel(0, &ohci->regs->ed_bulkhead); | |
3e326ece | 1858 | |
57faca19 | 1859 | ohci_writel((uintptr_t)ohci->hcca, |
a5496a18 | 1860 | &ohci->regs->hcca); /* reset clears this */ |
3e326ece MK |
1861 | |
1862 | fminterval = 0x2edf; | |
a5496a18 | 1863 | ohci_writel((fminterval * 9) / 10, &ohci->regs->periodicstart); |
3e326ece | 1864 | fminterval |= ((((fminterval - 210) * 6) / 7) << 16); |
a5496a18 BB |
1865 | ohci_writel(fminterval, &ohci->regs->fminterval); |
1866 | ohci_writel(0x628, &ohci->regs->lsthresh); | |
3e326ece MK |
1867 | |
1868 | /* start controller operations */ | |
1869 | ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER; | |
1870 | ohci->disabled = 0; | |
a5496a18 | 1871 | ohci_writel(ohci->hc_control, &ohci->regs->control); |
3e326ece MK |
1872 | |
1873 | /* disable all interrupts */ | |
1874 | mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD | | |
1875 | OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC | | |
1876 | OHCI_INTR_OC | OHCI_INTR_MIE); | |
a5496a18 | 1877 | ohci_writel(mask, &ohci->regs->intrdisable); |
3e326ece MK |
1878 | /* clear all interrupts */ |
1879 | mask &= ~OHCI_INTR_MIE; | |
a5496a18 | 1880 | ohci_writel(mask, &ohci->regs->intrstatus); |
3e326ece MK |
1881 | /* Choose the interrupts we care about now - but w/o MIE */ |
1882 | mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO; | |
a5496a18 | 1883 | ohci_writel(mask, &ohci->regs->intrenable); |
3e326ece MK |
1884 | |
1885 | #ifdef OHCI_USE_NPS | |
1886 | /* required for AMD-756 and some Mac platforms */ | |
a5496a18 | 1887 | ohci_writel((roothub_a(ohci) | RH_A_NPS) & ~RH_A_PSM, |
3e326ece | 1888 | &ohci->regs->roothub.a); |
a5496a18 | 1889 | ohci_writel(RH_HS_LPSC, &ohci->regs->roothub.status); |
3e326ece MK |
1890 | #endif /* OHCI_USE_NPS */ |
1891 | ||
3e326ece MK |
1892 | /* connect the virtual root hub */ |
1893 | ohci->rh.devnum = 0; | |
1894 | ||
1895 | return 0; | |
1896 | } | |
1897 | ||
1898 | /*-------------------------------------------------------------------------*/ | |
1899 | ||
1900 | /* an interrupt happens */ | |
1901 | ||
c5613df5 | 1902 | static int hc_interrupt(ohci_t *ohci) |
3e326ece | 1903 | { |
3e326ece MK |
1904 | struct ohci_regs *regs = ohci->regs; |
1905 | int ints; | |
1906 | int stat = -1; | |
1907 | ||
8d005ef8 HG |
1908 | invalidate_dcache_hcca(ohci->hcca); |
1909 | ||
ddf83a2f | 1910 | if ((ohci->hcca->done_head != 0) && |
6f5794a6 | 1911 | !(m32_swap(ohci->hcca->done_head) & 0x01)) { |
ddf83a2f | 1912 | ints = OHCI_INTR_WDH; |
6f5794a6 | 1913 | } else { |
a5496a18 | 1914 | ints = ohci_readl(®s->intrstatus); |
6f5794a6 RB |
1915 | if (ints == ~(u32)0) { |
1916 | ohci->disabled++; | |
1917 | err("%s device removed!", ohci->slot_name); | |
1918 | return -1; | |
1919 | } else { | |
a5496a18 | 1920 | ints &= ohci_readl(®s->intrenable); |
6f5794a6 RB |
1921 | if (ints == 0) { |
1922 | dbg("hc_interrupt: returning..\n"); | |
1923 | return 0xff; | |
1924 | } | |
1925 | } | |
ddf83a2f | 1926 | } |
ae79f606 | 1927 | |
6f5794a6 RB |
1928 | /* dbg("Interrupt: %x frame: %x", ints, |
1929 | le16_to_cpu(ohci->hcca->frame_no)); */ | |
3e326ece | 1930 | |
6f5794a6 | 1931 | if (ints & OHCI_INTR_RHSC) |
ddf83a2f | 1932 | stat = 0xff; |
3e326ece MK |
1933 | |
1934 | if (ints & OHCI_INTR_UE) { | |
1935 | ohci->disabled++; | |
6f5794a6 | 1936 | err("OHCI Unrecoverable Error, controller usb-%s disabled", |
3e326ece MK |
1937 | ohci->slot_name); |
1938 | /* e.g. due to PCI Master/Target Abort */ | |
1939 | ||
1940 | #ifdef DEBUG | |
6f5794a6 | 1941 | ohci_dump(ohci, 1); |
3e326ece | 1942 | #else |
8f761f02 | 1943 | ohci_mdelay(1); |
3e326ece MK |
1944 | #endif |
1945 | /* FIXME: be optimistic, hope that bug won't repeat often. */ | |
1946 | /* Make some non-interrupt context restart the controller. */ | |
1947 | /* Count and limit the retries though; either hardware or */ | |
1948 | /* software errors can go forever... */ | |
6f5794a6 | 1949 | hc_reset(ohci); |
3e326ece MK |
1950 | return -1; |
1951 | } | |
1952 | ||
1953 | if (ints & OHCI_INTR_WDH) { | |
8f761f02 | 1954 | ohci_mdelay(1); |
a5496a18 BB |
1955 | ohci_writel(OHCI_INTR_WDH, ®s->intrdisable); |
1956 | (void)ohci_readl(®s->intrdisable); /* flush */ | |
c5613df5 | 1957 | stat = dl_done_list(ohci); |
a5496a18 BB |
1958 | ohci_writel(OHCI_INTR_WDH, ®s->intrenable); |
1959 | (void)ohci_readl(®s->intrdisable); /* flush */ | |
3e326ece MK |
1960 | } |
1961 | ||
1962 | if (ints & OHCI_INTR_SO) { | |
1963 | dbg("USB Schedule overrun\n"); | |
a5496a18 | 1964 | ohci_writel(OHCI_INTR_SO, ®s->intrenable); |
3e326ece MK |
1965 | stat = -1; |
1966 | } | |
1967 | ||
1968 | /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */ | |
1969 | if (ints & OHCI_INTR_SF) { | |
6f5794a6 | 1970 | unsigned int frame = m16_swap(ohci->hcca->frame_no) & 1; |
5b84dd67 | 1971 | mdelay(1); |
a5496a18 | 1972 | ohci_writel(OHCI_INTR_SF, ®s->intrdisable); |
3e326ece | 1973 | if (ohci->ed_rm_list[frame] != NULL) |
a5496a18 | 1974 | ohci_writel(OHCI_INTR_SF, ®s->intrenable); |
3e326ece MK |
1975 | stat = 0xff; |
1976 | } | |
1977 | ||
a5496a18 | 1978 | ohci_writel(ints, ®s->intrstatus); |
3e326ece MK |
1979 | return stat; |
1980 | } | |
1981 | ||
1982 | /*-------------------------------------------------------------------------*/ | |
1983 | ||
58b4048f HG |
1984 | #ifndef CONFIG_DM_USB |
1985 | ||
3e326ece MK |
1986 | /*-------------------------------------------------------------------------*/ |
1987 | ||
1988 | /* De-allocate all resources.. */ | |
1989 | ||
6f5794a6 | 1990 | static void hc_release_ohci(ohci_t *ohci) |
3e326ece | 1991 | { |
6f5794a6 | 1992 | dbg("USB HC release ohci usb-%s", ohci->slot_name); |
3e326ece MK |
1993 | |
1994 | if (!ohci->disabled) | |
6f5794a6 | 1995 | hc_reset(ohci); |
3e326ece MK |
1996 | } |
1997 | ||
1998 | /*-------------------------------------------------------------------------*/ | |
1999 | ||
2000 | /* | |
2001 | * low level initalisation routine, called from usb.c | |
2002 | */ | |
2003 | static char ohci_inited = 0; | |
2004 | ||
06d513ec | 2005 | int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) |
3e326ece | 2006 | { |
4dae14ce ZW |
2007 | #ifdef CONFIG_PCI_OHCI |
2008 | pci_dev_t pdev; | |
2009 | #endif | |
24e37645 | 2010 | |
6d0f6bcf | 2011 | #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT |
24e37645 | 2012 | /* cpu dependant init */ |
6f5794a6 | 2013 | if (usb_cpu_init()) |
3e326ece | 2014 | return -1; |
24e37645 | 2015 | #endif |
3e326ece | 2016 | |
6d0f6bcf | 2017 | #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT |
24e37645 | 2018 | /* board dependant init */ |
16297cfb | 2019 | if (board_usb_init(index, USB_INIT_HOST)) |
24e37645 MK |
2020 | return -1; |
2021 | #endif | |
6f5794a6 | 2022 | memset(&gohci, 0, sizeof(ohci_t)); |
3e326ece MK |
2023 | |
2024 | /* align the storage */ | |
2025 | if ((__u32)&ghcca[0] & 0xff) { | |
2026 | err("HCCA not aligned!!"); | |
2027 | return -1; | |
2028 | } | |
26548bb2 HG |
2029 | gohci.hcca = &ghcca[0]; |
2030 | info("aligned ghcca %p", gohci.hcca); | |
2031 | memset(gohci.hcca, 0, sizeof(struct ohci_hcca)); | |
3e326ece MK |
2032 | |
2033 | gohci.disabled = 1; | |
2034 | gohci.sleeping = 0; | |
2035 | gohci.irq = -1; | |
4dae14ce | 2036 | #ifdef CONFIG_PCI_OHCI |
477434c6 | 2037 | pdev = pci_find_devices(ohci_pci_ids, CONFIG_PCI_OHCI_DEVNO); |
4dae14ce ZW |
2038 | |
2039 | if (pdev != -1) { | |
2040 | u16 vid, did; | |
2041 | u32 base; | |
2042 | pci_read_config_word(pdev, PCI_VENDOR_ID, &vid); | |
2043 | pci_read_config_word(pdev, PCI_DEVICE_ID, &did); | |
2044 | printf("OHCI pci controller (%04x, %04x) found @(%d:%d:%d)\n", | |
2045 | vid, did, (pdev >> 16) & 0xff, | |
2046 | (pdev >> 11) & 0x1f, (pdev >> 8) & 0x7); | |
2047 | pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base); | |
2048 | printf("OHCI regs address 0x%08x\n", base); | |
2049 | gohci.regs = (struct ohci_regs *)base; | |
2050 | } else | |
2051 | return -1; | |
2052 | #else | |
6d0f6bcf | 2053 | gohci.regs = (struct ohci_regs *)CONFIG_SYS_USB_OHCI_REGS_BASE; |
4dae14ce | 2054 | #endif |
3e326ece MK |
2055 | |
2056 | gohci.flags = 0; | |
6d0f6bcf | 2057 | gohci.slot_name = CONFIG_SYS_USB_OHCI_SLOT_NAME; |
3e326ece MK |
2058 | |
2059 | if (hc_reset (&gohci) < 0) { | |
2060 | hc_release_ohci (&gohci); | |
2061 | err ("can't reset usb-%s", gohci.slot_name); | |
6d0f6bcf | 2062 | #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT |
24e37645 | 2063 | /* board dependant cleanup */ |
16297cfb | 2064 | board_usb_cleanup(index, USB_INIT_HOST); |
24e37645 MK |
2065 | #endif |
2066 | ||
6d0f6bcf | 2067 | #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT |
24e37645 | 2068 | /* cpu dependant cleanup */ |
ddf83a2f | 2069 | usb_cpu_init_fail(); |
24e37645 | 2070 | #endif |
3e326ece MK |
2071 | return -1; |
2072 | } | |
2073 | ||
6f5794a6 RB |
2074 | if (hc_start(&gohci) < 0) { |
2075 | err("can't start usb-%s", gohci.slot_name); | |
2076 | hc_release_ohci(&gohci); | |
3e326ece | 2077 | /* Initialization failed */ |
6d0f6bcf | 2078 | #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT |
24e37645 MK |
2079 | /* board dependant cleanup */ |
2080 | usb_board_stop(); | |
2081 | #endif | |
2082 | ||
6d0f6bcf | 2083 | #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT |
24e37645 MK |
2084 | /* cpu dependant cleanup */ |
2085 | usb_cpu_stop(); | |
2086 | #endif | |
3e326ece MK |
2087 | return -1; |
2088 | } | |
2089 | ||
2090 | #ifdef DEBUG | |
6f5794a6 | 2091 | ohci_dump(&gohci, 1); |
3e326ece | 2092 | #else |
8f761f02 | 2093 | ohci_mdelay(1); |
3e326ece MK |
2094 | #endif |
2095 | ohci_inited = 1; | |
2096 | return 0; | |
2097 | } | |
2098 | ||
c7e3b2b5 | 2099 | int usb_lowlevel_stop(int index) |
3e326ece MK |
2100 | { |
2101 | /* this gets called really early - before the controller has */ | |
2102 | /* even been initialized! */ | |
2103 | if (!ohci_inited) | |
2104 | return 0; | |
2105 | /* TODO release any interrupts, etc. */ | |
2106 | /* call hc_release_ohci() here ? */ | |
6f5794a6 | 2107 | hc_reset(&gohci); |
3e326ece | 2108 | |
6d0f6bcf | 2109 | #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT |
3e326ece | 2110 | /* board dependant cleanup */ |
6f5794a6 | 2111 | if (usb_board_stop()) |
3e326ece | 2112 | return -1; |
24e37645 MK |
2113 | #endif |
2114 | ||
6d0f6bcf | 2115 | #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT |
24e37645 | 2116 | /* cpu dependant cleanup */ |
6f5794a6 | 2117 | if (usb_cpu_stop()) |
24e37645 MK |
2118 | return -1; |
2119 | #endif | |
eba1f2fc RB |
2120 | /* This driver is no longer initialised. It needs a new low-level |
2121 | * init (board/cpu) before it can be used again. */ | |
2122 | ohci_inited = 0; | |
3e326ece MK |
2123 | return 0; |
2124 | } | |
c5613df5 HG |
2125 | |
2126 | int submit_control_msg(struct usb_device *dev, unsigned long pipe, | |
2127 | void *buffer, int transfer_len, struct devrequest *setup) | |
2128 | { | |
2129 | return _ohci_submit_control_msg(&gohci, dev, pipe, buffer, | |
2130 | transfer_len, setup); | |
2131 | } | |
58b4048f HG |
2132 | #endif |
2133 | ||
2134 | #ifdef CONFIG_DM_USB | |
2135 | static int ohci_submit_control_msg(struct udevice *dev, struct usb_device *udev, | |
2136 | unsigned long pipe, void *buffer, int length, | |
2137 | struct devrequest *setup) | |
2138 | { | |
2139 | ohci_t *ohci = dev_get_priv(usb_get_bus(dev)); | |
2140 | ||
2141 | return _ohci_submit_control_msg(ohci, udev, pipe, buffer, | |
2142 | length, setup); | |
2143 | } | |
2144 | ||
2145 | static int ohci_submit_bulk_msg(struct udevice *dev, struct usb_device *udev, | |
2146 | unsigned long pipe, void *buffer, int length) | |
2147 | { | |
2148 | ohci_t *ohci = dev_get_priv(usb_get_bus(dev)); | |
2149 | ||
2150 | return submit_common_msg(ohci, udev, pipe, buffer, length, NULL, 0); | |
2151 | } | |
2152 | ||
2153 | static int ohci_submit_int_msg(struct udevice *dev, struct usb_device *udev, | |
2154 | unsigned long pipe, void *buffer, int length, | |
2155 | int interval) | |
2156 | { | |
2157 | ohci_t *ohci = dev_get_priv(usb_get_bus(dev)); | |
2158 | ||
2159 | return submit_common_msg(ohci, udev, pipe, buffer, length, | |
2160 | NULL, interval); | |
2161 | } | |
2162 | ||
bf495712 HG |
2163 | static struct int_queue *ohci_create_int_queue(struct udevice *dev, |
2164 | struct usb_device *udev, unsigned long pipe, int queuesize, | |
2165 | int elementsize, void *buffer, int interval) | |
2166 | { | |
2167 | ohci_t *ohci = dev_get_priv(usb_get_bus(dev)); | |
2168 | ||
2169 | return _ohci_create_int_queue(ohci, udev, pipe, queuesize, elementsize, | |
2170 | buffer, interval); | |
2171 | } | |
2172 | ||
2173 | static void *ohci_poll_int_queue(struct udevice *dev, struct usb_device *udev, | |
2174 | struct int_queue *queue) | |
2175 | { | |
2176 | ohci_t *ohci = dev_get_priv(usb_get_bus(dev)); | |
2177 | ||
2178 | return _ohci_poll_int_queue(ohci, udev, queue); | |
2179 | } | |
2180 | ||
2181 | static int ohci_destroy_int_queue(struct udevice *dev, struct usb_device *udev, | |
2182 | struct int_queue *queue) | |
2183 | { | |
2184 | ohci_t *ohci = dev_get_priv(usb_get_bus(dev)); | |
2185 | ||
2186 | return _ohci_destroy_int_queue(ohci, udev, queue); | |
2187 | } | |
2188 | ||
58b4048f HG |
2189 | int ohci_register(struct udevice *dev, struct ohci_regs *regs) |
2190 | { | |
2191 | struct usb_bus_priv *priv = dev_get_uclass_priv(dev); | |
2192 | ohci_t *ohci = dev_get_priv(dev); | |
2193 | u32 reg; | |
2194 | ||
2195 | priv->desc_before_addr = true; | |
2196 | ||
2197 | ohci->regs = regs; | |
2198 | ohci->hcca = memalign(256, sizeof(struct ohci_hcca)); | |
2199 | if (!ohci->hcca) | |
2200 | return -ENOMEM; | |
2201 | memset(ohci->hcca, 0, sizeof(struct ohci_hcca)); | |
b748b24f | 2202 | flush_dcache_hcca(ohci->hcca); |
58b4048f HG |
2203 | |
2204 | if (hc_reset(ohci) < 0) | |
2205 | return -EIO; | |
2206 | ||
2207 | if (hc_start(ohci) < 0) | |
2208 | return -EIO; | |
2209 | ||
2210 | reg = ohci_readl(®s->revision); | |
2211 | printf("USB OHCI %x.%x\n", (reg >> 4) & 0xf, reg & 0xf); | |
2212 | ||
2213 | return 0; | |
2214 | } | |
2215 | ||
2216 | int ohci_deregister(struct udevice *dev) | |
2217 | { | |
2218 | ohci_t *ohci = dev_get_priv(dev); | |
2219 | ||
2220 | if (hc_reset(ohci) < 0) | |
2221 | return -EIO; | |
2222 | ||
2223 | free(ohci->hcca); | |
2224 | ||
2225 | return 0; | |
2226 | } | |
2227 | ||
2228 | struct dm_usb_ops ohci_usb_ops = { | |
2229 | .control = ohci_submit_control_msg, | |
2230 | .bulk = ohci_submit_bulk_msg, | |
2231 | .interrupt = ohci_submit_int_msg, | |
bf495712 HG |
2232 | .create_int_queue = ohci_create_int_queue, |
2233 | .poll_int_queue = ohci_poll_int_queue, | |
2234 | .destroy_int_queue = ohci_destroy_int_queue, | |
58b4048f HG |
2235 | }; |
2236 | ||
2237 | #endif |