[people/ms/u-boot.git] / drivers / usb / host / ohci-s3c24xx.h

/*
 * URB OHCI HCD (Host Controller Driver) for USB.
 *
 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
 * (C) Copyright 2000-2001 David Brownell <dbrownell@users.sourceforge.net>
 *
 * usb-ohci.h
 */


static int cc_to_error[16] = {

/* mapping of the OHCI CC status to error codes */
	/* No  Error  */ 0,
	/* CRC Error  */ USB_ST_CRC_ERR,
	/* Bit Stuff  */ USB_ST_BIT_ERR,
	/* Data Togg  */ USB_ST_CRC_ERR,
	/* Stall      */ USB_ST_STALLED,
	/* DevNotResp */ -1,
	/* PIDCheck   */ USB_ST_BIT_ERR,
	/* UnExpPID   */ USB_ST_BIT_ERR,
	/* DataOver   */ USB_ST_BUF_ERR,
	/* DataUnder  */ USB_ST_BUF_ERR,
	/* reservd    */ -1,
	/* reservd    */ -1,
	/* BufferOver */ USB_ST_BUF_ERR,
	/* BuffUnder  */ USB_ST_BUF_ERR,
	/* Not Access */ -1,
	/* Not Access */ -1
};

/* ED States */
#define ED_NEW		0x00
#define ED_UNLINK	0x01
#define ED_OPER		0x02
#define ED_DEL		0x04
#define ED_URB_DEL	0x08

/* usb_ohci_ed */
struct ed {
	__u32 hwINFO;
	__u32 hwTailP;
	__u32 hwHeadP;
	__u32 hwNextED;

	struct ed *ed_prev;
	__u8 int_period;
	__u8 int_branch;
	__u8 int_load;
	__u8 int_interval;
	__u8 state;
	__u8 type;
	__u16 last_iso;
	struct ed *ed_rm_list;

	struct usb_device *usb_dev;
	__u32 unused[3];
} __attribute__ ((aligned(16)));

/* TD info field */
#define TD_CC			0xf0000000
#define TD_CC_GET(td_p)		(((td_p) >> 28) & 0x0f)
#define TD_CC_SET(td_p, cc) \
	{(td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)}
#define TD_EC			0x0C000000
#define TD_T			0x03000000
#define TD_T_DATA0		0x02000000
#define TD_T_DATA1		0x03000000
#define TD_T_TOGGLE		0x00000000
#define TD_R			0x00040000
#define TD_DI			0x00E00000
#define TD_DI_SET(X)		(((X) & 0x07)<< 21)
#define TD_DP			0x00180000
#define TD_DP_SETUP		0x00000000
#define TD_DP_IN		0x00100000
#define TD_DP_OUT		0x00080000

#define TD_ISO			0x00010000
#define TD_DEL			0x00020000

/* CC Codes */
#define TD_CC_NOERROR		0x00
#define TD_CC_CRC		0x01
#define TD_CC_BITSTUFFING	0x02
#define TD_CC_DATATOGGLEM	0x03
#define TD_CC_STALL		0x04
#define TD_DEVNOTRESP		0x05
#define TD_PIDCHECKFAIL	0x06
#define TD_UNEXPECTEDPID	0x07
#define TD_DATAOVERRUN		0x08
#define TD_DATAUNDERRUN	0x09
#define TD_BUFFEROVERRUN	0x0C
#define TD_BUFFERUNDERRUN	0x0D
#define TD_NOTACCESSED		0x0F


#define MAXPSW 1

struct td {
	__u32 hwINFO;
	__u32 hwCBP;		/* Current Buffer Pointer */
	__u32 hwNextTD;		/* Next TD Pointer */
	__u32 hwBE;		/* Memory Buffer End Pointer */

	__u8 unused;
	__u8 index;
	struct ed *ed;
	struct td *next_dl_td;
	struct usb_device *usb_dev;
	int transfer_len;
	__u32 data;

	__u32 unused2[2];
} __attribute__ ((aligned(32)));

#define OHCI_ED_SKIP	(1 << 14)

/*
 * The HCCA (Host Controller Communications Area) is a 256 byte
 * structure defined in the OHCI spec. that the host controller is
 * told the base address of.  It must be 256-byte aligned.
 */

#define NUM_INTS 32		/* part of the OHCI standard */
struct ohci_hcca {
	__u32 int_table[NUM_INTS];	/* Interrupt ED table */
	__u16 frame_no;		/* current frame number */
	__u16 pad1;		/* set to 0 on each frame_no change */
	__u32 done_head;	/* info returned for an interrupt */
	u8 reserved_for_hc[116];
} __attribute__ ((aligned(256)));

/*
 * Maximum number of root hub ports.
 */
#define MAX_ROOT_PORTS	15	/* maximum OHCI root hub ports */

/*
 * This is the structure of the OHCI controller's memory mapped I/O
 * region.  This is Memory Mapped I/O.	You must use the readl() and
 * writel() macros defined in asm/io.h to access these!!
 */
struct ohci_regs {
	/* control and status registers */
	__u32 revision;
	__u32 control;
	__u32 cmdstatus;
	__u32 intrstatus;
	__u32 intrenable;
	__u32 intrdisable;
	/* memory pointers */
	__u32 hcca;
	__u32 ed_periodcurrent;
	__u32 ed_controlhead;
	__u32 ed_controlcurrent;
	__u32 ed_bulkhead;
	__u32 ed_bulkcurrent;
	__u32 donehead;
	/* frame counters */
	__u32 fminterval;
	__u32 fmremaining;
	__u32 fmnumber;
	__u32 periodicstart;
	__u32 lsthresh;
	/* Root hub ports */
	struct ohci_roothub_regs {
		__u32 a;
		__u32 b;
		__u32 status;
		__u32 portstatus[MAX_ROOT_PORTS];
	} roothub;
} __attribute__ ((aligned(32)));

/* OHCI CONTROL AND STATUS REGISTER MASKS */

/*
 * HcControl (control) register masks
 */
#define OHCI_CTRL_CBSR	(3 << 0)	/* control/bulk service ratio */
#define OHCI_CTRL_PLE	(1 << 2)	/* periodic list enable */
#define OHCI_CTRL_IE	(1 << 3)	/* isochronous enable */
#define OHCI_CTRL_CLE	(1 << 4)	/* control list enable */
#define OHCI_CTRL_BLE	(1 << 5)	/* bulk list enable */
#define OHCI_CTRL_HCFS	(3 << 6)	/* host controller functional state */
#define OHCI_CTRL_IR	(1 << 8)	/* interrupt routing */
#define OHCI_CTRL_RWC	(1 << 9)	/* remote wakeup connected */
#define OHCI_CTRL_RWE	(1 << 10)	/* remote wakeup enable */

/* pre-shifted values for HCFS */
#	define OHCI_USB_RESET	(0 << 6)
#	define OHCI_USB_RESUME	(1 << 6)
#	define OHCI_USB_OPER	(2 << 6)
#	define OHCI_USB_SUSPEND	(3 << 6)

/*
 * HcCommandStatus (cmdstatus) register masks
 */
#define OHCI_HCR	(1 << 0)	/* host controller reset */
#define OHCI_CLF	(1 << 1)	/* control list filled */
#define OHCI_BLF	(1 << 2)	/* bulk list filled */
#define OHCI_OCR	(1 << 3)	/* ownership change request */
#define OHCI_SOC	(3 << 16)	/* scheduling overrun count */

/*
 * masks used with interrupt registers:
 * HcInterruptStatus (intrstatus)
 * HcInterruptEnable (intrenable)
 * HcInterruptDisable (intrdisable)
 */
#define OHCI_INTR_SO	(1 << 0)	/* scheduling overrun */
#define OHCI_INTR_WDH	(1 << 1)	/* writeback of done_head */
#define OHCI_INTR_SF	(1 << 2)	/* start frame */
#define OHCI_INTR_RD	(1 << 3)	/* resume detect */
#define OHCI_INTR_UE	(1 << 4)	/* unrecoverable error */
#define OHCI_INTR_FNO	(1 << 5)	/* frame number overflow */
#define OHCI_INTR_RHSC	(1 << 6)	/* root hub status change */
#define OHCI_INTR_OC	(1 << 30)	/* ownership change */
#define OHCI_INTR_MIE	(1 << 31)	/* master interrupt enable */

/* Virtual Root HUB */
struct virt_root_hub {
	int devnum;		/* Address of Root Hub endpoint */
	void *dev;		/* was urb */
	void *int_addr;
	int send;
	int interval;
};

/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */

/* destination of request */
#define RH_INTERFACE		0x01
#define RH_ENDPOINT		0x02
#define RH_OTHER		0x03

#define RH_CLASS		0x20
#define RH_VENDOR		0x40

/* Requests: bRequest << 8 | bmRequestType */
#define RH_GET_STATUS		0x0080
#define RH_CLEAR_FEATURE	0x0100
#define RH_SET_FEATURE		0x0300
#define RH_SET_ADDRESS		0x0500
#define RH_GET_DESCRIPTOR	0x0680
#define RH_SET_DESCRIPTOR	0x0700
#define RH_GET_CONFIGURATION	0x0880
#define RH_SET_CONFIGURATION	0x0900
#define RH_GET_STATE		0x0280
#define RH_GET_INTERFACE	0x0A80
#define RH_SET_INTERFACE	0x0B00
#define RH_SYNC_FRAME		0x0C80
/* Our Vendor Specific Request */
#define RH_SET_EP		0x2000


/* Hub port features */
#define RH_PORT_CONNECTION	0x00
#define RH_PORT_ENABLE		0x01
#define RH_PORT_SUSPEND		0x02
#define RH_PORT_OVER_CURRENT	0x03
#define RH_PORT_RESET		0x04
#define RH_PORT_POWER		0x08
#define RH_PORT_LOW_SPEED	0x09

#define RH_C_PORT_CONNECTION	0x10
#define RH_C_PORT_ENABLE	0x11
#define RH_C_PORT_SUSPEND	0x12
#define RH_C_PORT_OVER_CURRENT	0x13
#define RH_C_PORT_RESET		0x14

/* Hub features */
#define RH_C_HUB_LOCAL_POWER	0x00
#define RH_C_HUB_OVER_CURRENT	0x01

#define RH_DEVICE_REMOTE_WAKEUP 0x00
#define RH_ENDPOINT_STALL	0x01

#define RH_ACK			0x01
#define RH_REQ_ERR		-1
#define RH_NACK			0x00


/* OHCI ROOT HUB REGISTER MASKS */

/* roothub.portstatus [i] bits */
#define RH_PS_CCS		0x00000001 /* current connect status */
#define RH_PS_PES		0x00000002 /* port enable status */
#define RH_PS_PSS		0x00000004 /* port suspend status */
#define RH_PS_POCI		0x00000008 /* port over current indicator */
#define RH_PS_PRS		0x00000010 /* port reset status */
#define RH_PS_PPS		0x00000100 /* port power status */
#define RH_PS_LSDA		0x00000200 /* low speed device attached */
#define RH_PS_CSC		0x00010000 /* connect status change */
#define RH_PS_PESC		0x00020000 /* port enable status change */
#define RH_PS_PSSC		0x00040000 /* port suspend status change */
#define RH_PS_OCIC		0x00080000 /* over current indicator change */
#define RH_PS_PRSC		0x00100000 /* port reset status change */

/* roothub.status bits */
#define RH_HS_LPS		0x00000001 /* local power status */
#define RH_HS_OCI		0x00000002 /* over current indicator */
#define RH_HS_DRWE		0x00008000 /* device remote wakeup enable */
#define RH_HS_LPSC		0x00010000 /* local power status change */
#define RH_HS_OCIC		0x00020000 /* over current indicator change */
#define RH_HS_CRWE		0x80000000 /* clear remote wakeup enable */

/* roothub.b masks */
#define RH_B_DR			0x0000ffff /* device removable flags */
#define RH_B_PPCM		0xffff0000 /* port power control mask */

/* roothub.a masks */
#define	RH_A_NDP		(0xff << 0)  /* number of downstream ports */
#define	RH_A_PSM		(1 << 8)     /* power switching mode */
#define	RH_A_NPS		(1 << 9)     /* no power switching */
#define	RH_A_DT			(1 << 10)    /* device type (mbz) */
#define	RH_A_OCPM		(1 << 11)    /* over current protection mode */
#define	RH_A_NOCP		(1 << 12)    /* no over current protection */
#define	RH_A_POTPGT		(0xff << 24) /* power on to power good time */

/* urb */
#define N_URB_TD 48
struct urb_priv {
	struct ed *ed;
	__u16 length;		/* number of tds associated with this request */
	__u16 td_cnt;		/* number of tds already serviced */
	int state;
	unsigned long pipe;
	int actual_length;
	struct td *td[N_URB_TD];	/* list pointer to all corresponding TDs
					   associated with this request */
};
#define URB_DEL 1

/*
 * This is the full ohci controller description
 *
 * Note how the "proper" USB information is just
 * a subset of what the full implementation needs. (Linus)
 */


struct ohci {
	struct ohci_hcca *hcca;	/* hcca */
	/*dma_addr_t hcca_dma; */

	int irq;
	int disabled;		/* e.g. got a UE, we're hung */
	int sleeping;
	unsigned long flags;	/* for HC bugs */

	struct ohci_regs *regs;	/* OHCI controller's memory */

	struct ed *ed_rm_list[2];  /* lists of all endpoints to be removed */
	struct ed *ed_bulktail;    /* last endpoint of bulk list */
	struct ed *ed_controltail; /* last endpoint of control list */
	int intrstatus;
	__u32 hc_control;	/* copy of the hc control reg */
	struct usb_device *dev[32];
	struct virt_root_hub rh;

	const char *slot_name;
};

#define NUM_EDS 8		/* num of preallocated endpoint descriptors */

struct ohci_device {
	struct ed ed[NUM_EDS];
	int ed_cnt;
};

/* hcd */
/* endpoint */
static int ep_link(struct ohci *ohci, struct ed *ed);
static int ep_unlink(struct ohci *ohci, struct ed *ed);
static struct ed *ep_add_ed(struct usb_device *usb_dev, unsigned long pipe);

/*-------------------------------------------------------------------------*/

/* we need more TDs than EDs */
#define NUM_TD 64

/* +1 so we can align the storage */
struct td gtd[NUM_TD + 1];

/* pointers to aligned storage */
struct td *ptd;

/* TDs ... */
static inline struct td *td_alloc(struct usb_device *usb_dev)
{
	int i;
	struct td *td;

	td = NULL;
	for (i = 0; i < NUM_TD; i++) {
		if (ptd[i].usb_dev == NULL) {
			td = &ptd[i];
			td->usb_dev = usb_dev;
			break;
		}
	}

	return td;
}

static inline void ed_free(struct ed *ed)
{
	ed->usb_dev = NULL;
}
Commit	Line	Data
149dded2 WD	1	/*
	2	* URB OHCI HCD (Host Controller Driver) for USB.
	3	*
	4	* (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
	5	* (C) Copyright 2000-2001 David Brownell <dbrownell@users.sourceforge.net>
	6	*
	7	* usb-ohci.h
	8	*/
	9
	10
	11	static int cc_to_error[16] = {
	12
	13	/* mapping of the OHCI CC status to error codes */
d67cce2d	14	/* No Error */ 0,
	15	/* CRC Error */ USB_ST_CRC_ERR,
	16	/* Bit Stuff */ USB_ST_BIT_ERR,
	17	/* Data Togg */ USB_ST_CRC_ERR,
	18	/* Stall */ USB_ST_STALLED,
	19	/* DevNotResp */ -1,
	20	/* PIDCheck */ USB_ST_BIT_ERR,
	21	/* UnExpPID */ USB_ST_BIT_ERR,
	22	/* DataOver */ USB_ST_BUF_ERR,
	23	/* DataUnder */ USB_ST_BUF_ERR,
	24	/* reservd */ -1,
	25	/* reservd */ -1,
	26	/* BufferOver */ USB_ST_BUF_ERR,
	27	/* BuffUnder */ USB_ST_BUF_ERR,
	28	/* Not Access */ -1,
	29	/* Not Access */ -1
149dded2 WD	30	};
	31
	32	/* ED States */
53677ef1 WD	33	#define ED_NEW 0x00
53677ef1 WD	34	#define ED_UNLINK 0x01
149dded2 WD	35	#define ED_OPER 0x02
149dded2 WD	36	#define ED_DEL 0x04
53677ef1	37	#define ED_URB_DEL 0x08
149dded2 WD	38
	39	/* usb_ohci_ed */
	40	struct ed {
	41	__u32 hwINFO;
	42	__u32 hwTailP;
	43	__u32 hwHeadP;
	44	__u32 hwNextED;
	45
	46	struct ed *ed_prev;
	47	__u8 int_period;
	48	__u8 int_branch;
	49	__u8 int_load;
	50	__u8 int_interval;
	51	__u8 state;
	52	__u8 type;
	53	__u16 last_iso;
	54	struct ed *ed_rm_list;
	55
	56	struct usb_device *usb_dev;
	57	__u32 unused[3];
d67cce2d	58	} __attribute__ ((aligned(16)));
149dded2 WD	59
149dded2 WD	60	/* TD info field */
53677ef1	61	#define TD_CC 0xf0000000
d67cce2d	62	#define TD_CC_GET(td_p) (((td_p) >> 28) & 0x0f)
	63	#define TD_CC_SET(td_p, cc) \
	64	{(td_p) = ((td_p) & 0x0fffffff) \| (((cc) & 0x0f) << 28)}
53677ef1 WD	65	#define TD_EC 0x0C000000
	66	#define TD_T 0x03000000
	67	#define TD_T_DATA0 0x02000000
	68	#define TD_T_DATA1 0x03000000
	69	#define TD_T_TOGGLE 0x00000000
	70	#define TD_R 0x00040000
	71	#define TD_DI 0x00E00000
	72	#define TD_DI_SET(X) (((X) & 0x07)<< 21)
	73	#define TD_DP 0x00180000
	74	#define TD_DP_SETUP 0x00000000
	75	#define TD_DP_IN 0x00100000
	76	#define TD_DP_OUT 0x00080000
	77
	78	#define TD_ISO 0x00010000
	79	#define TD_DEL 0x00020000
149dded2 WD	80
149dded2 WD	81	/* CC Codes */
53677ef1 WD	82	#define TD_CC_NOERROR 0x00
	83	#define TD_CC_CRC 0x01
	84	#define TD_CC_BITSTUFFING 0x02
	85	#define TD_CC_DATATOGGLEM 0x03
	86	#define TD_CC_STALL 0x04
	87	#define TD_DEVNOTRESP 0x05
	88	#define TD_PIDCHECKFAIL 0x06
	89	#define TD_UNEXPECTEDPID 0x07
	90	#define TD_DATAOVERRUN 0x08
	91	#define TD_DATAUNDERRUN 0x09
	92	#define TD_BUFFEROVERRUN 0x0C
	93	#define TD_BUFFERUNDERRUN 0x0D
	94	#define TD_NOTACCESSED 0x0F
149dded2 WD	95
	96
	97	#define MAXPSW 1
	98
	99	struct td {
	100	__u32 hwINFO;
53677ef1 WD	101	__u32 hwCBP; /* Current Buffer Pointer */
	102	__u32 hwNextTD; /* Next TD Pointer */
	103	__u32 hwBE; /* Memory Buffer End Pointer */
	104
	105	__u8 unused;
	106	__u8 index;
	107	struct ed *ed;
	108	struct td *next_dl_td;
149dded2 WD	109	struct usb_device *usb_dev;
	110	int transfer_len;
	111	__u32 data;
	112
	113	__u32 unused2[2];
d67cce2d	114	} __attribute__ ((aligned(32)));
149dded2 WD	115
	116	#define OHCI_ED_SKIP (1 << 14)
	117
	118	/*
	119	* The HCCA (Host Controller Communications Area) is a 256 byte
	120	* structure defined in the OHCI spec. that the host controller is
	121	* told the base address of. It must be 256-byte aligned.
	122	*/
	123
d67cce2d	124	#define NUM_INTS 32 /* part of the OHCI standard */
149dded2	125	struct ohci_hcca {
d67cce2d	126	__u32 int_table[NUM_INTS]; /* Interrupt ED table */
	127	__u16 frame_no; /* current frame number */
	128	__u16 pad1; /* set to 0 on each frame_no change */
	129	__u32 done_head; /* info returned for an interrupt */
	130	u8 reserved_for_hc[116];
	131	} __attribute__ ((aligned(256)));
149dded2 WD	132
	133	/*
	134	* Maximum number of root hub ports.
	135	*/
	136	#define MAX_ROOT_PORTS 15 /* maximum OHCI root hub ports */
	137
	138	/*
	139	* This is the structure of the OHCI controller's memory mapped I/O
53677ef1	140	* region. This is Memory Mapped I/O. You must use the readl() and
149dded2 WD	141	* writel() macros defined in asm/io.h to access these!!
	142	*/
	143	struct ohci_regs {
	144	/* control and status registers */
d67cce2d	145	__u32 revision;
	146	__u32 control;
	147	__u32 cmdstatus;
	148	__u32 intrstatus;
	149	__u32 intrenable;
	150	__u32 intrdisable;
149dded2	151	/* memory pointers */
d67cce2d	152	__u32 hcca;
	153	__u32 ed_periodcurrent;
	154	__u32 ed_controlhead;
	155	__u32 ed_controlcurrent;
	156	__u32 ed_bulkhead;
	157	__u32 ed_bulkcurrent;
	158	__u32 donehead;
149dded2	159	/* frame counters */
d67cce2d	160	__u32 fminterval;
	161	__u32 fmremaining;
	162	__u32 fmnumber;
	163	__u32 periodicstart;
	164	__u32 lsthresh;
149dded2	165	/* Root hub ports */
d67cce2d	166	struct ohci_roothub_regs {
	167	__u32 a;
	168	__u32 b;
	169	__u32 status;
	170	__u32 portstatus[MAX_ROOT_PORTS];
149dded2	171	} roothub;
d67cce2d	172	} __attribute__ ((aligned(32)));
149dded2 WD	173
	174	/* OHCI CONTROL AND STATUS REGISTER MASKS */
	175
	176	/*
	177	* HcControl (control) register masks
	178	*/
	179	#define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */
	180	#define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */
	181	#define OHCI_CTRL_IE (1 << 3) /* isochronous enable */
	182	#define OHCI_CTRL_CLE (1 << 4) /* control list enable */
	183	#define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */
	184	#define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */
	185	#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */
	186	#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */
	187	#define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */
	188
	189	/* pre-shifted values for HCFS */
	190	# define OHCI_USB_RESET (0 << 6)
	191	# define OHCI_USB_RESUME (1 << 6)
	192	# define OHCI_USB_OPER (2 << 6)
	193	# define OHCI_USB_SUSPEND (3 << 6)
	194
	195	/*
	196	* HcCommandStatus (cmdstatus) register masks
	197	*/
	198	#define OHCI_HCR (1 << 0) /* host controller reset */
53677ef1 WD	199	#define OHCI_CLF (1 << 1) /* control list filled */
	200	#define OHCI_BLF (1 << 2) /* bulk list filled */
	201	#define OHCI_OCR (1 << 3) /* ownership change request */
	202	#define OHCI_SOC (3 << 16) /* scheduling overrun count */
149dded2 WD	203
	204	/*
	205	* masks used with interrupt registers:
	206	* HcInterruptStatus (intrstatus)
	207	* HcInterruptEnable (intrenable)
	208	* HcInterruptDisable (intrdisable)
	209	*/
	210	#define OHCI_INTR_SO (1 << 0) /* scheduling overrun */
	211	#define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */
	212	#define OHCI_INTR_SF (1 << 2) /* start frame */
	213	#define OHCI_INTR_RD (1 << 3) /* resume detect */
	214	#define OHCI_INTR_UE (1 << 4) /* unrecoverable error */
	215	#define OHCI_INTR_FNO (1 << 5) /* frame number overflow */
	216	#define OHCI_INTR_RHSC (1 << 6) /* root hub status change */
	217	#define OHCI_INTR_OC (1 << 30) /* ownership change */
	218	#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */
	219
149dded2 WD	220	/* Virtual Root HUB */
149dded2 WD	221	struct virt_root_hub {
d67cce2d	222	int devnum; /* Address of Root Hub endpoint */
d67cce2d	223	void dev; / was urb */
149dded2 WD	224	void *int_addr;
	225	int send;
	226	int interval;
	227	};
	228
	229	/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */
	230
	231	/* destination of request */
53677ef1 WD	232	#define RH_INTERFACE 0x01
	233	#define RH_ENDPOINT 0x02
	234	#define RH_OTHER 0x03
149dded2	235
53677ef1 WD	236	#define RH_CLASS 0x20
53677ef1 WD	237	#define RH_VENDOR 0x40
149dded2 WD	238
149dded2 WD	239	/* Requests: bRequest << 8 \| bmRequestType */
53677ef1 WD	240	#define RH_GET_STATUS 0x0080
	241	#define RH_CLEAR_FEATURE 0x0100
	242	#define RH_SET_FEATURE 0x0300
149dded2 WD	243	#define RH_SET_ADDRESS 0x0500
149dded2 WD	244	#define RH_GET_DESCRIPTOR 0x0680
53677ef1	245	#define RH_SET_DESCRIPTOR 0x0700
149dded2 WD	246	#define RH_GET_CONFIGURATION 0x0880
149dded2 WD	247	#define RH_SET_CONFIGURATION 0x0900
53677ef1 WD	248	#define RH_GET_STATE 0x0280
	249	#define RH_GET_INTERFACE 0x0A80
	250	#define RH_SET_INTERFACE 0x0B00
	251	#define RH_SYNC_FRAME 0x0C80
149dded2	252	/* Our Vendor Specific Request */
53677ef1	253	#define RH_SET_EP 0x2000
149dded2 WD	254
	255
	256	/* Hub port features */
53677ef1 WD	257	#define RH_PORT_CONNECTION 0x00
	258	#define RH_PORT_ENABLE 0x01
	259	#define RH_PORT_SUSPEND 0x02
	260	#define RH_PORT_OVER_CURRENT 0x03
	261	#define RH_PORT_RESET 0x04
	262	#define RH_PORT_POWER 0x08
	263	#define RH_PORT_LOW_SPEED 0x09
	264
	265	#define RH_C_PORT_CONNECTION 0x10
	266	#define RH_C_PORT_ENABLE 0x11
	267	#define RH_C_PORT_SUSPEND 0x12
	268	#define RH_C_PORT_OVER_CURRENT 0x13
	269	#define RH_C_PORT_RESET 0x14
149dded2 WD	270
149dded2 WD	271	/* Hub features */
53677ef1 WD	272	#define RH_C_HUB_LOCAL_POWER 0x00
53677ef1 WD	273	#define RH_C_HUB_OVER_CURRENT 0x01
149dded2	274
53677ef1 WD	275	#define RH_DEVICE_REMOTE_WAKEUP 0x00
53677ef1 WD	276	#define RH_ENDPOINT_STALL 0x01
149dded2	277
53677ef1 WD	278	#define RH_ACK 0x01
	279	#define RH_REQ_ERR -1
	280	#define RH_NACK 0x00
149dded2 WD	281
	282
	283	/* OHCI ROOT HUB REGISTER MASKS */
	284
	285	/* roothub.portstatus [i] bits */
d67cce2d	286	#define RH_PS_CCS 0x00000001 /* current connect status */
	287	#define RH_PS_PES 0x00000002 /* port enable status */
	288	#define RH_PS_PSS 0x00000004 /* port suspend status */
	289	#define RH_PS_POCI 0x00000008 /* port over current indicator */
	290	#define RH_PS_PRS 0x00000010 /* port reset status */
	291	#define RH_PS_PPS 0x00000100 /* port power status */
	292	#define RH_PS_LSDA 0x00000200 /* low speed device attached */
	293	#define RH_PS_CSC 0x00010000 /* connect status change */
	294	#define RH_PS_PESC 0x00020000 /* port enable status change */
	295	#define RH_PS_PSSC 0x00040000 /* port suspend status change */
	296	#define RH_PS_OCIC 0x00080000 /* over current indicator change */
	297	#define RH_PS_PRSC 0x00100000 /* port reset status change */
149dded2 WD	298
149dded2 WD	299	/* roothub.status bits */
d67cce2d	300	#define RH_HS_LPS 0x00000001 /* local power status */
	301	#define RH_HS_OCI 0x00000002 /* over current indicator */
	302	#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */
	303	#define RH_HS_LPSC 0x00010000 /* local power status change */
	304	#define RH_HS_OCIC 0x00020000 /* over current indicator change */
	305	#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */
149dded2 WD	306
149dded2 WD	307	/* roothub.b masks */
d67cce2d	308	#define RH_B_DR 0x0000ffff /* device removable flags */
d67cce2d	309	#define RH_B_PPCM 0xffff0000 /* port power control mask */
149dded2 WD	310
149dded2 WD	311	/* roothub.a masks */
d67cce2d	312	#define RH_A_NDP (0xff << 0) /* number of downstream ports */
	313	#define RH_A_PSM (1 << 8) /* power switching mode */
	314	#define RH_A_NPS (1 << 9) /* no power switching */
	315	#define RH_A_DT (1 << 10) /* device type (mbz) */
	316	#define RH_A_OCPM (1 << 11) /* over current protection mode */
	317	#define RH_A_NOCP (1 << 12) /* no over current protection */
	318	#define RH_A_POTPGT (0xff << 24) /* power on to power good time */
149dded2 WD	319
	320	/* urb */
	321	#define N_URB_TD 48
d67cce2d	322	struct urb_priv {
	323	struct ed *ed;
	324	__u16 length; /* number of tds associated with this request */
	325	__u16 td_cnt; /* number of tds already serviced */
	326	int state;
149dded2 WD	327	unsigned long pipe;
149dded2 WD	328	int actual_length;
d67cce2d	329	struct td td[N_URB_TD]; / list pointer to all corresponding TDs
	330	associated with this request */
	331	};
149dded2 WD	332	#define URB_DEL 1
	333
	334	/*
	335	* This is the full ohci controller description
	336	*
	337	* Note how the "proper" USB information is just
	338	* a subset of what the full implementation needs. (Linus)
	339	*/
	340
	341
d67cce2d	342	struct ohci {
53677ef1 WD	343	struct ohci_hcca hcca; / hcca */
53677ef1 WD	344	/dma_addr_t hcca_dma; /
149dded2 WD	345
149dded2 WD	346	int irq;
53677ef1	347	int disabled; /* e.g. got a UE, we're hung */
149dded2	348	int sleeping;
53677ef1	349	unsigned long flags; /* for HC bugs */
149dded2 WD	350
	351	struct ohci_regs regs; / OHCI controller's memory */
	352
d67cce2d	353	struct ed ed_rm_list[2]; / lists of all endpoints to be removed */
	354	struct ed ed_bulktail; / last endpoint of bulk list */
	355	struct ed ed_controltail; / last endpoint of control list */
149dded2	356	int intrstatus;
53677ef1	357	__u32 hc_control; /* copy of the hc control reg */
149dded2 WD	358	struct usb_device *dev[32];
	359	struct virt_root_hub rh;
	360
53677ef1	361	const char *slot_name;
d67cce2d	362	};
149dded2 WD	363
	364	#define NUM_EDS 8 /* num of preallocated endpoint descriptors */
	365
	366	struct ohci_device {
d67cce2d	367	struct ed ed[NUM_EDS];
149dded2 WD	368	int ed_cnt;
	369	};
	370
	371	/* hcd */
	372	/* endpoint */
d67cce2d	373	static int ep_link(struct ohci ohci, struct ed ed);
	374	static int ep_unlink(struct ohci ohci, struct ed ed);
	375	static struct ed ep_add_ed(struct usb_device usb_dev, unsigned long pipe);
149dded2 WD	376
	377	/-------------------------------------------------------------------------/
	378
	379	/* we need more TDs than EDs */
	380	#define NUM_TD 64
	381
	382	/* +1 so we can align the storage */
d67cce2d	383	struct td gtd[NUM_TD + 1];
53677ef1	384
149dded2	385	/* pointers to aligned storage */
d67cce2d	386	struct td *ptd;
149dded2 WD	387
149dded2 WD	388	/* TDs ... */
d67cce2d	389	static inline struct td td_alloc(struct usb_device usb_dev)
149dded2 WD	390	{
149dded2 WD	391	int i;
53677ef1	392	struct td *td;
149dded2 WD	393
149dded2 WD	394	td = NULL;
53677ef1 WD	395	for (i = 0; i < NUM_TD; i++) {
53677ef1 WD	396	if (ptd[i].usb_dev == NULL) {
149dded2 WD	397	td = &ptd[i];
	398	td->usb_dev = usb_dev;
	399	break;
	400	}
	401	}
	402
	403	return td;
	404	}
	405
d67cce2d	406	static inline void ed_free(struct ed *ed)
149dded2 WD	407	{
	408	ed->usb_dev = NULL;
	409	}