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5853e133 VG |
1 | /* |
2 | * USB HOST XHCI Controller stack | |
3 | * | |
4 | * Based on xHCI host controller driver in linux-kernel | |
5 | * by Sarah Sharp. | |
6 | * | |
7 | * Copyright (C) 2008 Intel Corp. | |
8 | * Author: Sarah Sharp | |
9 | * | |
10 | * Copyright (C) 2013 Samsung Electronics Co.Ltd | |
11 | * Authors: Vivek Gautam <gautam.vivek@samsung.com> | |
12 | * Vikas Sajjan <vikas.sajjan@samsung.com> | |
13 | * | |
14 | * SPDX-License-Identifier: GPL-2.0+ | |
15 | */ | |
16 | ||
17 | /** | |
18 | * This file gives the xhci stack for usb3.0 looking into | |
19 | * xhci specification Rev1.0 (5/21/10). | |
20 | * The quirk devices support hasn't been given yet. | |
21 | */ | |
22 | ||
23 | #include <common.h> | |
a5762fe0 | 24 | #include <dm.h> |
5853e133 VG |
25 | #include <asm/byteorder.h> |
26 | #include <usb.h> | |
27 | #include <malloc.h> | |
28 | #include <watchdog.h> | |
29 | #include <asm/cache.h> | |
30 | #include <asm/unaligned.h> | |
5d97dff0 | 31 | #include <linux/errno.h> |
5853e133 VG |
32 | #include "xhci.h" |
33 | ||
34 | #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT | |
35 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 | |
36 | #endif | |
37 | ||
38 | static struct descriptor { | |
39 | struct usb_hub_descriptor hub; | |
40 | struct usb_device_descriptor device; | |
41 | struct usb_config_descriptor config; | |
42 | struct usb_interface_descriptor interface; | |
43 | struct usb_endpoint_descriptor endpoint; | |
44 | struct usb_ss_ep_comp_descriptor ep_companion; | |
45 | } __attribute__ ((packed)) descriptor = { | |
46 | { | |
47 | 0xc, /* bDescLength */ | |
48 | 0x2a, /* bDescriptorType: hub descriptor */ | |
49 | 2, /* bNrPorts -- runtime modified */ | |
50 | cpu_to_le16(0x8), /* wHubCharacteristics */ | |
51 | 10, /* bPwrOn2PwrGood */ | |
52 | 0, /* bHubCntrCurrent */ | |
337fc7e6 BM |
53 | { /* Device removable */ |
54 | } /* at most 7 ports! XXX */ | |
5853e133 VG |
55 | }, |
56 | { | |
57 | 0x12, /* bLength */ | |
58 | 1, /* bDescriptorType: UDESC_DEVICE */ | |
59 | cpu_to_le16(0x0300), /* bcdUSB: v3.0 */ | |
60 | 9, /* bDeviceClass: UDCLASS_HUB */ | |
61 | 0, /* bDeviceSubClass: UDSUBCLASS_HUB */ | |
62 | 3, /* bDeviceProtocol: UDPROTO_SSHUBSTT */ | |
63 | 9, /* bMaxPacketSize: 512 bytes 2^9 */ | |
64 | 0x0000, /* idVendor */ | |
65 | 0x0000, /* idProduct */ | |
66 | cpu_to_le16(0x0100), /* bcdDevice */ | |
67 | 1, /* iManufacturer */ | |
68 | 2, /* iProduct */ | |
69 | 0, /* iSerialNumber */ | |
70 | 1 /* bNumConfigurations: 1 */ | |
71 | }, | |
72 | { | |
73 | 0x9, | |
74 | 2, /* bDescriptorType: UDESC_CONFIG */ | |
75 | cpu_to_le16(0x1f), /* includes SS endpoint descriptor */ | |
76 | 1, /* bNumInterface */ | |
77 | 1, /* bConfigurationValue */ | |
78 | 0, /* iConfiguration */ | |
79 | 0x40, /* bmAttributes: UC_SELF_POWER */ | |
80 | 0 /* bMaxPower */ | |
81 | }, | |
82 | { | |
83 | 0x9, /* bLength */ | |
84 | 4, /* bDescriptorType: UDESC_INTERFACE */ | |
85 | 0, /* bInterfaceNumber */ | |
86 | 0, /* bAlternateSetting */ | |
87 | 1, /* bNumEndpoints */ | |
88 | 9, /* bInterfaceClass: UICLASS_HUB */ | |
89 | 0, /* bInterfaceSubClass: UISUBCLASS_HUB */ | |
90 | 0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */ | |
91 | 0 /* iInterface */ | |
92 | }, | |
93 | { | |
94 | 0x7, /* bLength */ | |
95 | 5, /* bDescriptorType: UDESC_ENDPOINT */ | |
96 | 0x81, /* bEndpointAddress: IN endpoint 1 */ | |
97 | 3, /* bmAttributes: UE_INTERRUPT */ | |
98 | 8, /* wMaxPacketSize */ | |
99 | 255 /* bInterval */ | |
100 | }, | |
101 | { | |
102 | 0x06, /* ss_bLength */ | |
103 | 0x30, /* ss_bDescriptorType: SS EP Companion */ | |
104 | 0x00, /* ss_bMaxBurst: allows 1 TX between ACKs */ | |
105 | /* ss_bmAttributes: 1 packet per service interval */ | |
106 | 0x00, | |
107 | /* ss_wBytesPerInterval: 15 bits for max 15 ports */ | |
108 | cpu_to_le16(0x02), | |
109 | }, | |
110 | }; | |
111 | ||
a5762fe0 | 112 | #ifndef CONFIG_DM_USB |
5853e133 | 113 | static struct xhci_ctrl xhcic[CONFIG_USB_MAX_CONTROLLER_COUNT]; |
a5762fe0 | 114 | #endif |
5853e133 | 115 | |
7c1deec0 SG |
116 | struct xhci_ctrl *xhci_get_ctrl(struct usb_device *udev) |
117 | { | |
a5762fe0 SG |
118 | #ifdef CONFIG_DM_USB |
119 | struct udevice *dev; | |
120 | ||
121 | /* Find the USB controller */ | |
122 | for (dev = udev->dev; | |
123 | device_get_uclass_id(dev) != UCLASS_USB; | |
124 | dev = dev->parent) | |
125 | ; | |
126 | return dev_get_priv(dev); | |
127 | #else | |
7c1deec0 | 128 | return udev->controller; |
a5762fe0 | 129 | #endif |
7c1deec0 SG |
130 | } |
131 | ||
5853e133 VG |
132 | /** |
133 | * Waits for as per specified amount of time | |
134 | * for the "result" to match with "done" | |
135 | * | |
136 | * @param ptr pointer to the register to be read | |
137 | * @param mask mask for the value read | |
138 | * @param done value to be campared with result | |
139 | * @param usec time to wait till | |
140 | * @return 0 if handshake is success else < 0 on failure | |
141 | */ | |
142 | static int handshake(uint32_t volatile *ptr, uint32_t mask, | |
143 | uint32_t done, int usec) | |
144 | { | |
145 | uint32_t result; | |
146 | ||
147 | do { | |
148 | result = xhci_readl(ptr); | |
149 | if (result == ~(uint32_t)0) | |
150 | return -ENODEV; | |
151 | result &= mask; | |
152 | if (result == done) | |
153 | return 0; | |
154 | usec--; | |
155 | udelay(1); | |
156 | } while (usec > 0); | |
157 | ||
158 | return -ETIMEDOUT; | |
159 | } | |
160 | ||
161 | /** | |
162 | * Set the run bit and wait for the host to be running. | |
163 | * | |
164 | * @param hcor pointer to host controller operation registers | |
165 | * @return status of the Handshake | |
166 | */ | |
167 | static int xhci_start(struct xhci_hcor *hcor) | |
168 | { | |
169 | u32 temp; | |
170 | int ret; | |
171 | ||
172 | puts("Starting the controller\n"); | |
173 | temp = xhci_readl(&hcor->or_usbcmd); | |
174 | temp |= (CMD_RUN); | |
175 | xhci_writel(&hcor->or_usbcmd, temp); | |
176 | ||
177 | /* | |
178 | * Wait for the HCHalted Status bit to be 0 to indicate the host is | |
179 | * running. | |
180 | */ | |
181 | ret = handshake(&hcor->or_usbsts, STS_HALT, 0, XHCI_MAX_HALT_USEC); | |
182 | if (ret) | |
183 | debug("Host took too long to start, " | |
184 | "waited %u microseconds.\n", | |
185 | XHCI_MAX_HALT_USEC); | |
186 | return ret; | |
187 | } | |
188 | ||
189 | /** | |
190 | * Resets the XHCI Controller | |
191 | * | |
192 | * @param hcor pointer to host controller operation registers | |
193 | * @return -EBUSY if XHCI Controller is not halted else status of handshake | |
194 | */ | |
121a4d13 | 195 | static int xhci_reset(struct xhci_hcor *hcor) |
5853e133 VG |
196 | { |
197 | u32 cmd; | |
198 | u32 state; | |
199 | int ret; | |
200 | ||
201 | /* Halting the Host first */ | |
a5ccda47 | 202 | debug("// Halt the HC: %p\n", hcor); |
5853e133 VG |
203 | state = xhci_readl(&hcor->or_usbsts) & STS_HALT; |
204 | if (!state) { | |
205 | cmd = xhci_readl(&hcor->or_usbcmd); | |
206 | cmd &= ~CMD_RUN; | |
207 | xhci_writel(&hcor->or_usbcmd, cmd); | |
208 | } | |
209 | ||
210 | ret = handshake(&hcor->or_usbsts, | |
211 | STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC); | |
212 | if (ret) { | |
213 | printf("Host not halted after %u microseconds.\n", | |
214 | XHCI_MAX_HALT_USEC); | |
215 | return -EBUSY; | |
216 | } | |
217 | ||
218 | debug("// Reset the HC\n"); | |
219 | cmd = xhci_readl(&hcor->or_usbcmd); | |
220 | cmd |= CMD_RESET; | |
221 | xhci_writel(&hcor->or_usbcmd, cmd); | |
222 | ||
223 | ret = handshake(&hcor->or_usbcmd, CMD_RESET, 0, XHCI_MAX_RESET_USEC); | |
224 | if (ret) | |
225 | return ret; | |
226 | ||
227 | /* | |
228 | * xHCI cannot write to any doorbells or operational registers other | |
229 | * than status until the "Controller Not Ready" flag is cleared. | |
230 | */ | |
231 | return handshake(&hcor->or_usbsts, STS_CNR, 0, XHCI_MAX_RESET_USEC); | |
232 | } | |
233 | ||
234 | /** | |
235 | * Used for passing endpoint bitmasks between the core and HCDs. | |
236 | * Find the index for an endpoint given its descriptor. | |
237 | * Use the return value to right shift 1 for the bitmask. | |
238 | * | |
239 | * Index = (epnum * 2) + direction - 1, | |
240 | * where direction = 0 for OUT, 1 for IN. | |
241 | * For control endpoints, the IN index is used (OUT index is unused), so | |
242 | * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2) | |
243 | * | |
244 | * @param desc USB enpdoint Descriptor | |
245 | * @return index of the Endpoint | |
246 | */ | |
247 | static unsigned int xhci_get_ep_index(struct usb_endpoint_descriptor *desc) | |
248 | { | |
249 | unsigned int index; | |
250 | ||
251 | if (usb_endpoint_xfer_control(desc)) | |
252 | index = (unsigned int)(usb_endpoint_num(desc) * 2); | |
253 | else | |
254 | index = (unsigned int)((usb_endpoint_num(desc) * 2) - | |
255 | (usb_endpoint_dir_in(desc) ? 0 : 1)); | |
256 | ||
257 | return index; | |
258 | } | |
259 | ||
260 | /** | |
261 | * Issue a configure endpoint command or evaluate context command | |
262 | * and wait for it to finish. | |
263 | * | |
264 | * @param udev pointer to the Device Data Structure | |
265 | * @param ctx_change flag to indicate the Context has changed or NOT | |
266 | * @return 0 on success, -1 on failure | |
267 | */ | |
268 | static int xhci_configure_endpoints(struct usb_device *udev, bool ctx_change) | |
269 | { | |
270 | struct xhci_container_ctx *in_ctx; | |
271 | struct xhci_virt_device *virt_dev; | |
7c1deec0 | 272 | struct xhci_ctrl *ctrl = xhci_get_ctrl(udev); |
5853e133 VG |
273 | union xhci_trb *event; |
274 | ||
275 | virt_dev = ctrl->devs[udev->slot_id]; | |
276 | in_ctx = virt_dev->in_ctx; | |
277 | ||
421a5a0c | 278 | xhci_flush_cache((uintptr_t)in_ctx->bytes, in_ctx->size); |
5853e133 VG |
279 | xhci_queue_command(ctrl, in_ctx->bytes, udev->slot_id, 0, |
280 | ctx_change ? TRB_EVAL_CONTEXT : TRB_CONFIG_EP); | |
281 | event = xhci_wait_for_event(ctrl, TRB_COMPLETION); | |
282 | BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags)) | |
283 | != udev->slot_id); | |
284 | ||
285 | switch (GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))) { | |
286 | case COMP_SUCCESS: | |
287 | debug("Successful %s command\n", | |
288 | ctx_change ? "Evaluate Context" : "Configure Endpoint"); | |
289 | break; | |
290 | default: | |
291 | printf("ERROR: %s command returned completion code %d.\n", | |
292 | ctx_change ? "Evaluate Context" : "Configure Endpoint", | |
293 | GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))); | |
294 | return -EINVAL; | |
295 | } | |
296 | ||
297 | xhci_acknowledge_event(ctrl); | |
298 | ||
299 | return 0; | |
300 | } | |
301 | ||
302 | /** | |
303 | * Configure the endpoint, programming the device contexts. | |
304 | * | |
305 | * @param udev pointer to the USB device structure | |
306 | * @return returns the status of the xhci_configure_endpoints | |
307 | */ | |
308 | static int xhci_set_configuration(struct usb_device *udev) | |
309 | { | |
310 | struct xhci_container_ctx *in_ctx; | |
311 | struct xhci_container_ctx *out_ctx; | |
312 | struct xhci_input_control_ctx *ctrl_ctx; | |
313 | struct xhci_slot_ctx *slot_ctx; | |
314 | struct xhci_ep_ctx *ep_ctx[MAX_EP_CTX_NUM]; | |
315 | int cur_ep; | |
316 | int max_ep_flag = 0; | |
317 | int ep_index; | |
318 | unsigned int dir; | |
319 | unsigned int ep_type; | |
7c1deec0 | 320 | struct xhci_ctrl *ctrl = xhci_get_ctrl(udev); |
5853e133 VG |
321 | int num_of_ep; |
322 | int ep_flag = 0; | |
323 | u64 trb_64 = 0; | |
324 | int slot_id = udev->slot_id; | |
325 | struct xhci_virt_device *virt_dev = ctrl->devs[slot_id]; | |
326 | struct usb_interface *ifdesc; | |
327 | ||
328 | out_ctx = virt_dev->out_ctx; | |
329 | in_ctx = virt_dev->in_ctx; | |
330 | ||
331 | num_of_ep = udev->config.if_desc[0].no_of_ep; | |
332 | ifdesc = &udev->config.if_desc[0]; | |
333 | ||
334 | ctrl_ctx = xhci_get_input_control_ctx(in_ctx); | |
aab0db08 BM |
335 | /* Initialize the input context control */ |
336 | ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG); | |
5853e133 VG |
337 | ctrl_ctx->drop_flags = 0; |
338 | ||
339 | /* EP_FLAG gives values 1 & 4 for EP1OUT and EP2IN */ | |
340 | for (cur_ep = 0; cur_ep < num_of_ep; cur_ep++) { | |
341 | ep_flag = xhci_get_ep_index(&ifdesc->ep_desc[cur_ep]); | |
342 | ctrl_ctx->add_flags |= cpu_to_le32(1 << (ep_flag + 1)); | |
343 | if (max_ep_flag < ep_flag) | |
344 | max_ep_flag = ep_flag; | |
345 | } | |
346 | ||
421a5a0c | 347 | xhci_inval_cache((uintptr_t)out_ctx->bytes, out_ctx->size); |
5853e133 VG |
348 | |
349 | /* slot context */ | |
350 | xhci_slot_copy(ctrl, in_ctx, out_ctx); | |
351 | slot_ctx = xhci_get_slot_ctx(ctrl, in_ctx); | |
352 | slot_ctx->dev_info &= ~(LAST_CTX_MASK); | |
353 | slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(max_ep_flag + 1) | 0); | |
354 | ||
355 | xhci_endpoint_copy(ctrl, in_ctx, out_ctx, 0); | |
356 | ||
357 | /* filling up ep contexts */ | |
358 | for (cur_ep = 0; cur_ep < num_of_ep; cur_ep++) { | |
359 | struct usb_endpoint_descriptor *endpt_desc = NULL; | |
360 | ||
361 | endpt_desc = &ifdesc->ep_desc[cur_ep]; | |
362 | trb_64 = 0; | |
363 | ||
364 | ep_index = xhci_get_ep_index(endpt_desc); | |
365 | ep_ctx[ep_index] = xhci_get_ep_ctx(ctrl, in_ctx, ep_index); | |
366 | ||
367 | /* Allocate the ep rings */ | |
368 | virt_dev->eps[ep_index].ring = xhci_ring_alloc(1, true); | |
369 | if (!virt_dev->eps[ep_index].ring) | |
370 | return -ENOMEM; | |
371 | ||
372 | /*NOTE: ep_desc[0] actually represents EP1 and so on */ | |
373 | dir = (((endpt_desc->bEndpointAddress) & (0x80)) >> 7); | |
374 | ep_type = (((endpt_desc->bmAttributes) & (0x3)) | (dir << 2)); | |
375 | ep_ctx[ep_index]->ep_info2 = | |
376 | cpu_to_le32(ep_type << EP_TYPE_SHIFT); | |
377 | ep_ctx[ep_index]->ep_info2 |= | |
378 | cpu_to_le32(MAX_PACKET | |
379 | (get_unaligned(&endpt_desc->wMaxPacketSize))); | |
380 | ||
381 | ep_ctx[ep_index]->ep_info2 |= | |
382 | cpu_to_le32(((0 & MAX_BURST_MASK) << MAX_BURST_SHIFT) | | |
383 | ((3 & ERROR_COUNT_MASK) << ERROR_COUNT_SHIFT)); | |
384 | ||
385 | trb_64 = (uintptr_t) | |
386 | virt_dev->eps[ep_index].ring->enqueue; | |
387 | ep_ctx[ep_index]->deq = cpu_to_le64(trb_64 | | |
388 | virt_dev->eps[ep_index].ring->cycle_state); | |
389 | } | |
390 | ||
391 | return xhci_configure_endpoints(udev, false); | |
392 | } | |
393 | ||
394 | /** | |
395 | * Issue an Address Device command (which will issue a SetAddress request to | |
396 | * the device). | |
397 | * | |
398 | * @param udev pointer to the Device Data Structure | |
399 | * @return 0 if successful else error code on failure | |
400 | */ | |
5dd75e3b | 401 | static int xhci_address_device(struct usb_device *udev, int root_portnr) |
5853e133 VG |
402 | { |
403 | int ret = 0; | |
7c1deec0 | 404 | struct xhci_ctrl *ctrl = xhci_get_ctrl(udev); |
5853e133 VG |
405 | struct xhci_slot_ctx *slot_ctx; |
406 | struct xhci_input_control_ctx *ctrl_ctx; | |
407 | struct xhci_virt_device *virt_dev; | |
408 | int slot_id = udev->slot_id; | |
409 | union xhci_trb *event; | |
410 | ||
411 | virt_dev = ctrl->devs[slot_id]; | |
412 | ||
413 | /* | |
414 | * This is the first Set Address since device plug-in | |
415 | * so setting up the slot context. | |
416 | */ | |
5dd75e3b SG |
417 | debug("Setting up addressable devices %p\n", ctrl->dcbaa); |
418 | xhci_setup_addressable_virt_dev(ctrl, udev->slot_id, udev->speed, | |
419 | root_portnr); | |
5853e133 VG |
420 | |
421 | ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx); | |
422 | ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG); | |
423 | ctrl_ctx->drop_flags = 0; | |
424 | ||
425 | xhci_queue_command(ctrl, (void *)ctrl_ctx, slot_id, 0, TRB_ADDR_DEV); | |
426 | event = xhci_wait_for_event(ctrl, TRB_COMPLETION); | |
427 | BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags)) != slot_id); | |
428 | ||
429 | switch (GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))) { | |
430 | case COMP_CTX_STATE: | |
431 | case COMP_EBADSLT: | |
432 | printf("Setup ERROR: address device command for slot %d.\n", | |
433 | slot_id); | |
434 | ret = -EINVAL; | |
435 | break; | |
436 | case COMP_TX_ERR: | |
437 | puts("Device not responding to set address.\n"); | |
438 | ret = -EPROTO; | |
439 | break; | |
440 | case COMP_DEV_ERR: | |
441 | puts("ERROR: Incompatible device" | |
442 | "for address device command.\n"); | |
443 | ret = -ENODEV; | |
444 | break; | |
445 | case COMP_SUCCESS: | |
446 | debug("Successful Address Device command\n"); | |
447 | udev->status = 0; | |
448 | break; | |
449 | default: | |
450 | printf("ERROR: unexpected command completion code 0x%x.\n", | |
451 | GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))); | |
452 | ret = -EINVAL; | |
453 | break; | |
454 | } | |
455 | ||
456 | xhci_acknowledge_event(ctrl); | |
457 | ||
458 | if (ret < 0) | |
459 | /* | |
460 | * TODO: Unsuccessful Address Device command shall leave the | |
461 | * slot in default state. So, issue Disable Slot command now. | |
462 | */ | |
463 | return ret; | |
464 | ||
421a5a0c ST |
465 | xhci_inval_cache((uintptr_t)virt_dev->out_ctx->bytes, |
466 | virt_dev->out_ctx->size); | |
5853e133 VG |
467 | slot_ctx = xhci_get_slot_ctx(ctrl, virt_dev->out_ctx); |
468 | ||
469 | debug("xHC internal address is: %d\n", | |
470 | le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK); | |
471 | ||
472 | return 0; | |
473 | } | |
474 | ||
475 | /** | |
476 | * Issue Enable slot command to the controller to allocate | |
477 | * device slot and assign the slot id. It fails if the xHC | |
478 | * ran out of device slots, the Enable Slot command timed out, | |
479 | * or allocating memory failed. | |
480 | * | |
481 | * @param udev pointer to the Device Data Structure | |
482 | * @return Returns 0 on succes else return error code on failure | |
483 | */ | |
121a4d13 | 484 | static int _xhci_alloc_device(struct usb_device *udev) |
5853e133 | 485 | { |
7c1deec0 | 486 | struct xhci_ctrl *ctrl = xhci_get_ctrl(udev); |
5853e133 | 487 | union xhci_trb *event; |
5853e133 VG |
488 | int ret; |
489 | ||
490 | /* | |
491 | * Root hub will be first device to be initailized. | |
492 | * If this device is root-hub, don't do any xHC related | |
493 | * stuff. | |
494 | */ | |
495 | if (ctrl->rootdev == 0) { | |
496 | udev->speed = USB_SPEED_SUPER; | |
497 | return 0; | |
498 | } | |
499 | ||
500 | xhci_queue_command(ctrl, NULL, 0, 0, TRB_ENABLE_SLOT); | |
501 | event = xhci_wait_for_event(ctrl, TRB_COMPLETION); | |
502 | BUG_ON(GET_COMP_CODE(le32_to_cpu(event->event_cmd.status)) | |
503 | != COMP_SUCCESS); | |
504 | ||
505 | udev->slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags)); | |
506 | ||
507 | xhci_acknowledge_event(ctrl); | |
508 | ||
7e0c5ee8 | 509 | ret = xhci_alloc_virt_device(ctrl, udev->slot_id); |
5853e133 VG |
510 | if (ret < 0) { |
511 | /* | |
512 | * TODO: Unsuccessful Address Device command shall leave | |
513 | * the slot in default. So, issue Disable Slot command now. | |
514 | */ | |
515 | puts("Could not allocate xHCI USB device data structures\n"); | |
516 | return ret; | |
517 | } | |
518 | ||
519 | return 0; | |
520 | } | |
521 | ||
a5762fe0 SG |
522 | #ifndef CONFIG_DM_USB |
523 | int usb_alloc_device(struct usb_device *udev) | |
524 | { | |
525 | return _xhci_alloc_device(udev); | |
526 | } | |
527 | #endif | |
528 | ||
5853e133 VG |
529 | /* |
530 | * Full speed devices may have a max packet size greater than 8 bytes, but the | |
531 | * USB core doesn't know that until it reads the first 8 bytes of the | |
532 | * descriptor. If the usb_device's max packet size changes after that point, | |
533 | * we need to issue an evaluate context command and wait on it. | |
534 | * | |
535 | * @param udev pointer to the Device Data Structure | |
536 | * @return returns the status of the xhci_configure_endpoints | |
537 | */ | |
538 | int xhci_check_maxpacket(struct usb_device *udev) | |
539 | { | |
7c1deec0 | 540 | struct xhci_ctrl *ctrl = xhci_get_ctrl(udev); |
5853e133 VG |
541 | unsigned int slot_id = udev->slot_id; |
542 | int ep_index = 0; /* control endpoint */ | |
543 | struct xhci_container_ctx *in_ctx; | |
544 | struct xhci_container_ctx *out_ctx; | |
545 | struct xhci_input_control_ctx *ctrl_ctx; | |
546 | struct xhci_ep_ctx *ep_ctx; | |
547 | int max_packet_size; | |
548 | int hw_max_packet_size; | |
549 | int ret = 0; | |
550 | struct usb_interface *ifdesc; | |
551 | ||
552 | ifdesc = &udev->config.if_desc[0]; | |
553 | ||
554 | out_ctx = ctrl->devs[slot_id]->out_ctx; | |
421a5a0c | 555 | xhci_inval_cache((uintptr_t)out_ctx->bytes, out_ctx->size); |
5853e133 VG |
556 | |
557 | ep_ctx = xhci_get_ep_ctx(ctrl, out_ctx, ep_index); | |
558 | hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2)); | |
559 | max_packet_size = usb_endpoint_maxp(&ifdesc->ep_desc[0]); | |
560 | if (hw_max_packet_size != max_packet_size) { | |
561 | debug("Max Packet Size for ep 0 changed.\n"); | |
562 | debug("Max packet size in usb_device = %d\n", max_packet_size); | |
563 | debug("Max packet size in xHCI HW = %d\n", hw_max_packet_size); | |
564 | debug("Issuing evaluate context command.\n"); | |
565 | ||
566 | /* Set up the modified control endpoint 0 */ | |
567 | xhci_endpoint_copy(ctrl, ctrl->devs[slot_id]->in_ctx, | |
568 | ctrl->devs[slot_id]->out_ctx, ep_index); | |
569 | in_ctx = ctrl->devs[slot_id]->in_ctx; | |
570 | ep_ctx = xhci_get_ep_ctx(ctrl, in_ctx, ep_index); | |
571 | ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK); | |
572 | ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size)); | |
573 | ||
574 | /* | |
575 | * Set up the input context flags for the command | |
576 | * FIXME: This won't work if a non-default control endpoint | |
577 | * changes max packet sizes. | |
578 | */ | |
579 | ctrl_ctx = xhci_get_input_control_ctx(in_ctx); | |
580 | ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG); | |
581 | ctrl_ctx->drop_flags = 0; | |
582 | ||
583 | ret = xhci_configure_endpoints(udev, true); | |
584 | } | |
585 | return ret; | |
586 | } | |
587 | ||
588 | /** | |
589 | * Clears the Change bits of the Port Status Register | |
590 | * | |
591 | * @param wValue request value | |
592 | * @param wIndex request index | |
593 | * @param addr address of posrt status register | |
594 | * @param port_status state of port status register | |
595 | * @return none | |
596 | */ | |
597 | static void xhci_clear_port_change_bit(u16 wValue, | |
598 | u16 wIndex, volatile uint32_t *addr, u32 port_status) | |
599 | { | |
600 | char *port_change_bit; | |
601 | u32 status; | |
602 | ||
603 | switch (wValue) { | |
604 | case USB_PORT_FEAT_C_RESET: | |
605 | status = PORT_RC; | |
606 | port_change_bit = "reset"; | |
607 | break; | |
608 | case USB_PORT_FEAT_C_CONNECTION: | |
609 | status = PORT_CSC; | |
610 | port_change_bit = "connect"; | |
611 | break; | |
612 | case USB_PORT_FEAT_C_OVER_CURRENT: | |
613 | status = PORT_OCC; | |
614 | port_change_bit = "over-current"; | |
615 | break; | |
616 | case USB_PORT_FEAT_C_ENABLE: | |
617 | status = PORT_PEC; | |
618 | port_change_bit = "enable/disable"; | |
619 | break; | |
620 | case USB_PORT_FEAT_C_SUSPEND: | |
621 | status = PORT_PLC; | |
622 | port_change_bit = "suspend/resume"; | |
623 | break; | |
624 | default: | |
625 | /* Should never happen */ | |
626 | return; | |
627 | } | |
628 | ||
629 | /* Change bits are all write 1 to clear */ | |
630 | xhci_writel(addr, port_status | status); | |
631 | ||
632 | port_status = xhci_readl(addr); | |
633 | debug("clear port %s change, actual port %d status = 0x%x\n", | |
634 | port_change_bit, wIndex, port_status); | |
635 | } | |
636 | ||
637 | /** | |
638 | * Save Read Only (RO) bits and save read/write bits where | |
639 | * writing a 0 clears the bit and writing a 1 sets the bit (RWS). | |
640 | * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect. | |
641 | * | |
642 | * @param state state of the Port Status and Control Regsiter | |
643 | * @return a value that would result in the port being in the | |
644 | * same state, if the value was written to the port | |
645 | * status control register. | |
646 | */ | |
647 | static u32 xhci_port_state_to_neutral(u32 state) | |
648 | { | |
649 | /* Save read-only status and port state */ | |
650 | return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS); | |
651 | } | |
652 | ||
653 | /** | |
654 | * Submits the Requests to the XHCI Host Controller | |
655 | * | |
656 | * @param udev pointer to the USB device structure | |
657 | * @param pipe contains the DIR_IN or OUT , devnum | |
658 | * @param buffer buffer to be read/written based on the request | |
659 | * @return returns 0 if successful else -1 on failure | |
660 | */ | |
661 | static int xhci_submit_root(struct usb_device *udev, unsigned long pipe, | |
662 | void *buffer, struct devrequest *req) | |
663 | { | |
664 | uint8_t tmpbuf[4]; | |
665 | u16 typeReq; | |
666 | void *srcptr = NULL; | |
667 | int len, srclen; | |
668 | uint32_t reg; | |
669 | volatile uint32_t *status_reg; | |
7c1deec0 | 670 | struct xhci_ctrl *ctrl = xhci_get_ctrl(udev); |
7274671e | 671 | struct xhci_hccr *hccr = ctrl->hccr; |
5853e133 | 672 | struct xhci_hcor *hcor = ctrl->hcor; |
7274671e | 673 | int max_ports = HCS_MAX_PORTS(xhci_readl(&hccr->cr_hcsparams1)); |
5853e133 | 674 | |
25d1936a | 675 | if ((req->requesttype & USB_RT_PORT) && |
7274671e BM |
676 | le16_to_cpu(req->index) > max_ports) { |
677 | printf("The request port(%d) exceeds maximum port number\n", | |
678 | le16_to_cpu(req->index) - 1); | |
5853e133 VG |
679 | return -EINVAL; |
680 | } | |
681 | ||
682 | status_reg = (volatile uint32_t *) | |
683 | (&hcor->portregs[le16_to_cpu(req->index) - 1].or_portsc); | |
684 | srclen = 0; | |
685 | ||
686 | typeReq = req->request | req->requesttype << 8; | |
687 | ||
688 | switch (typeReq) { | |
689 | case DeviceRequest | USB_REQ_GET_DESCRIPTOR: | |
690 | switch (le16_to_cpu(req->value) >> 8) { | |
691 | case USB_DT_DEVICE: | |
692 | debug("USB_DT_DEVICE request\n"); | |
693 | srcptr = &descriptor.device; | |
694 | srclen = 0x12; | |
695 | break; | |
696 | case USB_DT_CONFIG: | |
697 | debug("USB_DT_CONFIG config\n"); | |
698 | srcptr = &descriptor.config; | |
699 | srclen = 0x19; | |
700 | break; | |
701 | case USB_DT_STRING: | |
702 | debug("USB_DT_STRING config\n"); | |
703 | switch (le16_to_cpu(req->value) & 0xff) { | |
704 | case 0: /* Language */ | |
705 | srcptr = "\4\3\11\4"; | |
706 | srclen = 4; | |
707 | break; | |
708 | case 1: /* Vendor String */ | |
f161c178 | 709 | srcptr = "\16\3U\0-\0B\0o\0o\0t\0"; |
5853e133 VG |
710 | srclen = 14; |
711 | break; | |
712 | case 2: /* Product Name */ | |
713 | srcptr = "\52\3X\0H\0C\0I\0 " | |
714 | "\0H\0o\0s\0t\0 " | |
715 | "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0"; | |
716 | srclen = 42; | |
717 | break; | |
718 | default: | |
719 | printf("unknown value DT_STRING %x\n", | |
720 | le16_to_cpu(req->value)); | |
721 | goto unknown; | |
722 | } | |
723 | break; | |
724 | default: | |
725 | printf("unknown value %x\n", le16_to_cpu(req->value)); | |
726 | goto unknown; | |
727 | } | |
728 | break; | |
729 | case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8): | |
730 | switch (le16_to_cpu(req->value) >> 8) { | |
731 | case USB_DT_HUB: | |
f3421196 | 732 | case USB_DT_SS_HUB: |
5853e133 VG |
733 | debug("USB_DT_HUB config\n"); |
734 | srcptr = &descriptor.hub; | |
735 | srclen = 0x8; | |
736 | break; | |
737 | default: | |
738 | printf("unknown value %x\n", le16_to_cpu(req->value)); | |
739 | goto unknown; | |
740 | } | |
741 | break; | |
742 | case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8): | |
743 | debug("USB_REQ_SET_ADDRESS\n"); | |
744 | ctrl->rootdev = le16_to_cpu(req->value); | |
745 | break; | |
746 | case DeviceOutRequest | USB_REQ_SET_CONFIGURATION: | |
747 | /* Do nothing */ | |
748 | break; | |
749 | case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8): | |
750 | tmpbuf[0] = 1; /* USB_STATUS_SELFPOWERED */ | |
751 | tmpbuf[1] = 0; | |
752 | srcptr = tmpbuf; | |
753 | srclen = 2; | |
754 | break; | |
755 | case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8): | |
756 | memset(tmpbuf, 0, 4); | |
757 | reg = xhci_readl(status_reg); | |
758 | if (reg & PORT_CONNECT) { | |
759 | tmpbuf[0] |= USB_PORT_STAT_CONNECTION; | |
760 | switch (reg & DEV_SPEED_MASK) { | |
761 | case XDEV_FS: | |
762 | debug("SPEED = FULLSPEED\n"); | |
763 | break; | |
764 | case XDEV_LS: | |
765 | debug("SPEED = LOWSPEED\n"); | |
766 | tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8; | |
767 | break; | |
768 | case XDEV_HS: | |
769 | debug("SPEED = HIGHSPEED\n"); | |
770 | tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8; | |
771 | break; | |
772 | case XDEV_SS: | |
773 | debug("SPEED = SUPERSPEED\n"); | |
774 | tmpbuf[1] |= USB_PORT_STAT_SUPER_SPEED >> 8; | |
775 | break; | |
776 | } | |
777 | } | |
778 | if (reg & PORT_PE) | |
779 | tmpbuf[0] |= USB_PORT_STAT_ENABLE; | |
780 | if ((reg & PORT_PLS_MASK) == XDEV_U3) | |
781 | tmpbuf[0] |= USB_PORT_STAT_SUSPEND; | |
782 | if (reg & PORT_OC) | |
783 | tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT; | |
784 | if (reg & PORT_RESET) | |
785 | tmpbuf[0] |= USB_PORT_STAT_RESET; | |
786 | if (reg & PORT_POWER) | |
787 | /* | |
788 | * XXX: This Port power bit (for USB 3.0 hub) | |
789 | * we are faking in USB 2.0 hub port status; | |
790 | * since there's a change in bit positions in | |
791 | * two: | |
792 | * USB 2.0 port status PP is at position[8] | |
793 | * USB 3.0 port status PP is at position[9] | |
794 | * So, we are still keeping it at position [8] | |
795 | */ | |
796 | tmpbuf[1] |= USB_PORT_STAT_POWER >> 8; | |
797 | if (reg & PORT_CSC) | |
798 | tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION; | |
799 | if (reg & PORT_PEC) | |
800 | tmpbuf[2] |= USB_PORT_STAT_C_ENABLE; | |
801 | if (reg & PORT_OCC) | |
802 | tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT; | |
803 | if (reg & PORT_RC) | |
804 | tmpbuf[2] |= USB_PORT_STAT_C_RESET; | |
805 | ||
806 | srcptr = tmpbuf; | |
807 | srclen = 4; | |
808 | break; | |
809 | case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8): | |
810 | reg = xhci_readl(status_reg); | |
811 | reg = xhci_port_state_to_neutral(reg); | |
812 | switch (le16_to_cpu(req->value)) { | |
813 | case USB_PORT_FEAT_ENABLE: | |
814 | reg |= PORT_PE; | |
815 | xhci_writel(status_reg, reg); | |
816 | break; | |
817 | case USB_PORT_FEAT_POWER: | |
818 | reg |= PORT_POWER; | |
819 | xhci_writel(status_reg, reg); | |
820 | break; | |
821 | case USB_PORT_FEAT_RESET: | |
822 | reg |= PORT_RESET; | |
823 | xhci_writel(status_reg, reg); | |
824 | break; | |
825 | default: | |
826 | printf("unknown feature %x\n", le16_to_cpu(req->value)); | |
827 | goto unknown; | |
828 | } | |
829 | break; | |
830 | case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8): | |
831 | reg = xhci_readl(status_reg); | |
832 | reg = xhci_port_state_to_neutral(reg); | |
833 | switch (le16_to_cpu(req->value)) { | |
834 | case USB_PORT_FEAT_ENABLE: | |
835 | reg &= ~PORT_PE; | |
836 | break; | |
837 | case USB_PORT_FEAT_POWER: | |
838 | reg &= ~PORT_POWER; | |
839 | break; | |
840 | case USB_PORT_FEAT_C_RESET: | |
841 | case USB_PORT_FEAT_C_CONNECTION: | |
842 | case USB_PORT_FEAT_C_OVER_CURRENT: | |
843 | case USB_PORT_FEAT_C_ENABLE: | |
844 | xhci_clear_port_change_bit((le16_to_cpu(req->value)), | |
845 | le16_to_cpu(req->index), | |
846 | status_reg, reg); | |
847 | break; | |
848 | default: | |
849 | printf("unknown feature %x\n", le16_to_cpu(req->value)); | |
850 | goto unknown; | |
851 | } | |
852 | xhci_writel(status_reg, reg); | |
853 | break; | |
854 | default: | |
855 | puts("Unknown request\n"); | |
856 | goto unknown; | |
857 | } | |
858 | ||
859 | debug("scrlen = %d\n req->length = %d\n", | |
860 | srclen, le16_to_cpu(req->length)); | |
861 | ||
b4141195 | 862 | len = min(srclen, (int)le16_to_cpu(req->length)); |
5853e133 VG |
863 | |
864 | if (srcptr != NULL && len > 0) | |
865 | memcpy(buffer, srcptr, len); | |
866 | else | |
867 | debug("Len is 0\n"); | |
868 | ||
869 | udev->act_len = len; | |
870 | udev->status = 0; | |
871 | ||
872 | return 0; | |
873 | ||
874 | unknown: | |
875 | udev->act_len = 0; | |
876 | udev->status = USB_ST_STALLED; | |
877 | ||
878 | return -ENODEV; | |
879 | } | |
880 | ||
881 | /** | |
882 | * Submits the INT request to XHCI Host cotroller | |
883 | * | |
884 | * @param udev pointer to the USB device | |
885 | * @param pipe contains the DIR_IN or OUT , devnum | |
886 | * @param buffer buffer to be read/written based on the request | |
887 | * @param length length of the buffer | |
888 | * @param interval interval of the interrupt | |
889 | * @return 0 | |
890 | */ | |
a5762fe0 SG |
891 | static int _xhci_submit_int_msg(struct usb_device *udev, unsigned long pipe, |
892 | void *buffer, int length, int interval) | |
5853e133 VG |
893 | { |
894 | /* | |
895 | * TODO: Not addressing any interrupt type transfer requests | |
896 | * Add support for it later. | |
897 | */ | |
898 | return -EINVAL; | |
899 | } | |
900 | ||
901 | /** | |
902 | * submit the BULK type of request to the USB Device | |
903 | * | |
904 | * @param udev pointer to the USB device | |
905 | * @param pipe contains the DIR_IN or OUT , devnum | |
906 | * @param buffer buffer to be read/written based on the request | |
907 | * @param length length of the buffer | |
908 | * @return returns 0 if successful else -1 on failure | |
909 | */ | |
a5762fe0 SG |
910 | static int _xhci_submit_bulk_msg(struct usb_device *udev, unsigned long pipe, |
911 | void *buffer, int length) | |
5853e133 VG |
912 | { |
913 | if (usb_pipetype(pipe) != PIPE_BULK) { | |
914 | printf("non-bulk pipe (type=%lu)", usb_pipetype(pipe)); | |
915 | return -EINVAL; | |
916 | } | |
917 | ||
918 | return xhci_bulk_tx(udev, pipe, length, buffer); | |
919 | } | |
920 | ||
921 | /** | |
922 | * submit the control type of request to the Root hub/Device based on the devnum | |
923 | * | |
924 | * @param udev pointer to the USB device | |
925 | * @param pipe contains the DIR_IN or OUT , devnum | |
926 | * @param buffer buffer to be read/written based on the request | |
927 | * @param length length of the buffer | |
928 | * @param setup Request type | |
5dd75e3b | 929 | * @param root_portnr Root port number that this device is on |
5853e133 VG |
930 | * @return returns 0 if successful else -1 on failure |
931 | */ | |
5dd75e3b SG |
932 | static int _xhci_submit_control_msg(struct usb_device *udev, unsigned long pipe, |
933 | void *buffer, int length, | |
934 | struct devrequest *setup, int root_portnr) | |
5853e133 | 935 | { |
7c1deec0 | 936 | struct xhci_ctrl *ctrl = xhci_get_ctrl(udev); |
5853e133 VG |
937 | int ret = 0; |
938 | ||
939 | if (usb_pipetype(pipe) != PIPE_CONTROL) { | |
940 | printf("non-control pipe (type=%lu)", usb_pipetype(pipe)); | |
941 | return -EINVAL; | |
942 | } | |
943 | ||
944 | if (usb_pipedevice(pipe) == ctrl->rootdev) | |
945 | return xhci_submit_root(udev, pipe, buffer, setup); | |
946 | ||
1b108880 TC |
947 | if (setup->request == USB_REQ_SET_ADDRESS && |
948 | (setup->requesttype & USB_TYPE_MASK) == USB_TYPE_STANDARD) | |
5dd75e3b | 949 | return xhci_address_device(udev, root_portnr); |
5853e133 | 950 | |
1b108880 TC |
951 | if (setup->request == USB_REQ_SET_CONFIGURATION && |
952 | (setup->requesttype & USB_TYPE_MASK) == USB_TYPE_STANDARD) { | |
5853e133 VG |
953 | ret = xhci_set_configuration(udev); |
954 | if (ret) { | |
955 | puts("Failed to configure xHCI endpoint\n"); | |
956 | return ret; | |
957 | } | |
958 | } | |
959 | ||
960 | return xhci_ctrl_tx(udev, pipe, setup, length, buffer); | |
961 | } | |
962 | ||
779d1263 | 963 | static int xhci_lowlevel_init(struct xhci_ctrl *ctrl) |
5853e133 | 964 | { |
779d1263 SG |
965 | struct xhci_hccr *hccr; |
966 | struct xhci_hcor *hcor; | |
5853e133 VG |
967 | uint32_t val; |
968 | uint32_t val2; | |
969 | uint32_t reg; | |
5853e133 | 970 | |
779d1263 SG |
971 | hccr = ctrl->hccr; |
972 | hcor = ctrl->hcor; | |
5853e133 VG |
973 | /* |
974 | * Program the Number of Device Slots Enabled field in the CONFIG | |
975 | * register with the max value of slots the HC can handle. | |
976 | */ | |
977 | val = (xhci_readl(&hccr->cr_hcsparams1) & HCS_SLOTS_MASK); | |
978 | val2 = xhci_readl(&hcor->or_config); | |
979 | val |= (val2 & ~HCS_SLOTS_MASK); | |
980 | xhci_writel(&hcor->or_config, val); | |
981 | ||
982 | /* initializing xhci data structures */ | |
983 | if (xhci_mem_init(ctrl, hccr, hcor) < 0) | |
984 | return -ENOMEM; | |
985 | ||
986 | reg = xhci_readl(&hccr->cr_hcsparams1); | |
987 | descriptor.hub.bNbrPorts = ((reg & HCS_MAX_PORTS_MASK) >> | |
988 | HCS_MAX_PORTS_SHIFT); | |
989 | printf("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts); | |
990 | ||
991 | /* Port Indicators */ | |
992 | reg = xhci_readl(&hccr->cr_hccparams); | |
993 | if (HCS_INDICATOR(reg)) | |
994 | put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics) | |
995 | | 0x80, &descriptor.hub.wHubCharacteristics); | |
996 | ||
997 | /* Port Power Control */ | |
998 | if (HCC_PPC(reg)) | |
999 | put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics) | |
1000 | | 0x01, &descriptor.hub.wHubCharacteristics); | |
1001 | ||
1002 | if (xhci_start(hcor)) { | |
1003 | xhci_reset(hcor); | |
1004 | return -ENODEV; | |
1005 | } | |
1006 | ||
1007 | /* Zero'ing IRQ control register and IRQ pending register */ | |
1008 | xhci_writel(&ctrl->ir_set->irq_control, 0x0); | |
1009 | xhci_writel(&ctrl->ir_set->irq_pending, 0x0); | |
1010 | ||
1011 | reg = HC_VERSION(xhci_readl(&hccr->cr_capbase)); | |
1012 | printf("USB XHCI %x.%02x\n", reg >> 8, reg & 0xff); | |
1013 | ||
779d1263 SG |
1014 | return 0; |
1015 | } | |
1016 | ||
1017 | static int xhci_lowlevel_stop(struct xhci_ctrl *ctrl) | |
1018 | { | |
1019 | u32 temp; | |
1020 | ||
1021 | xhci_reset(ctrl->hcor); | |
1022 | ||
1023 | debug("// Disabling event ring interrupts\n"); | |
1024 | temp = xhci_readl(&ctrl->hcor->or_usbsts); | |
1025 | xhci_writel(&ctrl->hcor->or_usbsts, temp & ~STS_EINT); | |
1026 | temp = xhci_readl(&ctrl->ir_set->irq_pending); | |
1027 | xhci_writel(&ctrl->ir_set->irq_pending, ER_IRQ_DISABLE(temp)); | |
5853e133 VG |
1028 | |
1029 | return 0; | |
1030 | } | |
1031 | ||
a5762fe0 | 1032 | #ifndef CONFIG_DM_USB |
5dd75e3b SG |
1033 | int submit_control_msg(struct usb_device *udev, unsigned long pipe, |
1034 | void *buffer, int length, struct devrequest *setup) | |
1035 | { | |
1036 | struct usb_device *hop = udev; | |
1037 | ||
1038 | if (hop->parent) | |
1039 | while (hop->parent->parent) | |
1040 | hop = hop->parent; | |
1041 | ||
1042 | return _xhci_submit_control_msg(udev, pipe, buffer, length, setup, | |
1043 | hop->portnr); | |
1044 | } | |
1045 | ||
a5762fe0 SG |
1046 | int submit_bulk_msg(struct usb_device *udev, unsigned long pipe, void *buffer, |
1047 | int length) | |
1048 | { | |
1049 | return _xhci_submit_bulk_msg(udev, pipe, buffer, length); | |
1050 | } | |
1051 | ||
1052 | int submit_int_msg(struct usb_device *udev, unsigned long pipe, void *buffer, | |
1053 | int length, int interval) | |
1054 | { | |
1055 | return _xhci_submit_int_msg(udev, pipe, buffer, length, interval); | |
1056 | } | |
1057 | ||
779d1263 SG |
1058 | /** |
1059 | * Intialises the XHCI host controller | |
1060 | * and allocates the necessary data structures | |
1061 | * | |
1062 | * @param index index to the host controller data structure | |
1063 | * @return pointer to the intialised controller | |
1064 | */ | |
1065 | int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) | |
1066 | { | |
1067 | struct xhci_hccr *hccr; | |
1068 | struct xhci_hcor *hcor; | |
1069 | struct xhci_ctrl *ctrl; | |
1070 | int ret; | |
1071 | ||
a5ccda47 ST |
1072 | *controller = NULL; |
1073 | ||
779d1263 SG |
1074 | if (xhci_hcd_init(index, &hccr, (struct xhci_hcor **)&hcor) != 0) |
1075 | return -ENODEV; | |
1076 | ||
1077 | if (xhci_reset(hcor) != 0) | |
1078 | return -ENODEV; | |
1079 | ||
1080 | ctrl = &xhcic[index]; | |
1081 | ||
1082 | ctrl->hccr = hccr; | |
1083 | ctrl->hcor = hcor; | |
1084 | ||
1085 | ret = xhci_lowlevel_init(ctrl); | |
1086 | ||
a5ccda47 ST |
1087 | if (ret) { |
1088 | ctrl->hccr = NULL; | |
1089 | ctrl->hcor = NULL; | |
1090 | } else { | |
1091 | *controller = &xhcic[index]; | |
1092 | } | |
779d1263 SG |
1093 | |
1094 | return ret; | |
1095 | } | |
1096 | ||
5853e133 VG |
1097 | /** |
1098 | * Stops the XHCI host controller | |
1099 | * and cleans up all the related data structures | |
1100 | * | |
1101 | * @param index index to the host controller data structure | |
1102 | * @return none | |
1103 | */ | |
1104 | int usb_lowlevel_stop(int index) | |
1105 | { | |
1106 | struct xhci_ctrl *ctrl = (xhcic + index); | |
5853e133 | 1107 | |
a5ccda47 ST |
1108 | if (ctrl->hcor) { |
1109 | xhci_lowlevel_stop(ctrl); | |
1110 | xhci_hcd_stop(index); | |
1111 | xhci_cleanup(ctrl); | |
1112 | } | |
5853e133 VG |
1113 | |
1114 | return 0; | |
1115 | } | |
a5762fe0 SG |
1116 | #endif /* CONFIG_DM_USB */ |
1117 | ||
1118 | #ifdef CONFIG_DM_USB | |
a5762fe0 SG |
1119 | |
1120 | static int xhci_submit_control_msg(struct udevice *dev, struct usb_device *udev, | |
1121 | unsigned long pipe, void *buffer, int length, | |
1122 | struct devrequest *setup) | |
1123 | { | |
1124 | struct usb_device *uhop; | |
1125 | struct udevice *hub; | |
1126 | int root_portnr = 0; | |
1127 | ||
1128 | debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__, | |
1129 | dev->name, udev, udev->dev->name, udev->portnr); | |
1130 | hub = udev->dev; | |
1131 | if (device_get_uclass_id(hub) == UCLASS_USB_HUB) { | |
1132 | /* Figure out our port number on the root hub */ | |
46c1d493 | 1133 | if (usb_hub_is_root_hub(hub)) { |
a5762fe0 SG |
1134 | root_portnr = udev->portnr; |
1135 | } else { | |
46c1d493 | 1136 | while (!usb_hub_is_root_hub(hub->parent)) |
a5762fe0 | 1137 | hub = hub->parent; |
bcbe3d15 | 1138 | uhop = dev_get_parent_priv(hub); |
a5762fe0 SG |
1139 | root_portnr = uhop->portnr; |
1140 | } | |
1141 | } | |
1142 | /* | |
1143 | struct usb_device *hop = udev; | |
1144 | ||
1145 | if (hop->parent) | |
1146 | while (hop->parent->parent) | |
1147 | hop = hop->parent; | |
1148 | */ | |
1149 | return _xhci_submit_control_msg(udev, pipe, buffer, length, setup, | |
1150 | root_portnr); | |
1151 | } | |
1152 | ||
1153 | static int xhci_submit_bulk_msg(struct udevice *dev, struct usb_device *udev, | |
1154 | unsigned long pipe, void *buffer, int length) | |
1155 | { | |
1156 | debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev); | |
1157 | return _xhci_submit_bulk_msg(udev, pipe, buffer, length); | |
1158 | } | |
1159 | ||
1160 | static int xhci_submit_int_msg(struct udevice *dev, struct usb_device *udev, | |
1161 | unsigned long pipe, void *buffer, int length, | |
1162 | int interval) | |
1163 | { | |
1164 | debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev); | |
1165 | return _xhci_submit_int_msg(udev, pipe, buffer, length, interval); | |
1166 | } | |
1167 | ||
1168 | static int xhci_alloc_device(struct udevice *dev, struct usb_device *udev) | |
1169 | { | |
1170 | debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev); | |
1171 | return _xhci_alloc_device(udev); | |
1172 | } | |
1173 | ||
1174 | int xhci_register(struct udevice *dev, struct xhci_hccr *hccr, | |
1175 | struct xhci_hcor *hcor) | |
1176 | { | |
1177 | struct xhci_ctrl *ctrl = dev_get_priv(dev); | |
1178 | struct usb_bus_priv *priv = dev_get_uclass_priv(dev); | |
1179 | int ret; | |
1180 | ||
1181 | debug("%s: dev='%s', ctrl=%p, hccr=%p, hcor=%p\n", __func__, dev->name, | |
1182 | ctrl, hccr, hcor); | |
1183 | ||
1184 | ctrl->dev = dev; | |
1185 | ||
1186 | /* | |
1187 | * XHCI needs to issue a Address device command to setup | |
1188 | * proper device context structures, before it can interact | |
1189 | * with the device. So a get_descriptor will fail before any | |
1190 | * of that is done for XHCI unlike EHCI. | |
1191 | */ | |
1192 | priv->desc_before_addr = false; | |
1193 | ||
1194 | ret = xhci_reset(hcor); | |
1195 | if (ret) | |
1196 | goto err; | |
1197 | ||
1198 | ctrl->hccr = hccr; | |
1199 | ctrl->hcor = hcor; | |
1200 | ret = xhci_lowlevel_init(ctrl); | |
1201 | if (ret) | |
1202 | goto err; | |
1203 | ||
1204 | return 0; | |
1205 | err: | |
1206 | free(ctrl); | |
1207 | debug("%s: failed, ret=%d\n", __func__, ret); | |
1208 | return ret; | |
1209 | } | |
1210 | ||
1211 | int xhci_deregister(struct udevice *dev) | |
1212 | { | |
1213 | struct xhci_ctrl *ctrl = dev_get_priv(dev); | |
1214 | ||
1215 | xhci_lowlevel_stop(ctrl); | |
1216 | xhci_cleanup(ctrl); | |
1217 | ||
1218 | return 0; | |
1219 | } | |
1220 | ||
1221 | struct dm_usb_ops xhci_usb_ops = { | |
1222 | .control = xhci_submit_control_msg, | |
1223 | .bulk = xhci_submit_bulk_msg, | |
1224 | .interrupt = xhci_submit_int_msg, | |
1225 | .alloc_device = xhci_alloc_device, | |
1226 | }; | |
1227 | ||
1228 | #endif |