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1 | /* |
2 | * Blackfin MUSB HCD (Host Controller Driver) for u-boot | |
3 | * | |
4 | * Copyright (c) 2008-2009 Analog Devices Inc. | |
5 | * | |
6 | * Licensed under the GPL-2 or later. | |
7 | */ | |
8 | ||
9 | #ifndef __BLACKFIN_USB_H__ | |
10 | #define __BLACKFIN_USB_H__ | |
11 | ||
12 | #include <linux/types.h> | |
13 | ||
14 | /* Every register is 32bit aligned, but only 16bits in size */ | |
15 | #define ureg(name) u16 name; u16 __pad_##name; | |
16 | ||
17 | #define musb_regs musb_regs | |
18 | struct musb_regs { | |
19 | /* common registers */ | |
20 | ureg(faddr) | |
21 | ureg(power) | |
22 | ureg(intrtx) | |
23 | ureg(intrrx) | |
24 | ureg(intrtxe) | |
25 | ureg(intrrxe) | |
26 | ureg(intrusb) | |
27 | ureg(intrusbe) | |
28 | ureg(frame) | |
29 | ureg(index) | |
30 | ureg(testmode) | |
31 | ureg(globintr) | |
32 | ureg(global_ctl) | |
33 | u32 reserved0[3]; | |
34 | /* indexed registers */ | |
35 | ureg(txmaxp) | |
36 | ureg(txcsr) | |
37 | ureg(rxmaxp) | |
38 | ureg(rxcsr) | |
39 | ureg(rxcount) | |
40 | ureg(txtype) | |
41 | ureg(txinterval) | |
42 | ureg(rxtype) | |
43 | ureg(rxinterval) | |
44 | u32 reserved1; | |
45 | ureg(txcount) | |
46 | u32 reserved2[5]; | |
47 | /* fifo */ | |
48 | u16 fifox[32]; | |
49 | /* OTG, dynamic FIFO, version & vendor registers */ | |
50 | u32 reserved3[16]; | |
51 | ureg(devctl) | |
52 | ureg(vbus_irq) | |
53 | ureg(vbus_mask) | |
54 | u32 reserved4[15]; | |
55 | ureg(linkinfo) | |
56 | ureg(vplen) | |
57 | ureg(hseof1) | |
58 | ureg(fseof1) | |
59 | ureg(lseof1) | |
60 | u32 reserved5[41]; | |
61 | /* target address registers */ | |
62 | struct musb_tar_regs { | |
63 | ureg(txmaxp) | |
64 | ureg(txcsr) | |
65 | ureg(rxmaxp) | |
66 | ureg(rxcsr) | |
67 | ureg(rxcount) | |
68 | ureg(txtype) | |
69 | ureg(txinternal) | |
70 | ureg(rxtype) | |
71 | ureg(rxinternal) | |
72 | u32 reserved6; | |
73 | ureg(txcount) | |
74 | u32 reserved7[5]; | |
75 | } tar[8]; | |
76 | } __attribute__((packed)); | |
77 | ||
78 | struct bfin_musb_dma_regs { | |
79 | ureg(interrupt); | |
80 | ureg(control); | |
81 | ureg(addr_low); | |
82 | ureg(addr_high); | |
83 | ureg(count_low); | |
84 | ureg(count_high); | |
ec2aadb4 | 85 | u32 reserved0[2]; |
e608f221 BW |
86 | }; |
87 | ||
88 | #undef ureg | |
89 | ||
90 | /* EP5-EP7 are the only ones with 1024 byte FIFOs which BULK really needs */ | |
91 | #define MUSB_BULK_EP 5 | |
92 | ||
93 | /* Blackfin FIFO's are static */ | |
94 | #define MUSB_NO_DYNAMIC_FIFO | |
95 | ||
96 | /* No HUB support :( */ | |
97 | #define MUSB_NO_MULTIPOINT | |
98 | ||
99 | #endif |