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[people/ms/u-boot.git] / drivers / usb / musb / musb_hcd.c
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a1428969
TA		 1/*
2 * Mentor USB OTG Core host controller driver.
3 *
4 * Copyright (c) 2008 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19 * MA 02111-1307 USA
20 *
21 * Author: Thomas Abraham t-abraham@ti.com, Texas Instruments
22 */
23
24#include <common.h>
25#include "musb_hcd.h"
26
27/* MSC control transfers */
28#define USB_MSC_BBB_RESET 0xFF
29#define USB_MSC_BBB_GET_MAX_LUN 0xFE
30
31/* Endpoint configuration information */
32static struct musb_epinfo epinfo[3] = {
33 {MUSB_BULK_EP, 1, 512}, /* EP1 - Bluk Out - 512 Bytes */
34 {MUSB_BULK_EP, 0, 512}, /* EP1 - Bluk In - 512 Bytes */
35 {MUSB_INTR_EP, 0, 64} /* EP2 - Interrupt IN - 64 Bytes */
36};
37
38/*
39 * This function writes the data toggle value.
40 */
41static void write_toggle(struct usb_device *dev, u8 ep, u8 dir_out)
42{
43 u16 toggle = usb_gettoggle(dev, ep, dir_out);
44 u16 csr;
45
46 if (dir_out) {
47 if (!toggle)
48 writew(MUSB_TXCSR_CLRDATATOG, &musbr->txcsr);
49 else {
50 csr = readw(&musbr->txcsr);
51 csr |= MUSB_TXCSR_H_WR_DATATOGGLE;
52 writew(csr, &musbr->txcsr);
53 csr |= (toggle << MUSB_TXCSR_H_DATATOGGLE_SHIFT);
54 writew(csr, &musbr->txcsr);
55 }
56 } else {
57 if (!toggle)
58 writew(MUSB_RXCSR_CLRDATATOG, &musbr->rxcsr);
59 else {
60 csr = readw(&musbr->rxcsr);
61 csr |= MUSB_RXCSR_H_WR_DATATOGGLE;
62 writew(csr, &musbr->rxcsr);
63 csr |= (toggle << MUSB_S_RXCSR_H_DATATOGGLE);
64 writew(csr, &musbr->rxcsr);
65 }
66 }
67}
68
69/*
70 * This function checks if RxStall has occured on the endpoint. If a RxStall
71 * has occured, the RxStall is cleared and 1 is returned. If RxStall has
72 * not occured, 0 is returned.
73 */
74static u8 check_stall(u8 ep, u8 dir_out)
75{
76 u16 csr;
77
78 /* For endpoint 0 */
79 if (!ep) {
80 csr = readw(&musbr->txcsr);
81 if (csr & MUSB_CSR0_H_RXSTALL) {
82 csr &= ~MUSB_CSR0_H_RXSTALL;
83 writew(csr, &musbr->txcsr);
84 return 1;
85 }
86 } else { /* For non-ep0 */
87 if (dir_out) { /* is it tx ep */
88 csr = readw(&musbr->txcsr);
89 if (csr & MUSB_TXCSR_H_RXSTALL) {
90 csr &= ~MUSB_TXCSR_H_RXSTALL;
91 writew(csr, &musbr->txcsr);
92 return 1;
93 }
94 } else { /* is it rx ep */
95 csr = readw(&musbr->rxcsr);
96 if (csr & MUSB_RXCSR_H_RXSTALL) {
97 csr &= ~MUSB_RXCSR_H_RXSTALL;
98 writew(csr, &musbr->rxcsr);
99 return 1;
100 }
101 }
102 }
103 return 0;
104}
105
106/*
107 * waits until ep0 is ready. Returns 0 if ep is ready, -1 for timeout
108 * error and -2 for stall.
109 */
110static int wait_until_ep0_ready(struct usb_device *dev, u32 bit_mask)
111{
112 u16 csr;
113 int result = 1;
114
115 while (result > 0) {
116 csr = readw(&musbr->txcsr);
117 if (csr & MUSB_CSR0_H_ERROR) {
118 csr &= ~MUSB_CSR0_H_ERROR;
119 writew(csr, &musbr->txcsr);
120 dev->status = USB_ST_CRC_ERR;
121 result = -1;
122 break;
123 }
124
125 switch (bit_mask) {
126 case MUSB_CSR0_TXPKTRDY:
127 if (!(csr & MUSB_CSR0_TXPKTRDY)) {
128 if (check_stall(MUSB_CONTROL_EP, 0)) {
129 dev->status = USB_ST_STALLED;
130 result = -2;
131 } else
132 result = 0;
133 }
134 break;
135
136 case MUSB_CSR0_RXPKTRDY:
137 if (check_stall(MUSB_CONTROL_EP, 0)) {
138 dev->status = USB_ST_STALLED;
139 result = -2;
140 } else
141 if (csr & MUSB_CSR0_RXPKTRDY)
142 result = 0;
143 break;
144
145 case MUSB_CSR0_H_REQPKT:
146 if (!(csr & MUSB_CSR0_H_REQPKT)) {
147 if (check_stall(MUSB_CONTROL_EP, 0)) {
148 dev->status = USB_ST_STALLED;
149 result = -2;
150 } else
151 result = 0;
152 }
153 break;
154 }
155 }
156 return result;
157}
158
159/*
160 * waits until tx ep is ready. Returns 1 when ep is ready and 0 on error.
161 */
162static u8 wait_until_txep_ready(struct usb_device *dev, u8 ep)
163{
164 u16 csr;
165
166 do {
167 if (check_stall(ep, 1)) {
168 dev->status = USB_ST_STALLED;
169 return 0;
170 }
171
172 csr = readw(&musbr->txcsr);
173 if (csr & MUSB_TXCSR_H_ERROR) {
174 dev->status = USB_ST_CRC_ERR;
175 return 0;
176 }
177 } while (csr & MUSB_TXCSR_TXPKTRDY);
178 return 1;
179}
180
181/*
182 * waits until rx ep is ready. Returns 1 when ep is ready and 0 on error.
183 */
184static u8 wait_until_rxep_ready(struct usb_device *dev, u8 ep)
185{
186 u16 csr;
187
188 do {
189 if (check_stall(ep, 0)) {
190 dev->status = USB_ST_STALLED;
191 return 0;
192 }
193
194 csr = readw(&musbr->rxcsr);
195 if (csr & MUSB_RXCSR_H_ERROR) {
196 dev->status = USB_ST_CRC_ERR;
197 return 0;
198 }
199 } while (!(csr & MUSB_RXCSR_RXPKTRDY));
200 return 1;
201}
202
203/*
204 * This function performs the setup phase of the control transfer
205 */
206static int ctrlreq_setup_phase(struct usb_device *dev, struct devrequest *setup)
207{
208 int result;
209 u16 csr;
210
211 /* write the control request to ep0 fifo */
212 write_fifo(MUSB_CONTROL_EP, sizeof(struct devrequest), (void *)setup);
213
214 /* enable transfer of setup packet */
215 csr = readw(&musbr->txcsr);
216 csr |= (MUSB_CSR0_TXPKTRDY|MUSB_CSR0_H_SETUPPKT);
217 writew(csr, &musbr->txcsr);
218
219 /* wait until the setup packet is transmitted */
220 result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY);
221 dev->act_len = 0;
222 return result;
223}
224
225/*
226 * This function handles the control transfer in data phase
227 */
228static int ctrlreq_in_data_phase(struct usb_device *dev, u32 len, void *buffer)
229{
230 u16 csr;
231 u32 rxlen = 0;
232 u32 nextlen = 0;
233 u8 maxpktsize = (1 << dev->maxpacketsize) * 8;
234 u8 *rxbuff = (u8 *)buffer;
235 u8 rxedlength;
236 int result;
237
238 while (rxlen < len) {
239 /* Determine the next read length */
240 nextlen = ((len-rxlen) > maxpktsize) ? maxpktsize : (len-rxlen);
241
242 /* Set the ReqPkt bit */
243 csr = readw(&musbr->txcsr);
244 writew(csr | MUSB_CSR0_H_REQPKT, &musbr->txcsr);
245 result = wait_until_ep0_ready(dev, MUSB_CSR0_RXPKTRDY);
246 if (result < 0)
247 return result;
248
249 /* Actual number of bytes received by usb */
250 rxedlength = readb(&musbr->rxcount);
251
252 /* Read the data from the RxFIFO */
253 read_fifo(MUSB_CONTROL_EP, rxedlength, &rxbuff[rxlen]);
254
255 /* Clear the RxPktRdy Bit */
256 csr = readw(&musbr->txcsr);
257 csr &= ~MUSB_CSR0_RXPKTRDY;
258 writew(csr, &musbr->txcsr);
259
260 /* short packet? */
261 if (rxedlength != nextlen) {
262 dev->act_len += rxedlength;
263 break;
264 }
265 rxlen += nextlen;
266 dev->act_len = rxlen;
267 }
268 return 0;
269}
270
271/*
272 * This function handles the control transfer out data phase
273 */
274static int ctrlreq_out_data_phase(struct usb_device *dev, u32 len, void *buffer)
275{
276 u16 csr;
277 u32 txlen = 0;
278 u32 nextlen = 0;
279 u8 maxpktsize = (1 << dev->maxpacketsize) * 8;
280 u8 *txbuff = (u8 *)buffer;
281 int result = 0;
282
283 while (txlen < len) {
284 /* Determine the next write length */
285 nextlen = ((len-txlen) > maxpktsize) ? maxpktsize : (len-txlen);
286
287 /* Load the data to send in FIFO */
288 write_fifo(MUSB_CONTROL_EP, txlen, &txbuff[txlen]);
289
290 /* Set TXPKTRDY bit */
291 csr = readw(&musbr->txcsr);
292 writew(csr | MUSB_CSR0_H_DIS_PING | MUSB_CSR0_TXPKTRDY,
293 &musbr->txcsr);
294 result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY);
295 if (result < 0)
296 break;
297
298 txlen += nextlen;
299 dev->act_len = txlen;
300 }
301 return result;
302}
303
304/*
305 * This function handles the control transfer out status phase
306 */
307static int ctrlreq_out_status_phase(struct usb_device *dev)
308{
309 u16 csr;
310 int result;
311
312 /* Set the StatusPkt bit */
313 csr = readw(&musbr->txcsr);
314 csr |= (MUSB_CSR0_H_DIS_PING | MUSB_CSR0_TXPKTRDY |
315 MUSB_CSR0_H_STATUSPKT);
316 writew(csr, &musbr->txcsr);
317
318 /* Wait until TXPKTRDY bit is cleared */
319 result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY);
320 return result;
321}
322
323/*
324 * This function handles the control transfer in status phase
325 */
326static int ctrlreq_in_status_phase(struct usb_device *dev)
327{
328 u16 csr;
329 int result;
330
331 /* Set the StatusPkt bit and ReqPkt bit */
332 csr = MUSB_CSR0_H_DIS_PING | MUSB_CSR0_H_REQPKT | MUSB_CSR0_H_STATUSPKT;
333 writew(csr, &musbr->txcsr);
334 result = wait_until_ep0_ready(dev, MUSB_CSR0_H_REQPKT);
335
336 /* clear StatusPkt bit and RxPktRdy bit */
337 csr = readw(&musbr->txcsr);
338 csr &= ~(MUSB_CSR0_RXPKTRDY | MUSB_CSR0_H_STATUSPKT);
339 writew(csr, &musbr->txcsr);
340 return result;
341}
342
343/*
344 * determines the speed of the device (High/Full/Slow)
345 */
346static u8 get_dev_speed(struct usb_device *dev)
347{
348 return (dev->speed & USB_SPEED_HIGH) ? MUSB_TYPE_SPEED_HIGH :
349 ((dev->speed & USB_SPEED_LOW) ? MUSB_TYPE_SPEED_LOW :
350 MUSB_TYPE_SPEED_FULL);
351}
352
353/*
354 * configure the hub address and the port address.
355 */
356static void config_hub_port(struct usb_device *dev, u8 ep)
357{
358 u8 chid;
359 u8 hub;
360
361 /* Find out the nearest parent which is high speed */
362 while (dev->parent->parent != NULL)
363 if (get_dev_speed(dev->parent) != MUSB_TYPE_SPEED_HIGH)
364 dev = dev->parent;
365 else
366 break;
367
368 /* determine the port address at that hub */
369 hub = dev->parent->devnum;
370 for (chid = 0; chid < USB_MAXCHILDREN; chid++)
371 if (dev->parent->children[chid] == dev)
372 break;
373
374 /* configure the hub address and the port address */
375 writeb(hub, &musbr->tar[ep].txhubaddr);
376 writeb((chid + 1), &musbr->tar[ep].txhubport);
377 writeb(hub, &musbr->tar[ep].rxhubaddr);
378 writeb((chid + 1), &musbr->tar[ep].rxhubport);
379}
380
381/*
382 * do a control transfer
383 */
384int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
385 int len, struct devrequest *setup)
386{
387 int devnum = usb_pipedevice(pipe);
388 u16 csr;
389 u8 devspeed;
390
391 /* select control endpoint */
392 writeb(MUSB_CONTROL_EP, &musbr->index);
393 csr = readw(&musbr->txcsr);
394
395 /* target addr and (for multipoint) hub addr/port */
396 writeb(devnum, &musbr->tar[MUSB_CONTROL_EP].txfuncaddr);
397 writeb(devnum, &musbr->tar[MUSB_CONTROL_EP].rxfuncaddr);
398
399 /* configure the hub address and the port number as required */
400 devspeed = get_dev_speed(dev);
401 if ((musb_ishighspeed()) && (dev->parent != NULL) &&
402 (devspeed != MUSB_TYPE_SPEED_HIGH)) {
403 config_hub_port(dev, MUSB_CONTROL_EP);
404 writeb(devspeed << 6, &musbr->txtype);
405 } else {
406 writeb(musb_cfg.musb_speed << 6, &musbr->txtype);
407 writeb(0, &musbr->tar[MUSB_CONTROL_EP].txhubaddr);
408 writeb(0, &musbr->tar[MUSB_CONTROL_EP].txhubport);
409 writeb(0, &musbr->tar[MUSB_CONTROL_EP].rxhubaddr);
410 writeb(0, &musbr->tar[MUSB_CONTROL_EP].rxhubport);
411 }
412
413 /* Control transfer setup phase */
414 if (ctrlreq_setup_phase(dev, setup) < 0)
415 return 0;
416
417 switch (setup->request) {
418 case USB_REQ_GET_DESCRIPTOR:
419 case USB_REQ_GET_CONFIGURATION:
420 case USB_REQ_GET_INTERFACE:
421 case USB_REQ_GET_STATUS:
422 case USB_MSC_BBB_GET_MAX_LUN:
423 /* control transfer in-data-phase */
424 if (ctrlreq_in_data_phase(dev, len, buffer) < 0)
425 return 0;
426 /* control transfer out-status-phase */
427 if (ctrlreq_out_status_phase(dev) < 0)
428 return 0;
429 break;
430
431 case USB_REQ_SET_ADDRESS:
432 case USB_REQ_SET_CONFIGURATION:
433 case USB_REQ_SET_FEATURE:
434 case USB_REQ_SET_INTERFACE:
435 case USB_REQ_CLEAR_FEATURE:
436 case USB_MSC_BBB_RESET:
437 /* control transfer in status phase */
438 if (ctrlreq_in_status_phase(dev) < 0)
439 return 0;
440 break;
441
442 case USB_REQ_SET_DESCRIPTOR:
443 /* control transfer out data phase */
444 if (ctrlreq_out_data_phase(dev, len, buffer) < 0)
445 return 0;
446 /* control transfer in status phase */
447 if (ctrlreq_in_status_phase(dev) < 0)
448 return 0;
449 break;
450
451 default:
452 /* unhandled control transfer */
453 return -1;
454 }
455
456 dev->status = 0;
457 dev->act_len = len;
458 return len;
459}
460
461/*
462 * do a bulk transfer
463 */
464int submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
465 void *buffer, int len)
466{
467 int dir_out = usb_pipeout(pipe);
468 int ep = usb_pipeendpoint(pipe);
469 int devnum = usb_pipedevice(pipe);
470 u8 type;
471 u16 csr;
472 u32 txlen = 0;
473 u32 nextlen = 0;
474 u8 devspeed;
475
476 /* select bulk endpoint */
477 writeb(MUSB_BULK_EP, &musbr->index);
478
479 /* write the address of the device */
480 if (dir_out)
481 writeb(devnum, &musbr->tar[MUSB_BULK_EP].txfuncaddr);
482 else
483 writeb(devnum, &musbr->tar[MUSB_BULK_EP].rxfuncaddr);
484
485 /* configure the hub address and the port number as required */
486 devspeed = get_dev_speed(dev);
487 if ((musb_ishighspeed()) && (dev->parent != NULL) &&
488 (devspeed != MUSB_TYPE_SPEED_HIGH)) {
489 /*
490 * MUSB is in high speed and the destination device is full
491 * speed device. So configure the hub address and port
492 * address registers.
493 */
494 config_hub_port(dev, MUSB_BULK_EP);
495 } else {
496 if (dir_out) {
497 writeb(0, &musbr->tar[MUSB_BULK_EP].txhubaddr);
498 writeb(0, &musbr->tar[MUSB_BULK_EP].txhubport);
499 } else {
500 writeb(0, &musbr->tar[MUSB_BULK_EP].rxhubaddr);
501 writeb(0, &musbr->tar[MUSB_BULK_EP].rxhubport);
502 }
503 devspeed = musb_cfg.musb_speed;
504 }
505
506 /* Write the saved toggle bit value */
507 write_toggle(dev, ep, dir_out);
508
509 if (dir_out) { /* bulk-out transfer */
510 /* Program the TxType register */
511 type = (devspeed << MUSB_TYPE_SPEED_SHIFT) |
512 (MUSB_TYPE_PROTO_BULK << MUSB_TYPE_PROTO_SHIFT) |
513 (ep & MUSB_TYPE_REMOTE_END);
514 writeb(type, &musbr->txtype);
515
516 /* Write maximum packet size to the TxMaxp register */
517 writew(dev->epmaxpacketout[ep], &musbr->txmaxp);
518 while (txlen < len) {
519 nextlen = ((len-txlen) < dev->epmaxpacketout[ep]) ?
520 (len-txlen) : dev->epmaxpacketout[ep];
521
522 /* Write the data to the FIFO */
523 write_fifo(MUSB_BULK_EP, nextlen,
524 (void *)(((u8 *)buffer) + txlen));
525
526 /* Set the TxPktRdy bit */
527 csr = readw(&musbr->txcsr);
528 writew(csr | MUSB_TXCSR_TXPKTRDY, &musbr->txcsr);
529
530 /* Wait until the TxPktRdy bit is cleared */
531 if (!wait_until_txep_ready(dev, MUSB_BULK_EP)) {
532 readw(&musbr->txcsr);
533 usb_settoggle(dev, ep, dir_out,
534 (csr >> MUSB_TXCSR_H_DATATOGGLE_SHIFT) & 1);
535 dev->act_len = txlen;
536 return 0;
537 }
538 txlen += nextlen;
539 }
540
541 /* Keep a copy of the data toggle bit */
542 csr = readw(&musbr->txcsr);
543 usb_settoggle(dev, ep, dir_out,
544 (csr >> MUSB_TXCSR_H_DATATOGGLE_SHIFT) & 1);
545 } else { /* bulk-in transfer */
546 /* Write the saved toggle bit value */
547 write_toggle(dev, ep, dir_out);
548
549 /* Program the RxType register */
550 type = (devspeed << MUSB_TYPE_SPEED_SHIFT) |
551 (MUSB_TYPE_PROTO_BULK << MUSB_TYPE_PROTO_SHIFT) |
552 (ep & MUSB_TYPE_REMOTE_END);
553 writeb(type, &musbr->rxtype);
554
555 /* Write the maximum packet size to the RxMaxp register */
556 writew(dev->epmaxpacketin[ep], &musbr->rxmaxp);
557 while (txlen < len) {
558 nextlen = ((len-txlen) < dev->epmaxpacketin[ep]) ?
559 (len-txlen) : dev->epmaxpacketin[ep];
560
561 /* Set the ReqPkt bit */
562 writew(MUSB_RXCSR_H_REQPKT, &musbr->rxcsr);
563
564 /* Wait until the RxPktRdy bit is set */
565 if (!wait_until_rxep_ready(dev, MUSB_BULK_EP)) {
566 csr = readw(&musbr->rxcsr);
567 usb_settoggle(dev, ep, dir_out,
568 (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1);
569 csr &= ~MUSB_RXCSR_RXPKTRDY;
570 writew(csr, &musbr->rxcsr);
571 dev->act_len = txlen;
572 return 0;
573 }
574
575 /* Read the data from the FIFO */
576 read_fifo(MUSB_BULK_EP, nextlen,
577 (void *)(((u8 *)buffer) + txlen));
578
579 /* Clear the RxPktRdy bit */
580 csr = readw(&musbr->rxcsr);
581 csr &= ~MUSB_RXCSR_RXPKTRDY;
582 writew(csr, &musbr->rxcsr);
583 txlen += nextlen;
584 }
585
586 /* Keep a copy of the data toggle bit */
587 csr = readw(&musbr->rxcsr);
588 usb_settoggle(dev, ep, dir_out,
589 (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1);
590 }
591
592 /* bulk transfer is complete */
593 dev->status = 0;
594 dev->act_len = len;
595 return 0;
596}
597
598/*
599 * This function initializes the usb controller module.
600 */
601int usb_lowlevel_init(void)
602{
603 u8 power;
604 u32 timeout;
605
606 if (musb_platform_init() == -1)
607 return -1;
608
609 /* Configure all the endpoint FIFO's and start usb controller */
610 musbr = musb_cfg.regs;
611 musb_configure_ep(&epinfo[0],
612 sizeof(epinfo) / sizeof(struct musb_epinfo));
613 musb_start();
614
615 /*
616 * Wait until musb is enabled in host mode with a timeout. There
617 * should be a usb device connected.
618 */
619 timeout = musb_cfg.timeout;
620 while (timeout--)
621 if (readb(&musbr->devctl) & MUSB_DEVCTL_HM)
622 break;
623
624 /* if musb core is not in host mode, then return */
625 if (!timeout)
626 return -1;
627
628 /* start usb bus reset */
629 power = readb(&musbr->power);
630 writeb(power | MUSB_POWER_RESET, &musbr->power);
631
632 /* After initiating a usb reset, wait for about 20ms to 30ms */
633 udelay(30000);
634
635 /* stop usb bus reset */
636 power = readb(&musbr->power);
637 power &= ~MUSB_POWER_RESET;
638 writeb(power, &musbr->power);
639
640 /* Determine if the connected device is a high/full/low speed device */
641 musb_cfg.musb_speed = (readb(&musbr->power) & MUSB_POWER_HSMODE) ?
642 MUSB_TYPE_SPEED_HIGH :
643 ((readb(&musbr->devctl) & MUSB_DEVCTL_FSDEV) ?
644 MUSB_TYPE_SPEED_FULL : MUSB_TYPE_SPEED_LOW);
645 return 0;
646}
647
648/*
649 * This function stops the operation of the davinci usb module.
650 */
651int usb_lowlevel_stop(void)
652{
653 /* Reset the USB module */
654 musb_platform_deinit();
655 writeb(0, &musbr->devctl);
656 return 0;
657}
658
659/*
660 * This function supports usb interrupt transfers. Currently, usb interrupt
661 * transfers are not supported.
662 */
663int submit_int_msg(struct usb_device *dev, unsigned long pipe,
664 void *buffer, int len, int interval)
665{
666 int dir_out = usb_pipeout(pipe);
667 int ep = usb_pipeendpoint(pipe);
668 int devnum = usb_pipedevice(pipe);
669 u8 type;
670 u16 csr;
671 u32 txlen = 0;
672 u32 nextlen = 0;
673 u8 devspeed;
674
675 /* select interrupt endpoint */
676 writeb(MUSB_INTR_EP, &musbr->index);
677
678 /* write the address of the device */
679 if (dir_out)
680 writeb(devnum, &musbr->tar[MUSB_INTR_EP].txfuncaddr);
681 else
682 writeb(devnum, &musbr->tar[MUSB_INTR_EP].rxfuncaddr);
683
684 /* configure the hub address and the port number as required */
685 devspeed = get_dev_speed(dev);
686 if ((musb_ishighspeed()) && (dev->parent != NULL) &&
687 (devspeed != MUSB_TYPE_SPEED_HIGH)) {
688 /*
689 * MUSB is in high speed and the destination device is full
690 * speed device. So configure the hub address and port
691 * address registers.
692 */
693 config_hub_port(dev, MUSB_INTR_EP);
694 } else {
695 if (dir_out) {
696 writeb(0, &musbr->tar[MUSB_INTR_EP].txhubaddr);
697 writeb(0, &musbr->tar[MUSB_INTR_EP].txhubport);
698 } else {
699 writeb(0, &musbr->tar[MUSB_INTR_EP].rxhubaddr);
700 writeb(0, &musbr->tar[MUSB_INTR_EP].rxhubport);
701 }
702 devspeed = musb_cfg.musb_speed;
703 }
704
705 /* Write the saved toggle bit value */
706 write_toggle(dev, ep, dir_out);
707
708 if (!dir_out) { /* intrrupt-in transfer */
709 /* Write the saved toggle bit value */
710 write_toggle(dev, ep, dir_out);
711 writeb(interval, &musbr->rxinterval);
712
713 /* Program the RxType register */
714 type = (devspeed << MUSB_TYPE_SPEED_SHIFT) |
715 (MUSB_TYPE_PROTO_INTR << MUSB_TYPE_PROTO_SHIFT) |
716 (ep & MUSB_TYPE_REMOTE_END);
717 writeb(type, &musbr->rxtype);
718
719 /* Write the maximum packet size to the RxMaxp register */
720 writew(dev->epmaxpacketin[ep], &musbr->rxmaxp);
721
722 while (txlen < len) {
723 nextlen = ((len-txlen) < dev->epmaxpacketin[ep]) ?
724 (len-txlen) : dev->epmaxpacketin[ep];
725
726 /* Set the ReqPkt bit */
727 writew(MUSB_RXCSR_H_REQPKT, &musbr->rxcsr);
728
729 /* Wait until the RxPktRdy bit is set */
730 if (!wait_until_rxep_ready(dev, MUSB_INTR_EP)) {
731 csr = readw(&musbr->rxcsr);
732 usb_settoggle(dev, ep, dir_out,
733 (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1);
734 csr &= ~MUSB_RXCSR_RXPKTRDY;
735 writew(csr, &musbr->rxcsr);
736 dev->act_len = txlen;
737 return 0;
738 }
739
740 /* Read the data from the FIFO */
741 read_fifo(MUSB_INTR_EP, nextlen,
742 (void *)(((u8 *)buffer) + txlen));
743
744 /* Clear the RxPktRdy bit */
745 csr = readw(&musbr->rxcsr);
746 csr &= ~MUSB_RXCSR_RXPKTRDY;
747 writew(csr, &musbr->rxcsr);
748 txlen += nextlen;
749 }
750
751 /* Keep a copy of the data toggle bit */
752 csr = readw(&musbr->rxcsr);
753 usb_settoggle(dev, ep, dir_out,
754 (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1);
755 }
756
757 /* interrupt transfer is complete */
758 dev->irq_status = 0;
759 dev->irq_act_len = len;
760 dev->irq_handle(dev);
761 dev->status = 0;
762 dev->act_len = len;
763 return 0;
764}
765
766
767#ifdef CONFIG_SYS_USB_EVENT_POLL
768/*
769 * This function polls for USB keyboard data.
770 */
771void usb_event_poll()
772{
773 device_t *dev;
774 struct usb_device *usb_kbd_dev;
775 struct usb_interface_descriptor *iface;
776 struct usb_endpoint_descriptor *ep;
777 int pipe;
778 int maxp;
779
780 /* Get the pointer to USB Keyboard device pointer */
781 dev = device_get_by_name("usbkbd");
782 usb_kbd_dev = (struct usb_device *)dev->priv;
783 iface = &usb_kbd_dev->config.if_desc[0];
784 ep = &iface->ep_desc[0];
785 pipe = usb_rcvintpipe(usb_kbd_dev, ep->bEndpointAddress);
786
787 /* Submit a interrupt transfer request */
788 maxp = usb_maxpacket(usb_kbd_dev, pipe);
789 usb_submit_int_msg(usb_kbd_dev, pipe, &new[0],
790 maxp > 8 ? 8 : maxp, ep->bInterval);
791}
792#endif /* CONFIG_SYS_USB_EVENT_POLL */
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