[people/ms/u-boot.git] / drivers / video / ipu.h

/*
 * Porting to u-boot:
 *
 * (C) Copyright 2010
 * Stefano Babic, DENX Software Engineering, sbabic@denx.de
 *
 * Linux IPU driver for MX51:
 *
 * (C) Copyright 2005-2010 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __ASM_ARCH_IPU_H__
#define __ASM_ARCH_IPU_H__

#include <linux/types.h>
#include <ipu_pixfmt.h>

#define IDMA_CHAN_INVALID	0xFF
#define HIGH_RESOLUTION_WIDTH	1024

struct clk {
	const char *name;
	int id;
	/* Source clock this clk depends on */
	struct clk *parent;
	/* Secondary clock to enable/disable with this clock */
	struct clk *secondary;
	/* Current clock rate */
	unsigned long rate;
	/* Reference count of clock enable/disable */
	__s8 usecount;
	/* Register bit position for clock's enable/disable control. */
	u8 enable_shift;
	/* Register address for clock's enable/disable control. */
	void *enable_reg;
	u32 flags;
	/*
	 * Function ptr to recalculate the clock's rate based on parent
	 * clock's rate
	 */
	void (*recalc) (struct clk *);
	/*
	 * Function ptr to set the clock to a new rate. The rate must match a
	 * supported rate returned from round_rate. Leave blank if clock is not
	* programmable
	 */
	int (*set_rate) (struct clk *, unsigned long);
	/*
	 * Function ptr to round the requested clock rate to the nearest
	 * supported rate that is less than or equal to the requested rate.
	 */
	unsigned long (*round_rate) (struct clk *, unsigned long);
	/*
	 * Function ptr to enable the clock. Leave blank if clock can not
	 * be gated.
	 */
	int (*enable) (struct clk *);
	/*
	 * Function ptr to disable the clock. Leave blank if clock can not
	 * be gated.
	 */
	void (*disable) (struct clk *);
	/* Function ptr to set the parent clock of the clock. */
	int (*set_parent) (struct clk *, struct clk *);
};

/*
 * Enumeration of Synchronous (Memory-less) panel types
 */
typedef enum {
	IPU_PANEL_SHARP_TFT,
	IPU_PANEL_TFT,
} ipu_panel_t;

/*
 * IPU Driver channels definitions.
 * Note these are different from IDMA channels
 */
#define IPU_MAX_CH	32
#define _MAKE_CHAN(num, v_in, g_in, a_in, out) \
	((num << 24) | (v_in << 18) | (g_in << 12) | (a_in << 6) | out)
#define _MAKE_ALT_CHAN(ch)		(ch | (IPU_MAX_CH << 24))
#define IPU_CHAN_ID(ch)			(ch >> 24)
#define IPU_CHAN_ALT(ch)		(ch & 0x02000000)
#define IPU_CHAN_ALPHA_IN_DMA(ch)	((uint32_t) (ch >> 6) & 0x3F)
#define IPU_CHAN_GRAPH_IN_DMA(ch)	((uint32_t) (ch >> 12) & 0x3F)
#define IPU_CHAN_VIDEO_IN_DMA(ch)	((uint32_t) (ch >> 18) & 0x3F)
#define IPU_CHAN_OUT_DMA(ch)		((uint32_t) (ch & 0x3F))
#define NO_DMA 0x3F
#define ALT	1

/*
 * Enumeration of IPU logical channels. An IPU logical channel is defined as a
 * combination of an input (memory to IPU), output (IPU to memory), and/or
 * secondary input IDMA channels and in some cases an Image Converter task.
 * Some channels consist of only an input or output.
 */
typedef enum {
	CHAN_NONE = -1,

	MEM_DC_SYNC = _MAKE_CHAN(7, 28, NO_DMA, NO_DMA, NO_DMA),
	MEM_DC_ASYNC = _MAKE_CHAN(8, 41, NO_DMA, NO_DMA, NO_DMA),
	MEM_BG_SYNC = _MAKE_CHAN(9, 23, NO_DMA, 51, NO_DMA),
	MEM_FG_SYNC = _MAKE_CHAN(10, 27, NO_DMA, 31, NO_DMA),

	MEM_BG_ASYNC0 = _MAKE_CHAN(11, 24, NO_DMA, 52, NO_DMA),
	MEM_FG_ASYNC0 = _MAKE_CHAN(12, 29, NO_DMA, 33, NO_DMA),
	MEM_BG_ASYNC1 = _MAKE_ALT_CHAN(MEM_BG_ASYNC0),
	MEM_FG_ASYNC1 = _MAKE_ALT_CHAN(MEM_FG_ASYNC0),

	DIRECT_ASYNC0 = _MAKE_CHAN(13, NO_DMA, NO_DMA, NO_DMA, NO_DMA),
	DIRECT_ASYNC1 = _MAKE_CHAN(14, NO_DMA, NO_DMA, NO_DMA, NO_DMA),

} ipu_channel_t;

/*
 * Enumeration of types of buffers for a logical channel.
 */
typedef enum {
	IPU_OUTPUT_BUFFER = 0,	/*< Buffer for output from IPU */
	IPU_ALPHA_IN_BUFFER = 1,	/*< Buffer for input to IPU */
	IPU_GRAPH_IN_BUFFER = 2,	/*< Buffer for input to IPU */
	IPU_VIDEO_IN_BUFFER = 3,	/*< Buffer for input to IPU */
	IPU_INPUT_BUFFER = IPU_VIDEO_IN_BUFFER,
	IPU_SEC_INPUT_BUFFER = IPU_GRAPH_IN_BUFFER,
} ipu_buffer_t;

#define IPU_PANEL_SERIAL		1
#define IPU_PANEL_PARALLEL		2

struct ipu_channel {
	u8 video_in_dma;
	u8 alpha_in_dma;
	u8 graph_in_dma;
	u8 out_dma;
};

enum ipu_dmfc_type {
	DMFC_NORMAL = 0,
	DMFC_HIGH_RESOLUTION_DC,
	DMFC_HIGH_RESOLUTION_DP,
	DMFC_HIGH_RESOLUTION_ONLY_DP,
};


/*
 * Union of initialization parameters for a logical channel.
 */
typedef union {
	struct {
		uint32_t di;
		unsigned char interlaced;
	} mem_dc_sync;
	struct {
		uint32_t temp;
	} mem_sdc_fg;
	struct {
		uint32_t di;
		unsigned char interlaced;
		uint32_t in_pixel_fmt;
		uint32_t out_pixel_fmt;
		unsigned char alpha_chan_en;
	} mem_dp_bg_sync;
	struct {
		uint32_t temp;
	} mem_sdc_bg;
	struct {
		uint32_t di;
		unsigned char interlaced;
		uint32_t in_pixel_fmt;
		uint32_t out_pixel_fmt;
		unsigned char alpha_chan_en;
	} mem_dp_fg_sync;
} ipu_channel_params_t;

/*
 * Enumeration of IPU interrupts.
 */
enum ipu_irq_line {
	IPU_IRQ_DP_SF_END = 448 + 3,
	IPU_IRQ_DC_FC_1 = 448 + 9,
};

/*
 * Bitfield of Display Interface signal polarities.
 */
typedef struct {
	unsigned datamask_en:1;
	unsigned ext_clk:1;
	unsigned interlaced:1;
	unsigned odd_field_first:1;
	unsigned clksel_en:1;
	unsigned clkidle_en:1;
	unsigned data_pol:1;	/* true = inverted */
	unsigned clk_pol:1;	/* true = rising edge */
	unsigned enable_pol:1;
	unsigned Hsync_pol:1;	/* true = active high */
	unsigned Vsync_pol:1;
} ipu_di_signal_cfg_t;

typedef enum {
	RGB,
	YCbCr,
	YUV
} ipu_color_space_t;

/* Common IPU API */
int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t *params);
void ipu_uninit_channel(ipu_channel_t channel);

int32_t ipu_init_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,
				uint32_t pixel_fmt,
				uint16_t width, uint16_t height,
				uint32_t stride,
				dma_addr_t phyaddr_0, dma_addr_t phyaddr_1,
				uint32_t u_offset, uint32_t v_offset);

int32_t ipu_update_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,
				  uint32_t bufNum, dma_addr_t phyaddr);

int32_t ipu_is_channel_busy(ipu_channel_t channel);
void ipu_clear_buffer_ready(ipu_channel_t channel, ipu_buffer_t type,
		uint32_t bufNum);
int32_t ipu_enable_channel(ipu_channel_t channel);
int32_t ipu_disable_channel(ipu_channel_t channel);

int32_t ipu_init_sync_panel(int disp,
			    uint32_t pixel_clk,
			    uint16_t width, uint16_t height,
			    uint32_t pixel_fmt,
			    uint16_t h_start_width, uint16_t h_sync_width,
			    uint16_t h_end_width, uint16_t v_start_width,
			    uint16_t v_sync_width, uint16_t v_end_width,
			    uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig);

int32_t ipu_disp_set_global_alpha(ipu_channel_t channel, unsigned char enable,
				  uint8_t alpha);
int32_t ipu_disp_set_color_key(ipu_channel_t channel, unsigned char enable,
			       uint32_t colorKey);

uint32_t bytes_per_pixel(uint32_t fmt);

void clk_enable(struct clk *clk);
void clk_disable(struct clk *clk);
u32 clk_get_rate(struct clk *clk);
int clk_set_rate(struct clk *clk, unsigned long rate);
long clk_round_rate(struct clk *clk, unsigned long rate);
int clk_set_parent(struct clk *clk, struct clk *parent);
int clk_get_usecount(struct clk *clk);
struct clk *clk_get_parent(struct clk *clk);

void ipu_dump_registers(void);
int ipu_probe(void);
bool ipu_clk_enabled(void);

void ipu_dmfc_init(int dmfc_type, int first);
void ipu_init_dc_mappings(void);
void ipu_dmfc_set_wait4eot(int dma_chan, int width);
void ipu_dc_init(int dc_chan, int di, unsigned char interlaced);
void ipu_dc_uninit(int dc_chan);
void ipu_dp_dc_enable(ipu_channel_t channel);
int ipu_dp_init(ipu_channel_t channel, uint32_t in_pixel_fmt,
		 uint32_t out_pixel_fmt);
void ipu_dp_uninit(ipu_channel_t channel);
void ipu_dp_dc_disable(ipu_channel_t channel, unsigned char swap);
ipu_color_space_t format_to_colorspace(uint32_t fmt);
#endif
Commit	Line	Data
575001e4 SB	1	/*
	2	* Porting to u-boot:
	3	*
	4	* (C) Copyright 2010
	5	* Stefano Babic, DENX Software Engineering, sbabic@denx.de
	6	*
	7	* Linux IPU driver for MX51:
	8	*
	9	* (C) Copyright 2005-2010 Freescale Semiconductor, Inc.
	10	*
1a459660	11	* SPDX-License-Identifier: GPL-2.0+
575001e4 SB	12	*/
	13
	14	#ifndef __ASM_ARCH_IPU_H__
	15	#define __ASM_ARCH_IPU_H__
	16
	17	#include <linux/types.h>
92a98a4a	18	#include <ipu_pixfmt.h>
575001e4 SB	19
	20	#define IDMA_CHAN_INVALID 0xFF
	21	#define HIGH_RESOLUTION_WIDTH 1024
	22
	23	struct clk {
	24	const char *name;
	25	int id;
	26	/* Source clock this clk depends on */
	27	struct clk *parent;
	28	/* Secondary clock to enable/disable with this clock */
	29	struct clk *secondary;
	30	/* Current clock rate */
	31	unsigned long rate;
	32	/* Reference count of clock enable/disable */
	33	__s8 usecount;
	34	/* Register bit position for clock's enable/disable control. */
	35	u8 enable_shift;
	36	/* Register address for clock's enable/disable control. */
	37	void *enable_reg;
	38	u32 flags;
	39	/*
	40	* Function ptr to recalculate the clock's rate based on parent
	41	* clock's rate
	42	*/
	43	void (recalc) (struct clk );
	44	/*
	45	* Function ptr to set the clock to a new rate. The rate must match a
	46	* supported rate returned from round_rate. Leave blank if clock is not
	47	* programmable
	48	*/
	49	int (set_rate) (struct clk , unsigned long);
	50	/*
	51	* Function ptr to round the requested clock rate to the nearest
	52	* supported rate that is less than or equal to the requested rate.
	53	*/
	54	unsigned long (round_rate) (struct clk , unsigned long);
	55	/*
	56	* Function ptr to enable the clock. Leave blank if clock can not
	57	* be gated.
	58	*/
	59	int (enable) (struct clk );
	60	/*
	61	* Function ptr to disable the clock. Leave blank if clock can not
	62	* be gated.
	63	*/
	64	void (disable) (struct clk );
	65	/* Function ptr to set the parent clock of the clock. */
	66	int (set_parent) (struct clk , struct clk *);
	67	};
	68
	69	/*
	70	* Enumeration of Synchronous (Memory-less) panel types
	71	*/
	72	typedef enum {
	73	IPU_PANEL_SHARP_TFT,
	74	IPU_PANEL_TFT,
	75	} ipu_panel_t;
	76
575001e4 SB	77	/*
	78	* IPU Driver channels definitions.
	79	* Note these are different from IDMA channels
	80	*/
	81	#define IPU_MAX_CH 32
	82	#define _MAKE_CHAN(num, v_in, g_in, a_in, out) \
	83	((num << 24) \| (v_in << 18) \| (g_in << 12) \| (a_in << 6) \| out)
	84	#define _MAKE_ALT_CHAN(ch) (ch \| (IPU_MAX_CH << 24))
	85	#define IPU_CHAN_ID(ch) (ch >> 24)
	86	#define IPU_CHAN_ALT(ch) (ch & 0x02000000)
	87	#define IPU_CHAN_ALPHA_IN_DMA(ch) ((uint32_t) (ch >> 6) & 0x3F)
	88	#define IPU_CHAN_GRAPH_IN_DMA(ch) ((uint32_t) (ch >> 12) & 0x3F)
	89	#define IPU_CHAN_VIDEO_IN_DMA(ch) ((uint32_t) (ch >> 18) & 0x3F)
	90	#define IPU_CHAN_OUT_DMA(ch) ((uint32_t) (ch & 0x3F))
	91	#define NO_DMA 0x3F
	92	#define ALT 1
	93
	94	/*
	95	* Enumeration of IPU logical channels. An IPU logical channel is defined as a
	96	* combination of an input (memory to IPU), output (IPU to memory), and/or
	97	* secondary input IDMA channels and in some cases an Image Converter task.
	98	* Some channels consist of only an input or output.
	99	*/
	100	typedef enum {
	101	CHAN_NONE = -1,
	102
	103	MEM_DC_SYNC = _MAKE_CHAN(7, 28, NO_DMA, NO_DMA, NO_DMA),
	104	MEM_DC_ASYNC = _MAKE_CHAN(8, 41, NO_DMA, NO_DMA, NO_DMA),
	105	MEM_BG_SYNC = _MAKE_CHAN(9, 23, NO_DMA, 51, NO_DMA),
	106	MEM_FG_SYNC = _MAKE_CHAN(10, 27, NO_DMA, 31, NO_DMA),
	107
	108	MEM_BG_ASYNC0 = _MAKE_CHAN(11, 24, NO_DMA, 52, NO_DMA),
	109	MEM_FG_ASYNC0 = _MAKE_CHAN(12, 29, NO_DMA, 33, NO_DMA),
	110	MEM_BG_ASYNC1 = _MAKE_ALT_CHAN(MEM_BG_ASYNC0),
	111	MEM_FG_ASYNC1 = _MAKE_ALT_CHAN(MEM_FG_ASYNC0),
	112
	113	DIRECT_ASYNC0 = _MAKE_CHAN(13, NO_DMA, NO_DMA, NO_DMA, NO_DMA),
	114	DIRECT_ASYNC1 = _MAKE_CHAN(14, NO_DMA, NO_DMA, NO_DMA, NO_DMA),
	115
	116	} ipu_channel_t;
	117
	118	/*
	119	* Enumeration of types of buffers for a logical channel.
	120	*/
	121	typedef enum {
	122	IPU_OUTPUT_BUFFER = 0, /< Buffer for output from IPU /
	123	IPU_ALPHA_IN_BUFFER = 1, /< Buffer for input to IPU /
	124	IPU_GRAPH_IN_BUFFER = 2, /< Buffer for input to IPU /
	125	IPU_VIDEO_IN_BUFFER = 3, /< Buffer for input to IPU /
	126	IPU_INPUT_BUFFER = IPU_VIDEO_IN_BUFFER,
	127	IPU_SEC_INPUT_BUFFER = IPU_GRAPH_IN_BUFFER,
	128	} ipu_buffer_t;
	129
	130	#define IPU_PANEL_SERIAL 1
	131	#define IPU_PANEL_PARALLEL 2
	132
	133	struct ipu_channel {
	134	u8 video_in_dma;
	135	u8 alpha_in_dma;
	136	u8 graph_in_dma;
	137	u8 out_dma;
	138	};
	139
	140	enum ipu_dmfc_type {
141	DMFC_NORMAL = 0,
142	DMFC_HIGH_RESOLUTION_DC,
143	DMFC_HIGH_RESOLUTION_DP,
144	DMFC_HIGH_RESOLUTION_ONLY_DP,
145	};
146
147
148	/*
149	* Union of initialization parameters for a logical channel.
150	*/
151	typedef union {
152	struct {
153	uint32_t di;
154	unsigned char interlaced;
155	} mem_dc_sync;
156	struct {
157	uint32_t temp;
158	} mem_sdc_fg;
159	struct {
160	uint32_t di;
161	unsigned char interlaced;
162	uint32_t in_pixel_fmt;
163	uint32_t out_pixel_fmt;
164	unsigned char alpha_chan_en;
165	} mem_dp_bg_sync;
166	struct {
167	uint32_t temp;
168	} mem_sdc_bg;
169	struct {
170	uint32_t di;
171	unsigned char interlaced;
172	uint32_t in_pixel_fmt;
173	uint32_t out_pixel_fmt;
174	unsigned char alpha_chan_en;
175	} mem_dp_fg_sync;
176	} ipu_channel_params_t;
177
e66866c5 LY	178	/*
	179	* Enumeration of IPU interrupts.
	180	*/
	181	enum ipu_irq_line {
	182	IPU_IRQ_DP_SF_END = 448 + 3,
	183	IPU_IRQ_DC_FC_1 = 448 + 9,
	184	};
	185
575001e4 SB	186	/*
	187	* Bitfield of Display Interface signal polarities.
	188	*/
	189	typedef struct {
	190	unsigned datamask_en:1;
	191	unsigned ext_clk:1;
	192	unsigned interlaced:1;
	193	unsigned odd_field_first:1;
	194	unsigned clksel_en:1;
	195	unsigned clkidle_en:1;
	196	unsigned data_pol:1; /* true = inverted */
	197	unsigned clk_pol:1; /* true = rising edge */
	198	unsigned enable_pol:1;
	199	unsigned Hsync_pol:1; /* true = active high */
	200	unsigned Vsync_pol:1;
	201	} ipu_di_signal_cfg_t;
	202
	203	typedef enum {
	204	RGB,
	205	YCbCr,
	206	YUV
	207	} ipu_color_space_t;
	208
	209	/* Common IPU API */
	210	int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t *params);
	211	void ipu_uninit_channel(ipu_channel_t channel);
	212
	213	int32_t ipu_init_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,
	214	uint32_t pixel_fmt,
	215	uint16_t width, uint16_t height,
	216	uint32_t stride,
	217	dma_addr_t phyaddr_0, dma_addr_t phyaddr_1,
	218	uint32_t u_offset, uint32_t v_offset);
	219
	220	int32_t ipu_update_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,
	221	uint32_t bufNum, dma_addr_t phyaddr);
	222
	223	int32_t ipu_is_channel_busy(ipu_channel_t channel);
	224	void ipu_clear_buffer_ready(ipu_channel_t channel, ipu_buffer_t type,
	225	uint32_t bufNum);
	226	int32_t ipu_enable_channel(ipu_channel_t channel);
	227	int32_t ipu_disable_channel(ipu_channel_t channel);
	228
	229	int32_t ipu_init_sync_panel(int disp,
	230	uint32_t pixel_clk,
	231	uint16_t width, uint16_t height,
	232	uint32_t pixel_fmt,
	233	uint16_t h_start_width, uint16_t h_sync_width,
	234	uint16_t h_end_width, uint16_t v_start_width,
	235	uint16_t v_sync_width, uint16_t v_end_width,
	236	uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig);
	237
	238	int32_t ipu_disp_set_global_alpha(ipu_channel_t channel, unsigned char enable,
	239	uint8_t alpha);
	240	int32_t ipu_disp_set_color_key(ipu_channel_t channel, unsigned char enable,
	241	uint32_t colorKey);
	242
	243	uint32_t bytes_per_pixel(uint32_t fmt);
	244
	245	void clk_enable(struct clk *clk);
	246	void clk_disable(struct clk *clk);
	247	u32 clk_get_rate(struct clk *clk);
	248	int clk_set_rate(struct clk *clk, unsigned long rate);
	249	long clk_round_rate(struct clk *clk, unsigned long rate);
250	int clk_set_parent(struct clk clk, struct clk parent);
251	int clk_get_usecount(struct clk *clk);
252	struct clk clk_get_parent(struct clk clk);
253
254	void ipu_dump_registers(void);
255	int ipu_probe(void);
f8ba7f27	256	bool ipu_clk_enabled(void);
575001e4 SB	257
	258	void ipu_dmfc_init(int dmfc_type, int first);
	259	void ipu_init_dc_mappings(void);
	260	void ipu_dmfc_set_wait4eot(int dma_chan, int width);
	261	void ipu_dc_init(int dc_chan, int di, unsigned char interlaced);
	262	void ipu_dc_uninit(int dc_chan);
	263	void ipu_dp_dc_enable(ipu_channel_t channel);
	264	int ipu_dp_init(ipu_channel_t channel, uint32_t in_pixel_fmt,
	265	uint32_t out_pixel_fmt);
	266	void ipu_dp_uninit(ipu_channel_t channel);
	267	void ipu_dp_dc_disable(ipu_channel_t channel, unsigned char swap);
	268	ipu_color_space_t format_to_colorspace(uint32_t fmt);
575001e4	269	#endif