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mx5 clocks: Cleanup
[people/ms/u-boot.git] / drivers / video / ipu_common.c
CommitLineData
575001e4
SB		 1/*
2 * Porting to u-boot:
3 *
4 * (C) Copyright 2010
5 * Stefano Babic, DENX Software Engineering, sbabic@denx.de
6 *
7 * Linux IPU driver for MX51:
8 *
9 * (C) Copyright 2005-2010 Freescale Semiconductor, Inc.
10 *
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29
30/* #define DEBUG */
31#include <common.h>
32#include <linux/types.h>
33#include <linux/err.h>
34#include <asm/io.h>
35#include <asm/errno.h>
36#include <asm/arch/imx-regs.h>
37#include <asm/arch/crm_regs.h>
38#include "ipu.h"
39#include "ipu_regs.h"
40
41extern struct mxc_ccm_reg *mxc_ccm;
42extern u32 *ipu_cpmem_base;
43
44struct ipu_ch_param_word {
45 uint32_t data[5];
46 uint32_t res[3];
47};
48
49struct ipu_ch_param {
50 struct ipu_ch_param_word word[2];
51};
52
53#define ipu_ch_param_addr(ch) (((struct ipu_ch_param *)ipu_cpmem_base) + (ch))
54
55#define _param_word(base, w) \
56 (((struct ipu_ch_param *)(base))->word[(w)].data)
57
58#define ipu_ch_param_set_field(base, w, bit, size, v) { \
59 int i = (bit) / 32; \
60 int off = (bit) % 32; \
61 _param_word(base, w)[i] |= (v) << off; \
62 if (((bit) + (size) - 1) / 32 > i) { \
63 _param_word(base, w)[i + 1] |= (v) >> (off ? (32 - off) : 0); \
64 } \
65}
66
67#define ipu_ch_param_mod_field(base, w, bit, size, v) { \
68 int i = (bit) / 32; \
69 int off = (bit) % 32; \
70 u32 mask = (1UL << size) - 1; \
71 u32 temp = _param_word(base, w)[i]; \
72 temp &= ~(mask << off); \
73 _param_word(base, w)[i] = temp | (v) << off; \
74 if (((bit) + (size) - 1) / 32 > i) { \
75 temp = _param_word(base, w)[i + 1]; \
76 temp &= ~(mask >> (32 - off)); \
77 _param_word(base, w)[i + 1] = \
78 temp | ((v) >> (off ? (32 - off) : 0)); \
79 } \
80}
81
82#define ipu_ch_param_read_field(base, w, bit, size) ({ \
83 u32 temp2; \
84 int i = (bit) / 32; \
85 int off = (bit) % 32; \
86 u32 mask = (1UL << size) - 1; \
87 u32 temp1 = _param_word(base, w)[i]; \
88 temp1 = mask & (temp1 >> off); \
89 if (((bit)+(size) - 1) / 32 > i) { \
90 temp2 = _param_word(base, w)[i + 1]; \
91 temp2 &= mask >> (off ? (32 - off) : 0); \
92 temp1 |= temp2 << (off ? (32 - off) : 0); \
93 } \
94 temp1; \
95})
96
97
98void clk_enable(struct clk *clk)
99{
100 if (clk) {
101 if (clk->usecount++ == 0) {
102 clk->enable(clk);
103 }
104 }
105}
106
107void clk_disable(struct clk *clk)
108{
109 if (clk) {
110 if (!(--clk->usecount)) {
111 if (clk->disable)
112 clk->disable(clk);
113 }
114 }
115}
116
117int clk_get_usecount(struct clk *clk)
118{
119 if (clk == NULL)
120 return 0;
121
122 return clk->usecount;
123}
124
125u32 clk_get_rate(struct clk *clk)
126{
127 if (!clk)
128 return 0;
129
130 return clk->rate;
131}
132
133struct clk *clk_get_parent(struct clk *clk)
134{
135 if (!clk)
136 return 0;
137
138 return clk->parent;
139}
140
141int clk_set_rate(struct clk *clk, unsigned long rate)
142{
143 if (clk && clk->set_rate)
144 clk->set_rate(clk, rate);
145 return clk->rate;
146}
147
148long clk_round_rate(struct clk *clk, unsigned long rate)
149{
150 if (clk == NULL || !clk->round_rate)
151 return 0;
152
153 return clk->round_rate(clk, rate);
154}
155
156int clk_set_parent(struct clk *clk, struct clk *parent)
157{
158 clk->parent = parent;
159 if (clk->set_parent)
160 return clk->set_parent(clk, parent);
161 return 0;
162}
163
164static int clk_ipu_enable(struct clk *clk)
165{
166 u32 reg;
167
168 reg = __raw_readl(clk->enable_reg);
169 reg |= MXC_CCM_CCGR_CG_MASK << clk->enable_shift;
170 __raw_writel(reg, clk->enable_reg);
171
0bb7e316 172#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
575001e4
SB		 173 /* Handshake with IPU when certain clock rates are changed. */
174 reg = __raw_readl(&mxc_ccm->ccdr);
175 reg &= ~MXC_CCM_CCDR_IPU_HS_MASK;
176 __raw_writel(reg, &mxc_ccm->ccdr);
177
178 /* Handshake with IPU when LPM is entered as its enabled. */
179 reg = __raw_readl(&mxc_ccm->clpcr);
180 reg &= ~MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS;
181 __raw_writel(reg, &mxc_ccm->clpcr);
e4942ad7 182#endif
575001e4
SB		 183 return 0;
184}
185
186static void clk_ipu_disable(struct clk *clk)
187{
188 u32 reg;
189
190 reg = __raw_readl(clk->enable_reg);
191 reg &= ~(MXC_CCM_CCGR_CG_MASK << clk->enable_shift);
192 __raw_writel(reg, clk->enable_reg);
193
0bb7e316 194#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
575001e4
SB		 195 /*
196 * No handshake with IPU whe dividers are changed
197 * as its not enabled.
198 */
199 reg = __raw_readl(&mxc_ccm->ccdr);
200 reg |= MXC_CCM_CCDR_IPU_HS_MASK;
201 __raw_writel(reg, &mxc_ccm->ccdr);
202
203 /* No handshake with IPU when LPM is entered as its not enabled. */
204 reg = __raw_readl(&mxc_ccm->clpcr);
205 reg |= MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS;
206 __raw_writel(reg, &mxc_ccm->clpcr);
e4942ad7 207#endif
575001e4
SB		 208}
209
210
211static struct clk ipu_clk = {
212 .name = "ipu_clk",
9fbdb1aa 213 .rate = CONFIG_IPUV3_CLK,
0bb7e316 214#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
477bca22 215 .enable_reg = (u32 *)(CCM_BASE_ADDR +
575001e4
SB		 216 offsetof(struct mxc_ccm_reg, CCGR5)),
217 .enable_shift = MXC_CCM_CCGR5_CG5_OFFSET,
0bb7e316
EN		 218#else
219 .enable_reg = (u32 *)(CCM_BASE_ADDR +
220 offsetof(struct mxc_ccm_reg, CCGR3)),
221 .enable_shift = MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET,
222#endif
575001e4
SB		 223 .enable = clk_ipu_enable,
224 .disable = clk_ipu_disable,
225 .usecount = 0,
226};
227
cf65d478
EN		 228static struct clk ldb_clk = {
229 .name = "ldb_clk",
230 .rate = 65000000,
231 .usecount = 0,
232};
233
575001e4
SB		 234/* Globals */
235struct clk *g_ipu_clk;
cf65d478 236struct clk *g_ldb_clk;
575001e4
SB		 237unsigned char g_ipu_clk_enabled;
238struct clk *g_di_clk[2];
239struct clk *g_pixel_clk[2];
240unsigned char g_dc_di_assignment[10];
241uint32_t g_channel_init_mask;
242uint32_t g_channel_enable_mask;
243
244static int ipu_dc_use_count;
245static int ipu_dp_use_count;
246static int ipu_dmfc_use_count;
247static int ipu_di_use_count[2];
248
249u32 *ipu_cpmem_base;
250u32 *ipu_dc_tmpl_reg;
251
252/* Static functions */
253
254static inline void ipu_ch_param_set_high_priority(uint32_t ch)
255{
256 ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 93, 2, 1);
257};
258
259static inline uint32_t channel_2_dma(ipu_channel_t ch, ipu_buffer_t type)
260{
261 return ((uint32_t) ch >> (6 * type)) & 0x3F;
262};
263
264/* Either DP BG or DP FG can be graphic window */
265static inline int ipu_is_dp_graphic_chan(uint32_t dma_chan)
266{
267 return (dma_chan == 23 || dma_chan == 27);
268}
269
270static inline int ipu_is_dmfc_chan(uint32_t dma_chan)
271{
272 return ((dma_chan >= 23) && (dma_chan <= 29));
273}
274
275
276static inline void ipu_ch_param_set_buffer(uint32_t ch, int bufNum,
277 dma_addr_t phyaddr)
278{
279 ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 29 * bufNum, 29,
280 phyaddr / 8);
281};
282
283#define idma_is_valid(ch) (ch != NO_DMA)
284#define idma_mask(ch) (idma_is_valid(ch) ? (1UL << (ch & 0x1F)) : 0)
285#define idma_is_set(reg, dma) (__raw_readl(reg(dma)) & idma_mask(dma))
286
287static void ipu_pixel_clk_recalc(struct clk *clk)
288{
289 u32 div = __raw_readl(DI_BS_CLKGEN0(clk->id));
290 if (div == 0)
291 clk->rate = 0;
292 else
293 clk->rate = (clk->parent->rate * 16) / div;
294}
295
296static unsigned long ipu_pixel_clk_round_rate(struct clk *clk,
297 unsigned long rate)
298{
299 u32 div, div1;
300 u32 tmp;
301 /*
302 * Calculate divider
303 * Fractional part is 4 bits,
304 * so simply multiply by 2^4 to get fractional part.
305 */
306 tmp = (clk->parent->rate * 16);
307 div = tmp / rate;
308
309 if (div < 0x10) /* Min DI disp clock divider is 1 */
310 div = 0x10;
311 if (div & ~0xFEF)
312 div &= 0xFF8;
313 else {
314 div1 = div & 0xFE0;
315 if ((tmp/div1 - tmp/div) < rate / 4)
316 div = div1;
317 else
318 div &= 0xFF8;
319 }
320 return (clk->parent->rate * 16) / div;
321}
322
323static int ipu_pixel_clk_set_rate(struct clk *clk, unsigned long rate)
324{
325 u32 div = (clk->parent->rate * 16) / rate;
326
327 __raw_writel(div, DI_BS_CLKGEN0(clk->id));
328
329 /* Setup pixel clock timing */
330 __raw_writel((div / 16) << 16, DI_BS_CLKGEN1(clk->id));
331
332 clk->rate = (clk->parent->rate * 16) / div;
333 return 0;
334}
335
336static int ipu_pixel_clk_enable(struct clk *clk)
337{
338 u32 disp_gen = __raw_readl(IPU_DISP_GEN);
339 disp_gen |= clk->id ? DI1_COUNTER_RELEASE : DI0_COUNTER_RELEASE;
340 __raw_writel(disp_gen, IPU_DISP_GEN);
341
342 return 0;
343}
344
345static void ipu_pixel_clk_disable(struct clk *clk)
346{
347 u32 disp_gen = __raw_readl(IPU_DISP_GEN);
348 disp_gen &= clk->id ? ~DI1_COUNTER_RELEASE : ~DI0_COUNTER_RELEASE;
349 __raw_writel(disp_gen, IPU_DISP_GEN);
350
351}
352
353static int ipu_pixel_clk_set_parent(struct clk *clk, struct clk *parent)
354{
355 u32 di_gen = __raw_readl(DI_GENERAL(clk->id));
356
357 if (parent == g_ipu_clk)
358 di_gen &= ~DI_GEN_DI_CLK_EXT;
cf65d478 359 else if (!IS_ERR(g_di_clk[clk->id]) && parent == g_ldb_clk)
575001e4
SB		 360 di_gen |= DI_GEN_DI_CLK_EXT;
361 else
362 return -EINVAL;
363
364 __raw_writel(di_gen, DI_GENERAL(clk->id));
365 ipu_pixel_clk_recalc(clk);
366 return 0;
367}
368
369static struct clk pixel_clk[] = {
370 {
371 .name = "pixel_clk",
372 .id = 0,
373 .recalc = ipu_pixel_clk_recalc,
374 .set_rate = ipu_pixel_clk_set_rate,
375 .round_rate = ipu_pixel_clk_round_rate,
376 .set_parent = ipu_pixel_clk_set_parent,
377 .enable = ipu_pixel_clk_enable,
378 .disable = ipu_pixel_clk_disable,
379 .usecount = 0,
380 },
381 {
382 .name = "pixel_clk",
383 .id = 1,
384 .recalc = ipu_pixel_clk_recalc,
385 .set_rate = ipu_pixel_clk_set_rate,
386 .round_rate = ipu_pixel_clk_round_rate,
387 .set_parent = ipu_pixel_clk_set_parent,
388 .enable = ipu_pixel_clk_enable,
389 .disable = ipu_pixel_clk_disable,
390 .usecount = 0,
391 },
392};
393
394/*
395 * This function resets IPU
396 */
397void ipu_reset(void)
398{
399 u32 *reg;
400 u32 value;
401
402 reg = (u32 *)SRC_BASE_ADDR;
403 value = __raw_readl(reg);
404 value = value | SW_IPU_RST;
405 __raw_writel(value, reg);
406}
407
408/*
409 * This function is called by the driver framework to initialize the IPU
410 * hardware.
411 *
412 * @param dev The device structure for the IPU passed in by the
413 * driver framework.
414 *
415 * @return Returns 0 on success or negative error code on error
416 */
417int ipu_probe(void)
418{
419 unsigned long ipu_base;
913db794 420#if defined CONFIG_MX51
575001e4
SB		 421 u32 temp;
422
423 u32 *reg_hsc_mcd = (u32 *)MIPI_HSC_BASE_ADDR;
424 u32 *reg_hsc_mxt_conf = (u32 *)(MIPI_HSC_BASE_ADDR + 0x800);
425
426 __raw_writel(0xF00, reg_hsc_mcd);
427
428 /* CSI mode reserved*/
429 temp = __raw_readl(reg_hsc_mxt_conf);
430 __raw_writel(temp | 0x0FF, reg_hsc_mxt_conf);
431
432 temp = __raw_readl(reg_hsc_mxt_conf);
433 __raw_writel(temp | 0x10000, reg_hsc_mxt_conf);
913db794 434#endif
575001e4
SB		 435
436 ipu_base = IPU_CTRL_BASE_ADDR;
437 ipu_cpmem_base = (u32 *)(ipu_base + IPU_CPMEM_REG_BASE);
438 ipu_dc_tmpl_reg = (u32 *)(ipu_base + IPU_DC_TMPL_REG_BASE);
439
440 g_pixel_clk[0] = &pixel_clk[0];
441 g_pixel_clk[1] = &pixel_clk[1];
442
443 g_ipu_clk = &ipu_clk;
444 debug("ipu_clk = %u\n", clk_get_rate(g_ipu_clk));
cf65d478
EN		 445 g_ldb_clk = &ldb_clk;
446 debug("ldb_clk = %u\n", clk_get_rate(g_ldb_clk));
575001e4
SB		 447 ipu_reset();
448
449 clk_set_parent(g_pixel_clk[0], g_ipu_clk);
450 clk_set_parent(g_pixel_clk[1], g_ipu_clk);
451 clk_enable(g_ipu_clk);
452
453 g_di_clk[0] = NULL;
454 g_di_clk[1] = NULL;
455
456 __raw_writel(0x807FFFFF, IPU_MEM_RST);
457 while (__raw_readl(IPU_MEM_RST) & 0x80000000)
458 ;
459
460 ipu_init_dc_mappings();
461
462 __raw_writel(0, IPU_INT_CTRL(5));
463 __raw_writel(0, IPU_INT_CTRL(6));
464 __raw_writel(0, IPU_INT_CTRL(9));
465 __raw_writel(0, IPU_INT_CTRL(10));
466
467 /* DMFC Init */
468 ipu_dmfc_init(DMFC_NORMAL, 1);
469
470 /* Set sync refresh channels as high priority */
471 __raw_writel(0x18800000L, IDMAC_CHA_PRI(0));
472
473 /* Set MCU_T to divide MCU access window into 2 */
474 __raw_writel(0x00400000L | (IPU_MCU_T_DEFAULT << 18), IPU_DISP_GEN);
475
476 clk_disable(g_ipu_clk);
477
478 return 0;
479}
480
481void ipu_dump_registers(void)
482{
483 debug("IPU_CONF = \t0x%08X\n", __raw_readl(IPU_CONF));
484 debug("IDMAC_CONF = \t0x%08X\n", __raw_readl(IDMAC_CONF));
485 debug("IDMAC_CHA_EN1 = \t0x%08X\n",
486 __raw_readl(IDMAC_CHA_EN(0)));
487 debug("IDMAC_CHA_EN2 = \t0x%08X\n",
488 __raw_readl(IDMAC_CHA_EN(32)));
489 debug("IDMAC_CHA_PRI1 = \t0x%08X\n",
490 __raw_readl(IDMAC_CHA_PRI(0)));
491 debug("IDMAC_CHA_PRI2 = \t0x%08X\n",
492 __raw_readl(IDMAC_CHA_PRI(32)));
493 debug("IPU_CHA_DB_MODE_SEL0 = \t0x%08X\n",
494 __raw_readl(IPU_CHA_DB_MODE_SEL(0)));
495 debug("IPU_CHA_DB_MODE_SEL1 = \t0x%08X\n",
496 __raw_readl(IPU_CHA_DB_MODE_SEL(32)));
497 debug("DMFC_WR_CHAN = \t0x%08X\n",
498 __raw_readl(DMFC_WR_CHAN));
499 debug("DMFC_WR_CHAN_DEF = \t0x%08X\n",
500 __raw_readl(DMFC_WR_CHAN_DEF));
501 debug("DMFC_DP_CHAN = \t0x%08X\n",
502 __raw_readl(DMFC_DP_CHAN));
503 debug("DMFC_DP_CHAN_DEF = \t0x%08X\n",
504 __raw_readl(DMFC_DP_CHAN_DEF));
505 debug("DMFC_IC_CTRL = \t0x%08X\n",
506 __raw_readl(DMFC_IC_CTRL));
507 debug("IPU_FS_PROC_FLOW1 = \t0x%08X\n",
508 __raw_readl(IPU_FS_PROC_FLOW1));
509 debug("IPU_FS_PROC_FLOW2 = \t0x%08X\n",
510 __raw_readl(IPU_FS_PROC_FLOW2));
511 debug("IPU_FS_PROC_FLOW3 = \t0x%08X\n",
512 __raw_readl(IPU_FS_PROC_FLOW3));
513 debug("IPU_FS_DISP_FLOW1 = \t0x%08X\n",
514 __raw_readl(IPU_FS_DISP_FLOW1));
515}
516
517/*
518 * This function is called to initialize a logical IPU channel.
519 *
520 * @param channel Input parameter for the logical channel ID to init.
521 *
522 * @param params Input parameter containing union of channel
523 * initialization parameters.
524 *
525 * @return Returns 0 on success or negative error code on fail
526 */
527int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t *params)
528{
529 int ret = 0;
530 uint32_t ipu_conf;
531
532 debug("init channel = %d\n", IPU_CHAN_ID(channel));
533
534 if (g_ipu_clk_enabled == 0) {
535 g_ipu_clk_enabled = 1;
536 clk_enable(g_ipu_clk);
537 }
538
539
540 if (g_channel_init_mask & (1L << IPU_CHAN_ID(channel))) {
541 printf("Warning: channel already initialized %d\n",
542 IPU_CHAN_ID(channel));
543 }
544
545 ipu_conf = __raw_readl(IPU_CONF);
546
547 switch (channel) {
548 case MEM_DC_SYNC:
549 if (params->mem_dc_sync.di > 1) {
550 ret = -EINVAL;
551 goto err;
552 }
553
554 g_dc_di_assignment[1] = params->mem_dc_sync.di;
555 ipu_dc_init(1, params->mem_dc_sync.di,
556 params->mem_dc_sync.interlaced);
557 ipu_di_use_count[params->mem_dc_sync.di]++;
558 ipu_dc_use_count++;
559 ipu_dmfc_use_count++;
560 break;
561 case MEM_BG_SYNC:
562 if (params->mem_dp_bg_sync.di > 1) {
563 ret = -EINVAL;
564 goto err;
565 }
566
567 g_dc_di_assignment[5] = params->mem_dp_bg_sync.di;
568 ipu_dp_init(channel, params->mem_dp_bg_sync.in_pixel_fmt,
569 params->mem_dp_bg_sync.out_pixel_fmt);
570 ipu_dc_init(5, params->mem_dp_bg_sync.di,
571 params->mem_dp_bg_sync.interlaced);
572 ipu_di_use_count[params->mem_dp_bg_sync.di]++;
573 ipu_dc_use_count++;
574 ipu_dp_use_count++;
575 ipu_dmfc_use_count++;
576 break;
577 case MEM_FG_SYNC:
578 ipu_dp_init(channel, params->mem_dp_fg_sync.in_pixel_fmt,
579 params->mem_dp_fg_sync.out_pixel_fmt);
580
581 ipu_dc_use_count++;
582 ipu_dp_use_count++;
583 ipu_dmfc_use_count++;
584 break;
585 default:
586 printf("Missing channel initialization\n");
587 break;
588 }
589
590 /* Enable IPU sub module */
591 g_channel_init_mask |= 1L << IPU_CHAN_ID(channel);
592 if (ipu_dc_use_count == 1)
593 ipu_conf |= IPU_CONF_DC_EN;
594 if (ipu_dp_use_count == 1)
595 ipu_conf |= IPU_CONF_DP_EN;
596 if (ipu_dmfc_use_count == 1)
597 ipu_conf |= IPU_CONF_DMFC_EN;
598 if (ipu_di_use_count[0] == 1) {
599 ipu_conf |= IPU_CONF_DI0_EN;
600 }
601 if (ipu_di_use_count[1] == 1) {
602 ipu_conf |= IPU_CONF_DI1_EN;
603 }
604
605 __raw_writel(ipu_conf, IPU_CONF);
606
607err:
608 return ret;
609}
610
611/*
612 * This function is called to uninitialize a logical IPU channel.
613 *
614 * @param channel Input parameter for the logical channel ID to uninit.
615 */
616void ipu_uninit_channel(ipu_channel_t channel)
617{
618 uint32_t reg;
619 uint32_t in_dma, out_dma = 0;
620 uint32_t ipu_conf;
621
622 if ((g_channel_init_mask & (1L << IPU_CHAN_ID(channel))) == 0) {
623 debug("Channel already uninitialized %d\n",
624 IPU_CHAN_ID(channel));
625 return;
626 }
627
628 /*
629 * Make sure channel is disabled
630 * Get input and output dma channels
631 */
632 in_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
633 out_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
634
635 if (idma_is_set(IDMAC_CHA_EN, in_dma) ||
636 idma_is_set(IDMAC_CHA_EN, out_dma)) {
637 printf(
638 "Channel %d is not disabled, disable first\n",
639 IPU_CHAN_ID(channel));
640 return;
641 }
642
643 ipu_conf = __raw_readl(IPU_CONF);
644
645 /* Reset the double buffer */
646 reg = __raw_readl(IPU_CHA_DB_MODE_SEL(in_dma));
647 __raw_writel(reg & ~idma_mask(in_dma), IPU_CHA_DB_MODE_SEL(in_dma));
648 reg = __raw_readl(IPU_CHA_DB_MODE_SEL(out_dma));
649 __raw_writel(reg & ~idma_mask(out_dma), IPU_CHA_DB_MODE_SEL(out_dma));
650
651 switch (channel) {
652 case MEM_DC_SYNC:
653 ipu_dc_uninit(1);
654 ipu_di_use_count[g_dc_di_assignment[1]]--;
655 ipu_dc_use_count--;
656 ipu_dmfc_use_count--;
657 break;
658 case MEM_BG_SYNC:
659 ipu_dp_uninit(channel);
660 ipu_dc_uninit(5);
661 ipu_di_use_count[g_dc_di_assignment[5]]--;
662 ipu_dc_use_count--;
663 ipu_dp_use_count--;
664 ipu_dmfc_use_count--;
665 break;
666 case MEM_FG_SYNC:
667 ipu_dp_uninit(channel);
668 ipu_dc_use_count--;
669 ipu_dp_use_count--;
670 ipu_dmfc_use_count--;
671 break;
672 default:
673 break;
674 }
675
676 g_channel_init_mask &= ~(1L << IPU_CHAN_ID(channel));
677
678 if (ipu_dc_use_count == 0)
679 ipu_conf &= ~IPU_CONF_DC_EN;
680 if (ipu_dp_use_count == 0)
681 ipu_conf &= ~IPU_CONF_DP_EN;
682 if (ipu_dmfc_use_count == 0)
683 ipu_conf &= ~IPU_CONF_DMFC_EN;
684 if (ipu_di_use_count[0] == 0) {
685 ipu_conf &= ~IPU_CONF_DI0_EN;
686 }
687 if (ipu_di_use_count[1] == 0) {
688 ipu_conf &= ~IPU_CONF_DI1_EN;
689 }
690
691 __raw_writel(ipu_conf, IPU_CONF);
692
693 if (ipu_conf == 0) {
694 clk_disable(g_ipu_clk);
695 g_ipu_clk_enabled = 0;
696 }
697
698}
699
700static inline void ipu_ch_param_dump(int ch)
701{
702#ifdef DEBUG
703 struct ipu_ch_param *p = ipu_ch_param_addr(ch);
704 debug("ch %d word 0 - %08X %08X %08X %08X %08X\n", ch,
705 p->word[0].data[0], p->word[0].data[1], p->word[0].data[2],
706 p->word[0].data[3], p->word[0].data[4]);
707 debug("ch %d word 1 - %08X %08X %08X %08X %08X\n", ch,
708 p->word[1].data[0], p->word[1].data[1], p->word[1].data[2],
709 p->word[1].data[3], p->word[1].data[4]);
710 debug("PFS 0x%x, ",
711 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 85, 4));
712 debug("BPP 0x%x, ",
713 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 107, 3));
714 debug("NPB 0x%x\n",
715 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 78, 7));
716
717 debug("FW %d, ",
718 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 125, 13));
719 debug("FH %d, ",
720 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 138, 12));
721 debug("Stride %d\n",
722 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 102, 14));
723
724 debug("Width0 %d+1, ",
725 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 116, 3));
726 debug("Width1 %d+1, ",
727 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 119, 3));
728 debug("Width2 %d+1, ",
729 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 122, 3));
730 debug("Width3 %d+1, ",
731 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 125, 3));
732 debug("Offset0 %d, ",
733 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 128, 5));
734 debug("Offset1 %d, ",
735 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 133, 5));
736 debug("Offset2 %d, ",
737 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 138, 5));
738 debug("Offset3 %d\n",
739 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 143, 5));
740#endif
741}
742
743static inline void ipu_ch_params_set_packing(struct ipu_ch_param *p,
744 int red_width, int red_offset,
745 int green_width, int green_offset,
746 int blue_width, int blue_offset,
747 int alpha_width, int alpha_offset)
748{
749 /* Setup red width and offset */
750 ipu_ch_param_set_field(p, 1, 116, 3, red_width - 1);
751 ipu_ch_param_set_field(p, 1, 128, 5, red_offset);
752 /* Setup green width and offset */
753 ipu_ch_param_set_field(p, 1, 119, 3, green_width - 1);
754 ipu_ch_param_set_field(p, 1, 133, 5, green_offset);
755 /* Setup blue width and offset */
756 ipu_ch_param_set_field(p, 1, 122, 3, blue_width - 1);
757 ipu_ch_param_set_field(p, 1, 138, 5, blue_offset);
758 /* Setup alpha width and offset */
759 ipu_ch_param_set_field(p, 1, 125, 3, alpha_width - 1);
760 ipu_ch_param_set_field(p, 1, 143, 5, alpha_offset);
761}
762
763static void ipu_ch_param_init(int ch,
764 uint32_t pixel_fmt, uint32_t width,
765 uint32_t height, uint32_t stride,
766 uint32_t u, uint32_t v,
767 uint32_t uv_stride, dma_addr_t addr0,
768 dma_addr_t addr1)
769{
770 uint32_t u_offset = 0;
771 uint32_t v_offset = 0;
772 struct ipu_ch_param params;
773
774 memset(&params, 0, sizeof(params));
775
776 ipu_ch_param_set_field(&params, 0, 125, 13, width - 1);
777
778 if ((ch == 8) || (ch == 9) || (ch == 10)) {
779 ipu_ch_param_set_field(&params, 0, 138, 12, (height / 2) - 1);
780 ipu_ch_param_set_field(&params, 1, 102, 14, (stride * 2) - 1);
781 } else {
782 ipu_ch_param_set_field(&params, 0, 138, 12, height - 1);
783 ipu_ch_param_set_field(&params, 1, 102, 14, stride - 1);
784 }
785
786 ipu_ch_param_set_field(&params, 1, 0, 29, addr0 >> 3);
787 ipu_ch_param_set_field(&params, 1, 29, 29, addr1 >> 3);
788
789 switch (pixel_fmt) {
790 case IPU_PIX_FMT_GENERIC:
791 /*Represents 8-bit Generic data */
792 ipu_ch_param_set_field(&params, 0, 107, 3, 5); /* bits/pixel */
793 ipu_ch_param_set_field(&params, 1, 85, 4, 6); /* pix format */
794 ipu_ch_param_set_field(&params, 1, 78, 7, 63); /* burst size */
795
796 break;
797 case IPU_PIX_FMT_GENERIC_32:
798 /*Represents 32-bit Generic data */
799 break;
800 case IPU_PIX_FMT_RGB565:
801 ipu_ch_param_set_field(&params, 0, 107, 3, 3); /* bits/pixel */
802 ipu_ch_param_set_field(&params, 1, 85, 4, 7); /* pix format */
803 ipu_ch_param_set_field(&params, 1, 78, 7, 15); /* burst size */
804
805 ipu_ch_params_set_packing(&params, 5, 0, 6, 5, 5, 11, 8, 16);
806 break;
807 case IPU_PIX_FMT_BGR24:
808 ipu_ch_param_set_field(&params, 0, 107, 3, 1); /* bits/pixel */
809 ipu_ch_param_set_field(&params, 1, 85, 4, 7); /* pix format */
810 ipu_ch_param_set_field(&params, 1, 78, 7, 19); /* burst size */
811
812 ipu_ch_params_set_packing(&params, 8, 0, 8, 8, 8, 16, 8, 24);
813 break;
814 case IPU_PIX_FMT_RGB24:
815 case IPU_PIX_FMT_YUV444:
816 ipu_ch_param_set_field(&params, 0, 107, 3, 1); /* bits/pixel */
817 ipu_ch_param_set_field(&params, 1, 85, 4, 7); /* pix format */
818 ipu_ch_param_set_field(&params, 1, 78, 7, 19); /* burst size */
819
820 ipu_ch_params_set_packing(&params, 8, 16, 8, 8, 8, 0, 8, 24);
821 break;
822 case IPU_PIX_FMT_BGRA32:
823 case IPU_PIX_FMT_BGR32:
824 ipu_ch_param_set_field(&params, 0, 107, 3, 0); /* bits/pixel */
825 ipu_ch_param_set_field(&params, 1, 85, 4, 7); /* pix format */
826 ipu_ch_param_set_field(&params, 1, 78, 7, 15); /* burst size */
827
828 ipu_ch_params_set_packing(&params, 8, 8, 8, 16, 8, 24, 8, 0);
829 break;
830 case IPU_PIX_FMT_RGBA32:
831 case IPU_PIX_FMT_RGB32:
832 ipu_ch_param_set_field(&params, 0, 107, 3, 0); /* bits/pixel */
833 ipu_ch_param_set_field(&params, 1, 85, 4, 7); /* pix format */
834 ipu_ch_param_set_field(&params, 1, 78, 7, 15); /* burst size */
835
836 ipu_ch_params_set_packing(&params, 8, 24, 8, 16, 8, 8, 8, 0);
837 break;
838 case IPU_PIX_FMT_ABGR32:
839 ipu_ch_param_set_field(&params, 0, 107, 3, 0); /* bits/pixel */
840 ipu_ch_param_set_field(&params, 1, 85, 4, 7); /* pix format */
841
842 ipu_ch_params_set_packing(&params, 8, 0, 8, 8, 8, 16, 8, 24);
843 break;
844 case IPU_PIX_FMT_UYVY:
845 ipu_ch_param_set_field(&params, 0, 107, 3, 3); /* bits/pixel */
846 ipu_ch_param_set_field(&params, 1, 85, 4, 0xA); /* pix format */
847 ipu_ch_param_set_field(&params, 1, 78, 7, 15); /* burst size */
848 break;
849 case IPU_PIX_FMT_YUYV:
850 ipu_ch_param_set_field(&params, 0, 107, 3, 3); /* bits/pixel */
851 ipu_ch_param_set_field(&params, 1, 85, 4, 0x8); /* pix format */
852 ipu_ch_param_set_field(&params, 1, 78, 7, 31); /* burst size */
853 break;
854 case IPU_PIX_FMT_YUV420P2:
855 case IPU_PIX_FMT_YUV420P:
856 ipu_ch_param_set_field(&params, 1, 85, 4, 2); /* pix format */
857
858 if (uv_stride < stride / 2)
859 uv_stride = stride / 2;
860
861 u_offset = stride * height;
862 v_offset = u_offset + (uv_stride * height / 2);
863 /* burst size */
864 if ((ch == 8) || (ch == 9) || (ch == 10)) {
865 ipu_ch_param_set_field(&params, 1, 78, 7, 15);
866 uv_stride = uv_stride*2;
867 } else {
868 ipu_ch_param_set_field(&params, 1, 78, 7, 31);
869 }
870 break;
871 case IPU_PIX_FMT_YVU422P:
872 /* BPP & pixel format */
873 ipu_ch_param_set_field(&params, 1, 85, 4, 1); /* pix format */
874 ipu_ch_param_set_field(&params, 1, 78, 7, 31); /* burst size */
875
876 if (uv_stride < stride / 2)
877 uv_stride = stride / 2;
878
879 v_offset = (v == 0) ? stride * height : v;
880 u_offset = (u == 0) ? v_offset + v_offset / 2 : u;
881 break;
882 case IPU_PIX_FMT_YUV422P:
883 /* BPP & pixel format */
884 ipu_ch_param_set_field(&params, 1, 85, 4, 1); /* pix format */
885 ipu_ch_param_set_field(&params, 1, 78, 7, 31); /* burst size */
886
887 if (uv_stride < stride / 2)
888 uv_stride = stride / 2;
889
890 u_offset = (u == 0) ? stride * height : u;
891 v_offset = (v == 0) ? u_offset + u_offset / 2 : v;
892 break;
893 case IPU_PIX_FMT_NV12:
894 /* BPP & pixel format */
895 ipu_ch_param_set_field(&params, 1, 85, 4, 4); /* pix format */
896 ipu_ch_param_set_field(&params, 1, 78, 7, 31); /* burst size */
897 uv_stride = stride;
898 u_offset = (u == 0) ? stride * height : u;
899 break;
900 default:
901 puts("mxc ipu: unimplemented pixel format\n");
902 break;
903 }
904
905
906 if (uv_stride)
907 ipu_ch_param_set_field(&params, 1, 128, 14, uv_stride - 1);
908
909 /* Get the uv offset from user when need cropping */
910 if (u || v) {
911 u_offset = u;
912 v_offset = v;
913 }
914
915 /* UBO and VBO are 22-bit */
916 if (u_offset/8 > 0x3fffff)
917 puts("The value of U offset exceeds IPU limitation\n");
918 if (v_offset/8 > 0x3fffff)
919 puts("The value of V offset exceeds IPU limitation\n");
920
921 ipu_ch_param_set_field(&params, 0, 46, 22, u_offset / 8);
922 ipu_ch_param_set_field(&params, 0, 68, 22, v_offset / 8);
923
924 debug("initializing idma ch %d @ %p\n", ch, ipu_ch_param_addr(ch));
925 memcpy(ipu_ch_param_addr(ch), &params, sizeof(params));
926};
927
928/*
929 * This function is called to initialize a buffer for logical IPU channel.
930 *
931 * @param channel Input parameter for the logical channel ID.
932 *
933 * @param type Input parameter which buffer to initialize.
934 *
935 * @param pixel_fmt Input parameter for pixel format of buffer.
936 * Pixel format is a FOURCC ASCII code.
937 *
938 * @param width Input parameter for width of buffer in pixels.
939 *
940 * @param height Input parameter for height of buffer in pixels.
941 *
942 * @param stride Input parameter for stride length of buffer
943 * in pixels.
944 *
945 * @param phyaddr_0 Input parameter buffer 0 physical address.
946 *
947 * @param phyaddr_1 Input parameter buffer 1 physical address.
948 * Setting this to a value other than NULL enables
949 * double buffering mode.
950 *
951 * @param u private u offset for additional cropping,
952 * zero if not used.
953 *
954 * @param v private v offset for additional cropping,
955 * zero if not used.
956 *
957 * @return Returns 0 on success or negative error code on fail
958 */
959int32_t ipu_init_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,
960 uint32_t pixel_fmt,
961 uint16_t width, uint16_t height,
962 uint32_t stride,
963 dma_addr_t phyaddr_0, dma_addr_t phyaddr_1,
964 uint32_t u, uint32_t v)
965{
966 uint32_t reg;
967 uint32_t dma_chan;
968
969 dma_chan = channel_2_dma(channel, type);
970 if (!idma_is_valid(dma_chan))
971 return -EINVAL;
972
973 if (stride < width * bytes_per_pixel(pixel_fmt))
974 stride = width * bytes_per_pixel(pixel_fmt);
975
976 if (stride % 4) {
977 printf(
978 "Stride not 32-bit aligned, stride = %d\n", stride);
979 return -EINVAL;
980 }
981 /* Build parameter memory data for DMA channel */
982 ipu_ch_param_init(dma_chan, pixel_fmt, width, height, stride, u, v, 0,
983 phyaddr_0, phyaddr_1);
984
985 if (ipu_is_dmfc_chan(dma_chan)) {
986 ipu_dmfc_set_wait4eot(dma_chan, width);
987 }
988
989 if (idma_is_set(IDMAC_CHA_PRI, dma_chan))
990 ipu_ch_param_set_high_priority(dma_chan);
991
992 ipu_ch_param_dump(dma_chan);
993
994 reg = __raw_readl(IPU_CHA_DB_MODE_SEL(dma_chan));
995 if (phyaddr_1)
996 reg |= idma_mask(dma_chan);
997 else
998 reg &= ~idma_mask(dma_chan);
999 __raw_writel(reg, IPU_CHA_DB_MODE_SEL(dma_chan));
1000
1001 /* Reset to buffer 0 */
1002 __raw_writel(idma_mask(dma_chan), IPU_CHA_CUR_BUF(dma_chan));
1003
1004 return 0;
1005}
1006
1007/*
1008 * This function enables a logical channel.
1009 *
1010 * @param channel Input parameter for the logical channel ID.
1011 *
1012 * @return This function returns 0 on success or negative error code on
1013 * fail.
1014 */
1015int32_t ipu_enable_channel(ipu_channel_t channel)
1016{
1017 uint32_t reg;
1018 uint32_t in_dma;
1019 uint32_t out_dma;
1020
1021 if (g_channel_enable_mask & (1L << IPU_CHAN_ID(channel))) {
1022 printf("Warning: channel already enabled %d\n",
1023 IPU_CHAN_ID(channel));
1024 }
1025
1026 /* Get input and output dma channels */
1027 out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
1028 in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
1029
1030 if (idma_is_valid(in_dma)) {
1031 reg = __raw_readl(IDMAC_CHA_EN(in_dma));
1032 __raw_writel(reg | idma_mask(in_dma), IDMAC_CHA_EN(in_dma));
1033 }
1034 if (idma_is_valid(out_dma)) {
1035 reg = __raw_readl(IDMAC_CHA_EN(out_dma));
1036 __raw_writel(reg | idma_mask(out_dma), IDMAC_CHA_EN(out_dma));
1037 }
1038
1039 if ((channel == MEM_DC_SYNC) || (channel == MEM_BG_SYNC) ||
1040 (channel == MEM_FG_SYNC))
1041 ipu_dp_dc_enable(channel);
1042
1043 g_channel_enable_mask |= 1L << IPU_CHAN_ID(channel);
1044
1045 return 0;
1046}
1047
1048/*
1049 * This function clear buffer ready for a logical channel.
1050 *
1051 * @param channel Input parameter for the logical channel ID.
1052 *
1053 * @param type Input parameter which buffer to clear.
1054 *
1055 * @param bufNum Input parameter for which buffer number clear
1056 * ready state.
1057 *
1058 */
1059void ipu_clear_buffer_ready(ipu_channel_t channel, ipu_buffer_t type,
1060 uint32_t bufNum)
1061{
1062 uint32_t dma_ch = channel_2_dma(channel, type);
1063
1064 if (!idma_is_valid(dma_ch))
1065 return;
1066
1067 __raw_writel(0xF0000000, IPU_GPR); /* write one to clear */
1068 if (bufNum == 0) {
1069 if (idma_is_set(IPU_CHA_BUF0_RDY, dma_ch)) {
1070 __raw_writel(idma_mask(dma_ch),
1071 IPU_CHA_BUF0_RDY(dma_ch));
1072 }
1073 } else {
1074 if (idma_is_set(IPU_CHA_BUF1_RDY, dma_ch)) {
1075 __raw_writel(idma_mask(dma_ch),
1076 IPU_CHA_BUF1_RDY(dma_ch));
1077 }
1078 }
1079 __raw_writel(0x0, IPU_GPR); /* write one to set */
1080}
1081
1082/*
1083 * This function disables a logical channel.
1084 *
1085 * @param channel Input parameter for the logical channel ID.
1086 *
1087 * @param wait_for_stop Flag to set whether to wait for channel end
1088 * of frame or return immediately.
1089 *
1090 * @return This function returns 0 on success or negative error code on
1091 * fail.
1092 */
1093int32_t ipu_disable_channel(ipu_channel_t channel)
1094{
1095 uint32_t reg;
1096 uint32_t in_dma;
1097 uint32_t out_dma;
1098
1099 if ((g_channel_enable_mask & (1L << IPU_CHAN_ID(channel))) == 0) {
1100 debug("Channel already disabled %d\n",
1101 IPU_CHAN_ID(channel));
1102 return 0;
1103 }
1104
1105 /* Get input and output dma channels */
1106 out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
1107 in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
1108
1109 if ((idma_is_valid(in_dma) &&
1110 !idma_is_set(IDMAC_CHA_EN, in_dma))
1111 && (idma_is_valid(out_dma) &&
1112 !idma_is_set(IDMAC_CHA_EN, out_dma)))
1113 return -EINVAL;
1114
1115 if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC) ||
1116 (channel == MEM_DC_SYNC)) {
1117 ipu_dp_dc_disable(channel, 0);
1118 }
1119
1120 /* Disable DMA channel(s) */
1121 if (idma_is_valid(in_dma)) {
1122 reg = __raw_readl(IDMAC_CHA_EN(in_dma));
1123 __raw_writel(reg & ~idma_mask(in_dma), IDMAC_CHA_EN(in_dma));
1124 __raw_writel(idma_mask(in_dma), IPU_CHA_CUR_BUF(in_dma));
1125 }
1126 if (idma_is_valid(out_dma)) {
1127 reg = __raw_readl(IDMAC_CHA_EN(out_dma));
1128 __raw_writel(reg & ~idma_mask(out_dma), IDMAC_CHA_EN(out_dma));
1129 __raw_writel(idma_mask(out_dma), IPU_CHA_CUR_BUF(out_dma));
1130 }
1131
1132 g_channel_enable_mask &= ~(1L << IPU_CHAN_ID(channel));
1133
1134 /* Set channel buffers NOT to be ready */
1135 if (idma_is_valid(in_dma)) {
1136 ipu_clear_buffer_ready(channel, IPU_VIDEO_IN_BUFFER, 0);
1137 ipu_clear_buffer_ready(channel, IPU_VIDEO_IN_BUFFER, 1);
1138 }
1139 if (idma_is_valid(out_dma)) {
1140 ipu_clear_buffer_ready(channel, IPU_OUTPUT_BUFFER, 0);
1141 ipu_clear_buffer_ready(channel, IPU_OUTPUT_BUFFER, 1);
1142 }
1143
1144 return 0;
1145}
1146
1147uint32_t bytes_per_pixel(uint32_t fmt)
1148{
1149 switch (fmt) {
1150 case IPU_PIX_FMT_GENERIC: /*generic data */
1151 case IPU_PIX_FMT_RGB332:
1152 case IPU_PIX_FMT_YUV420P:
1153 case IPU_PIX_FMT_YUV422P:
1154 return 1;
1155 break;
1156 case IPU_PIX_FMT_RGB565:
1157 case IPU_PIX_FMT_YUYV:
1158 case IPU_PIX_FMT_UYVY:
1159 return 2;
1160 break;
1161 case IPU_PIX_FMT_BGR24:
1162 case IPU_PIX_FMT_RGB24:
1163 return 3;
1164 break;
1165 case IPU_PIX_FMT_GENERIC_32: /*generic data */
1166 case IPU_PIX_FMT_BGR32:
1167 case IPU_PIX_FMT_BGRA32:
1168 case IPU_PIX_FMT_RGB32:
1169 case IPU_PIX_FMT_RGBA32:
1170 case IPU_PIX_FMT_ABGR32:
1171 return 4;
1172 break;
1173 default:
1174 return 1;
1175 break;
1176 }
1177 return 0;
1178}
1179
1180ipu_color_space_t format_to_colorspace(uint32_t fmt)
1181{
1182 switch (fmt) {
1183 case IPU_PIX_FMT_RGB666:
1184 case IPU_PIX_FMT_RGB565:
1185 case IPU_PIX_FMT_BGR24:
1186 case IPU_PIX_FMT_RGB24:
1187 case IPU_PIX_FMT_BGR32:
1188 case IPU_PIX_FMT_BGRA32:
1189 case IPU_PIX_FMT_RGB32:
1190 case IPU_PIX_FMT_RGBA32:
1191 case IPU_PIX_FMT_ABGR32:
1192 case IPU_PIX_FMT_LVDS666:
1193 case IPU_PIX_FMT_LVDS888:
1194 return RGB;
1195 break;
1196
1197 default:
1198 return YCbCr;
1199 break;
1200 }
1201 return RGB;
1202}
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