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Commit | Line | Data |
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c2539483 | 1 | /* |
147fd3ac | 2 | * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH |
c2539483 SG |
3 | * Copyright (c) 2015 Google, Inc |
4 | * Copyright 2014 Rockchip Inc. | |
5 | * | |
6 | * SPDX-License-Identifier: GPL-2.0+ | |
7 | */ | |
8 | ||
9 | #include <common.h> | |
10 | #include <clk.h> | |
11 | #include <display.h> | |
12 | #include <dm.h> | |
cc232a9d | 13 | #include <dw_hdmi.h> |
c2539483 SG |
14 | #include <edid.h> |
15 | #include <regmap.h> | |
16 | #include <syscon.h> | |
17 | #include <asm/gpio.h> | |
12085239 | 18 | #include <asm/hardware.h> |
c2539483 SG |
19 | #include <asm/io.h> |
20 | #include <asm/arch/clock.h> | |
147fd3ac PT |
21 | #include <asm/arch/hardware.h> |
22 | #include "rk_hdmi.h" | |
23 | #include "rk_vop.h" /* for rk_vop_probe_regulators */ | |
c2539483 | 24 | |
c2539483 SG |
25 | static const struct hdmi_phy_config rockchip_phy_config[] = { |
26 | { | |
0fc41e55 | 27 | .mpixelclock = 74250000, |
c2539483 SG |
28 | .sym_ctr = 0x8009, .term = 0x0004, .vlev_ctr = 0x0272, |
29 | }, { | |
0fc41e55 | 30 | .mpixelclock = 148500000, |
c2539483 SG |
31 | .sym_ctr = 0x802b, .term = 0x0004, .vlev_ctr = 0x028d, |
32 | }, { | |
0fc41e55 | 33 | .mpixelclock = 297000000, |
c2539483 | 34 | .sym_ctr = 0x8039, .term = 0x0005, .vlev_ctr = 0x028d, |
f210e557 PT |
35 | }, { |
36 | .mpixelclock = 584000000, | |
37 | .sym_ctr = 0x8039, .term = 0x0000, .vlev_ctr = 0x019d, | |
c2539483 SG |
38 | }, { |
39 | .mpixelclock = ~0ul, | |
40 | .sym_ctr = 0x0000, .term = 0x0000, .vlev_ctr = 0x0000, | |
41 | } | |
42 | }; | |
43 | ||
44 | static const struct hdmi_mpll_config rockchip_mpll_cfg[] = { | |
45 | { | |
0fc41e55 | 46 | .mpixelclock = 40000000, |
c2539483 SG |
47 | .cpce = 0x00b3, .gmp = 0x0000, .curr = 0x0018, |
48 | }, { | |
0fc41e55 | 49 | .mpixelclock = 65000000, |
c2539483 SG |
50 | .cpce = 0x0072, .gmp = 0x0001, .curr = 0x0028, |
51 | }, { | |
0fc41e55 | 52 | .mpixelclock = 66000000, |
c2539483 SG |
53 | .cpce = 0x013e, .gmp = 0x0003, .curr = 0x0038, |
54 | }, { | |
94412745 | 55 | .mpixelclock = 83500000, |
c2539483 SG |
56 | .cpce = 0x0072, .gmp = 0x0001, .curr = 0x0028, |
57 | }, { | |
0fc41e55 | 58 | .mpixelclock = 146250000, |
c2539483 SG |
59 | .cpce = 0x0051, .gmp = 0x0002, .curr = 0x0038, |
60 | }, { | |
0fc41e55 | 61 | .mpixelclock = 148500000, |
c2539483 | 62 | .cpce = 0x0051, .gmp = 0x0003, .curr = 0x0000, |
f210e557 PT |
63 | }, { |
64 | .mpixelclock = 272000000, | |
65 | .cpce = 0x0040, .gmp = 0x0003, .curr = 0x0000, | |
66 | }, { | |
67 | .mpixelclock = 340000000, | |
68 | .cpce = 0x0040, .gmp = 0x0003, .curr = 0x0000, | |
c2539483 SG |
69 | }, { |
70 | .mpixelclock = ~0ul, | |
71 | .cpce = 0x0051, .gmp = 0x0003, .curr = 0x0000, | |
72 | } | |
73 | }; | |
74 | ||
147fd3ac | 75 | int rk_hdmi_read_edid(struct udevice *dev, u8 *buf, int buf_size) |
c2539483 SG |
76 | { |
77 | struct rk_hdmi_priv *priv = dev_get_priv(dev); | |
c2539483 | 78 | |
cc232a9d | 79 | return dw_hdmi_read_edid(&priv->hdmi, buf, buf_size); |
c2539483 SG |
80 | } |
81 | ||
147fd3ac | 82 | int rk_hdmi_ofdata_to_platdata(struct udevice *dev) |
c2539483 SG |
83 | { |
84 | struct rk_hdmi_priv *priv = dev_get_priv(dev); | |
cc232a9d JS |
85 | struct dw_hdmi *hdmi = &priv->hdmi; |
86 | ||
18e48776 | 87 | hdmi->ioaddr = (ulong)dev_read_addr(dev); |
cc232a9d JS |
88 | hdmi->mpll_cfg = rockchip_mpll_cfg; |
89 | hdmi->phy_cfg = rockchip_phy_config; | |
147fd3ac PT |
90 | |
91 | /* hdmi->i2c_clk_{high,low} are set up by the SoC driver */ | |
92 | ||
cc232a9d JS |
93 | hdmi->reg_io_width = 4; |
94 | hdmi->phy_set = dw_hdmi_phy_cfg; | |
c2539483 | 95 | |
c2539483 SG |
96 | priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); |
97 | ||
98 | return 0; | |
99 | } | |
100 | ||
147fd3ac PT |
101 | void rk_hdmi_probe_regulators(struct udevice *dev, |
102 | const char * const *names, int cnt) | |
103 | { | |
104 | rk_vop_probe_regulators(dev, names, cnt); | |
105 | } | |
106 | ||
107 | int rk_hdmi_probe(struct udevice *dev) | |
c2539483 | 108 | { |
c2539483 | 109 | struct rk_hdmi_priv *priv = dev_get_priv(dev); |
cc232a9d | 110 | struct dw_hdmi *hdmi = &priv->hdmi; |
c2539483 | 111 | int ret; |
c2539483 | 112 | |
cc232a9d | 113 | ret = dw_hdmi_phy_wait_for_hpd(hdmi); |
c2539483 SG |
114 | if (ret < 0) { |
115 | debug("hdmi can not get hpd signal\n"); | |
116 | return -1; | |
117 | } | |
118 | ||
cc232a9d JS |
119 | dw_hdmi_init(hdmi); |
120 | dw_hdmi_phy_init(hdmi); | |
c2539483 SG |
121 | |
122 | return 0; | |
123 | } |