[people/ms/u-boot.git] / drivers / video / rockchip / rk_vop.c

/*
 * Copyright (c) 2015 Google, Inc
 * Copyright 2014 Rockchip Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <clk.h>
#include <display.h>
#include <dm.h>
#include <edid.h>
#include <regmap.h>
#include <syscon.h>
#include <video.h>
#include <asm/gpio.h>
#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/edp_rk3288.h>
#include <asm/arch/vop_rk3288.h>
#include <dm/device-internal.h>
#include <dm/uclass-internal.h>
#include <power/regulator.h>
#include "rk_vop.h"

DECLARE_GLOBAL_DATA_PTR;

enum vop_pol {
	HSYNC_POSITIVE = 0,
	VSYNC_POSITIVE = 1,
	DEN_NEGATIVE   = 2,
	DCLK_INVERT    = 3
};

static void rkvop_enable(struct rk3288_vop *regs, ulong fbbase,
			 int fb_bits_per_pixel,
			 const struct display_timing *edid)
{
	u32 lb_mode;
	u32 rgb_mode;
	u32 hactive = edid->hactive.typ;
	u32 vactive = edid->vactive.typ;

	writel(V_ACT_WIDTH(hactive - 1) | V_ACT_HEIGHT(vactive - 1),
	       &regs->win0_act_info);

	writel(V_DSP_XST(edid->hsync_len.typ + edid->hback_porch.typ) |
	       V_DSP_YST(edid->vsync_len.typ + edid->vback_porch.typ),
	       &regs->win0_dsp_st);

	writel(V_DSP_WIDTH(hactive - 1) |
		V_DSP_HEIGHT(vactive - 1),
		&regs->win0_dsp_info);

	clrsetbits_le32(&regs->win0_color_key, M_WIN0_KEY_EN | M_WIN0_KEY_COLOR,
			V_WIN0_KEY_EN(0) | V_WIN0_KEY_COLOR(0));

	switch (fb_bits_per_pixel) {
	case 16:
		rgb_mode = RGB565;
		writel(V_RGB565_VIRWIDTH(hactive), &regs->win0_vir);
		break;
	case 24:
		rgb_mode = RGB888;
		writel(V_RGB888_VIRWIDTH(hactive), &regs->win0_vir);
		break;
	case 32:
	default:
		rgb_mode = ARGB8888;
		writel(V_ARGB888_VIRWIDTH(hactive), &regs->win0_vir);
		break;
	}

	if (hactive > 2560)
		lb_mode = LB_RGB_3840X2;
	else if (hactive > 1920)
		lb_mode = LB_RGB_2560X4;
	else if (hactive > 1280)
		lb_mode = LB_RGB_1920X5;
	else
		lb_mode = LB_RGB_1280X8;

	clrsetbits_le32(&regs->win0_ctrl0,
			M_WIN0_LB_MODE | M_WIN0_DATA_FMT | M_WIN0_EN,
			V_WIN0_LB_MODE(lb_mode) | V_WIN0_DATA_FMT(rgb_mode) |
			V_WIN0_EN(1));

	writel(fbbase, &regs->win0_yrgb_mst);
	writel(0x01, &regs->reg_cfg_done); /* enable reg config */
}

static void rkvop_set_pin_polarity(struct udevice *dev,
				   enum vop_modes mode, u32 polarity)
{
	struct rkvop_driverdata *ops =
		(struct rkvop_driverdata *)dev_get_driver_data(dev);

	if (ops->set_pin_polarity)
		ops->set_pin_polarity(dev, mode, polarity);
}

static void rkvop_enable_output(struct udevice *dev, enum vop_modes mode)
{
	struct rk_vop_priv *priv = dev_get_priv(dev);
	struct rk3288_vop *regs = priv->regs;

	/* remove from standby */
	clrbits_le32(&regs->sys_ctrl, V_STANDBY_EN(1));

	switch (mode) {
	case VOP_MODE_HDMI:
		clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
				V_HDMI_OUT_EN(1));
		break;

	case VOP_MODE_EDP:
		clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
				V_EDP_OUT_EN(1));
		break;

	case VOP_MODE_LVDS:
		clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
				V_RGB_OUT_EN(1));
		break;

	case VOP_MODE_MIPI:
		clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
				V_MIPI_OUT_EN(1));
		break;

	default:
		debug("%s: unsupported output mode %x\n", __func__, mode);
	}
}

static void rkvop_mode_set(struct udevice *dev,
			   const struct display_timing *edid,
			   enum vop_modes mode)
{
	struct rk_vop_priv *priv = dev_get_priv(dev);
	struct rk3288_vop *regs = priv->regs;
	struct rkvop_driverdata *data =
		(struct rkvop_driverdata *)dev_get_driver_data(dev);

	u32 hactive = edid->hactive.typ;
	u32 vactive = edid->vactive.typ;
	u32 hsync_len = edid->hsync_len.typ;
	u32 hback_porch = edid->hback_porch.typ;
	u32 vsync_len = edid->vsync_len.typ;
	u32 vback_porch = edid->vback_porch.typ;
	u32 hfront_porch = edid->hfront_porch.typ;
	u32 vfront_porch = edid->vfront_porch.typ;
	int mode_flags;
	u32 pin_polarity;

	pin_polarity = BIT(DCLK_INVERT);
	if (edid->flags & DISPLAY_FLAGS_HSYNC_HIGH)
		pin_polarity |= BIT(HSYNC_POSITIVE);
	if (edid->flags & DISPLAY_FLAGS_VSYNC_HIGH)
		pin_polarity |= BIT(VSYNC_POSITIVE);

	rkvop_set_pin_polarity(dev, mode, pin_polarity);
	rkvop_enable_output(dev, mode);

	mode_flags = 0;  /* RGB888 */
	if ((data->features & VOP_FEATURE_OUTPUT_10BIT) &&
	    (mode == VOP_MODE_HDMI || mode == VOP_MODE_EDP))
		mode_flags = 15;  /* RGBaaa */

	clrsetbits_le32(&regs->dsp_ctrl0, M_DSP_OUT_MODE,
			V_DSP_OUT_MODE(mode_flags));

	writel(V_HSYNC(hsync_len) |
	       V_HORPRD(hsync_len + hback_porch + hactive + hfront_porch),
			&regs->dsp_htotal_hs_end);

	writel(V_HEAP(hsync_len + hback_porch + hactive) |
	       V_HASP(hsync_len + hback_porch),
	       &regs->dsp_hact_st_end);

	writel(V_VSYNC(vsync_len) |
	       V_VERPRD(vsync_len + vback_porch + vactive + vfront_porch),
	       &regs->dsp_vtotal_vs_end);

	writel(V_VAEP(vsync_len + vback_porch + vactive)|
	       V_VASP(vsync_len + vback_porch),
	       &regs->dsp_vact_st_end);

	writel(V_HEAP(hsync_len + hback_porch + hactive) |
	       V_HASP(hsync_len + hback_porch),
	       &regs->post_dsp_hact_info);

	writel(V_VAEP(vsync_len + vback_porch + vactive)|
	       V_VASP(vsync_len + vback_porch),
	       &regs->post_dsp_vact_info);

	writel(0x01, &regs->reg_cfg_done); /* enable reg config */
}

/**
 * rk_display_init() - Try to enable the given display device
 *
 * This function performs many steps:
 * - Finds the display device being referenced by @ep_node
 * - Puts the VOP's ID into its uclass platform data
 * - Probes the device to set it up
 * - Reads the EDID timing information
 * - Sets up the VOP clocks, etc. for the selected pixel clock and display mode
 * - Enables the display (the display device handles this and will do different
 *     things depending on the display type)
 * - Tells the uclass about the display resolution so that the console will
 *     appear correctly
 *
 * @dev:	VOP device that we want to connect to the display
 * @fbbase:	Frame buffer address
 * @ep_node:	Device tree node to process - this is the offset of an endpoint
 *		node within the VOP's 'port' list.
 * @return 0 if OK, -ve if something went wrong
 */
static int rk_display_init(struct udevice *dev, ulong fbbase, int ep_node)
{
	struct video_priv *uc_priv = dev_get_uclass_priv(dev);
	const void *blob = gd->fdt_blob;
	struct rk_vop_priv *priv = dev_get_priv(dev);
	int vop_id, remote_vop_id;
	struct rk3288_vop *regs = priv->regs;
	struct display_timing timing;
	struct udevice *disp;
	int ret, remote, i, offset;
	struct display_plat *disp_uc_plat;
	struct clk clk;
	enum video_log2_bpp l2bpp;

	vop_id = fdtdec_get_int(blob, ep_node, "reg", -1);
	debug("vop_id=%d\n", vop_id);
	remote = fdtdec_lookup_phandle(blob, ep_node, "remote-endpoint");
	if (remote < 0)
		return -EINVAL;
	remote_vop_id = fdtdec_get_int(blob, remote, "reg", -1);
	debug("remote vop_id=%d\n", remote_vop_id);

	for (i = 0, offset = remote; i < 3 && offset > 0; i++)
		offset = fdt_parent_offset(blob, offset);
	if (offset < 0) {
		debug("%s: Invalid remote-endpoint position\n", dev->name);
		return -EINVAL;
	}

	ret = uclass_find_device_by_of_offset(UCLASS_DISPLAY, offset, &disp);
	if (ret) {
		debug("%s: device '%s' display not found (ret=%d)\n", __func__,
		      dev->name, ret);
		return ret;
	}

	disp_uc_plat = dev_get_uclass_platdata(disp);
	debug("Found device '%s', disp_uc_priv=%p\n", disp->name, disp_uc_plat);
	if (display_in_use(disp)) {
		debug("   - device in use\n");
		return -EBUSY;
	}

	disp_uc_plat->source_id = remote_vop_id;
	disp_uc_plat->src_dev = dev;

	ret = device_probe(disp);
	if (ret) {
		debug("%s: device '%s' display won't probe (ret=%d)\n",
		      __func__, dev->name, ret);
		return ret;
	}

	ret = display_read_timing(disp, &timing);
	if (ret) {
		debug("%s: Failed to read timings\n", __func__);
		return ret;
	}

	ret = clk_get_by_index(dev, 1, &clk);
	if (!ret)
		ret = clk_set_rate(&clk, timing.pixelclock.typ);
	if (IS_ERR_VALUE(ret)) {
		debug("%s: Failed to set pixel clock: ret=%d\n", __func__, ret);
		return ret;
	}

	/* Set bitwidth for vop display according to vop mode */
	switch (vop_id) {
	case VOP_MODE_EDP:
	case VOP_MODE_LVDS:
		l2bpp = VIDEO_BPP16;
		break;
	case VOP_MODE_HDMI:
	case VOP_MODE_MIPI:
		l2bpp = VIDEO_BPP32;
		break;
	default:
		l2bpp = VIDEO_BPP16;
	}

	rkvop_mode_set(dev, &timing, vop_id);
	rkvop_enable(regs, fbbase, 1 << l2bpp, &timing);

	ret = display_enable(disp, 1 << l2bpp, &timing);
	if (ret)
		return ret;

	uc_priv->xsize = timing.hactive.typ;
	uc_priv->ysize = timing.vactive.typ;
	uc_priv->bpix = l2bpp;
	debug("fb=%lx, size=%d %d\n", fbbase, uc_priv->xsize, uc_priv->ysize);

	return 0;
}

void rk_vop_probe_regulators(struct udevice *dev,
			     const char * const *names, int cnt)
{
	int i, ret;
	const char *name;
	struct udevice *reg;

	for (i = 0; i < cnt; ++i) {
		name = names[i];
		debug("%s: probing regulator '%s'\n", dev->name, name);

		ret = regulator_autoset_by_name(name, &reg);
		if (!ret)
			ret = regulator_set_enable(reg, true);
	}
}

int rk_vop_probe(struct udevice *dev)
{
	struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
	const void *blob = gd->fdt_blob;
	struct rk_vop_priv *priv = dev_get_priv(dev);
	int ret = 0;
	int port, node;

	/* Before relocation we don't need to do anything */
	if (!(gd->flags & GD_FLG_RELOC))
		return 0;

	priv->regs = (struct rk3288_vop *)devfdt_get_addr(dev);

	/*
	 * Try all the ports until we find one that works. In practice this
	 * tries EDP first if available, then HDMI.
	 *
	 * Note that rockchip_vop_set_clk() always uses NPLL as the source
	 * clock so it is currently not possible to use more than one display
	 * device simultaneously.
	 */
	port = fdt_subnode_offset(blob, dev_of_offset(dev), "port");
	if (port < 0)
		return -EINVAL;
	for (node = fdt_first_subnode(blob, port);
	     node > 0;
	     node = fdt_next_subnode(blob, node)) {
		ret = rk_display_init(dev, plat->base, node);
		if (ret)
			debug("Device failed: ret=%d\n", ret);
		if (!ret)
			break;
	}
	video_set_flush_dcache(dev, 1);

	return ret;
}

int rk_vop_bind(struct udevice *dev)
{
	struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);

	plat->size = 4 * (CONFIG_VIDEO_ROCKCHIP_MAX_XRES *
			  CONFIG_VIDEO_ROCKCHIP_MAX_YRES);

	return 0;
}
Commit	Line	Data
7b7ad5c3 SG	1	/*
	2	* Copyright (c) 2015 Google, Inc
	3	* Copyright 2014 Rockchip Inc.
	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
	7
	8	#include <common.h>
	9	#include <clk.h>
	10	#include <display.h>
	11	#include <dm.h>
	12	#include <edid.h>
	13	#include <regmap.h>
	14	#include <syscon.h>
	15	#include <video.h>
	16	#include <asm/gpio.h>
	17	#include <asm/hardware.h>
	18	#include <asm/io.h>
	19	#include <asm/arch/clock.h>
7b7ad5c3	20	#include <asm/arch/edp_rk3288.h>
7b7ad5c3 SG	21	#include <asm/arch/vop_rk3288.h>
	22	#include <dm/device-internal.h>
	23	#include <dm/uclass-internal.h>
7b7ad5c3	24	#include <power/regulator.h>
d46d4047	25	#include "rk_vop.h"
7b7ad5c3 SG	26
	27	DECLARE_GLOBAL_DATA_PTR;
	28
d46d4047 PT	29	enum vop_pol {
	30	HSYNC_POSITIVE = 0,
	31	VSYNC_POSITIVE = 1,
	32	DEN_NEGATIVE = 2,
	33	DCLK_INVERT = 3
7b7ad5c3 SG	34	};
7b7ad5c3 SG	35
d46d4047 PT	36	static void rkvop_enable(struct rk3288_vop *regs, ulong fbbase,
	37	int fb_bits_per_pixel,
	38	const struct display_timing *edid)
7b7ad5c3 SG	39	{
	40	u32 lb_mode;
	41	u32 rgb_mode;
	42	u32 hactive = edid->hactive.typ;
	43	u32 vactive = edid->vactive.typ;
	44
	45	writel(V_ACT_WIDTH(hactive - 1) \| V_ACT_HEIGHT(vactive - 1),
	46	&regs->win0_act_info);
	47
	48	writel(V_DSP_XST(edid->hsync_len.typ + edid->hback_porch.typ) \|
	49	V_DSP_YST(edid->vsync_len.typ + edid->vback_porch.typ),
	50	&regs->win0_dsp_st);
	51
	52	writel(V_DSP_WIDTH(hactive - 1) \|
	53	V_DSP_HEIGHT(vactive - 1),
	54	&regs->win0_dsp_info);
	55
	56	clrsetbits_le32(&regs->win0_color_key, M_WIN0_KEY_EN \| M_WIN0_KEY_COLOR,
	57	V_WIN0_KEY_EN(0) \| V_WIN0_KEY_COLOR(0));
	58
	59	switch (fb_bits_per_pixel) {
	60	case 16:
	61	rgb_mode = RGB565;
	62	writel(V_RGB565_VIRWIDTH(hactive), &regs->win0_vir);
	63	break;
	64	case 24:
	65	rgb_mode = RGB888;
	66	writel(V_RGB888_VIRWIDTH(hactive), &regs->win0_vir);
	67	break;
	68	case 32:
	69	default:
	70	rgb_mode = ARGB8888;
	71	writel(V_ARGB888_VIRWIDTH(hactive), &regs->win0_vir);
	72	break;
	73	}
	74
	75	if (hactive > 2560)
	76	lb_mode = LB_RGB_3840X2;
	77	else if (hactive > 1920)
	78	lb_mode = LB_RGB_2560X4;
	79	else if (hactive > 1280)
	80	lb_mode = LB_RGB_1920X5;
	81	else
	82	lb_mode = LB_RGB_1280X8;
	83
	84	clrsetbits_le32(&regs->win0_ctrl0,
	85	M_WIN0_LB_MODE \| M_WIN0_DATA_FMT \| M_WIN0_EN,
	86	V_WIN0_LB_MODE(lb_mode) \| V_WIN0_DATA_FMT(rgb_mode) \|
	87	V_WIN0_EN(1));
	88
	89	writel(fbbase, &regs->win0_yrgb_mst);
	90	writel(0x01, &regs->reg_cfg_done); /* enable reg config */
	91	}
	92
d46d4047 PT	93	static void rkvop_set_pin_polarity(struct udevice *dev,
d46d4047 PT	94	enum vop_modes mode, u32 polarity)
7b7ad5c3	95	{
d46d4047 PT	96	struct rkvop_driverdata *ops =
	97	(struct rkvop_driverdata *)dev_get_driver_data(dev);
	98
	99	if (ops->set_pin_polarity)
	100	ops->set_pin_polarity(dev, mode, polarity);
	101	}
	102
	103	static void rkvop_enable_output(struct udevice *dev, enum vop_modes mode)
	104	{
	105	struct rk_vop_priv *priv = dev_get_priv(dev);
	106	struct rk3288_vop *regs = priv->regs;
7b7ad5c3	107
6b5a09aa SG	108	/* remove from standby */
	109	clrbits_le32(&regs->sys_ctrl, V_STANDBY_EN(1));
	110
7b7ad5c3 SG	111	switch (mode) {
	112	case VOP_MODE_HDMI:
	113	clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
	114	V_HDMI_OUT_EN(1));
	115	break;
d46d4047	116
7b7ad5c3	117	case VOP_MODE_EDP:
7b7ad5c3 SG	118	clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
	119	V_EDP_OUT_EN(1));
	120	break;
d46d4047	121
85307835 JC	122	case VOP_MODE_LVDS:
	123	clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
	124	V_RGB_OUT_EN(1));
	125	break;
d46d4047	126
9f819931 EG	127	case VOP_MODE_MIPI:
	128	clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
	129	V_MIPI_OUT_EN(1));
d46d4047 PT	130	break;
	131
	132	default:
	133	debug("%s: unsupported output mode %x\n", __func__, mode);
7b7ad5c3	134	}
d46d4047	135	}
7b7ad5c3	136
d46d4047 PT	137	static void rkvop_mode_set(struct udevice *dev,
	138	const struct display_timing *edid,
	139	enum vop_modes mode)
	140	{
	141	struct rk_vop_priv *priv = dev_get_priv(dev);
	142	struct rk3288_vop *regs = priv->regs;
	143	struct rkvop_driverdata *data =
	144	(struct rkvop_driverdata *)dev_get_driver_data(dev);
85307835	145
d46d4047 PT	146	u32 hactive = edid->hactive.typ;
	147	u32 vactive = edid->vactive.typ;
	148	u32 hsync_len = edid->hsync_len.typ;
	149	u32 hback_porch = edid->hback_porch.typ;
	150	u32 vsync_len = edid->vsync_len.typ;
	151	u32 vback_porch = edid->vback_porch.typ;
	152	u32 hfront_porch = edid->hfront_porch.typ;
	153	u32 vfront_porch = edid->vfront_porch.typ;
	154	int mode_flags;
	155	u32 pin_polarity;
	156
	157	pin_polarity = BIT(DCLK_INVERT);
	158	if (edid->flags & DISPLAY_FLAGS_HSYNC_HIGH)
	159	pin_polarity \|= BIT(HSYNC_POSITIVE);
	160	if (edid->flags & DISPLAY_FLAGS_VSYNC_HIGH)
	161	pin_polarity \|= BIT(VSYNC_POSITIVE);
	162
	163	rkvop_set_pin_polarity(dev, mode, pin_polarity);
	164	rkvop_enable_output(dev, mode);
7b7ad5c3	165
d46d4047 PT	166	mode_flags = 0; /* RGB888 */
	167	if ((data->features & VOP_FEATURE_OUTPUT_10BIT) &&
	168	(mode == VOP_MODE_HDMI \|\| mode == VOP_MODE_EDP))
	169	mode_flags = 15; /* RGBaaa */
	170
	171	clrsetbits_le32(&regs->dsp_ctrl0, M_DSP_OUT_MODE,
	172	V_DSP_OUT_MODE(mode_flags));
7b7ad5c3 SG	173
	174	writel(V_HSYNC(hsync_len) \|
	175	V_HORPRD(hsync_len + hback_porch + hactive + hfront_porch),
	176	&regs->dsp_htotal_hs_end);
	177
	178	writel(V_HEAP(hsync_len + hback_porch + hactive) \|
	179	V_HASP(hsync_len + hback_porch),
	180	&regs->dsp_hact_st_end);
	181
	182	writel(V_VSYNC(vsync_len) \|
	183	V_VERPRD(vsync_len + vback_porch + vactive + vfront_porch),
	184	&regs->dsp_vtotal_vs_end);
	185
	186	writel(V_VAEP(vsync_len + vback_porch + vactive)\|
	187	V_VASP(vsync_len + vback_porch),
	188	&regs->dsp_vact_st_end);
	189
	190	writel(V_HEAP(hsync_len + hback_porch + hactive) \|
	191	V_HASP(hsync_len + hback_porch),
	192	&regs->post_dsp_hact_info);
	193
	194	writel(V_VAEP(vsync_len + vback_porch + vactive)\|
	195	V_VASP(vsync_len + vback_porch),
	196	&regs->post_dsp_vact_info);
	197
	198	writel(0x01, &regs->reg_cfg_done); /* enable reg config */
	199	}
	200
	201	/**
	202	* rk_display_init() - Try to enable the given display device
	203	*
	204	* This function performs many steps:
	205	* - Finds the display device being referenced by @ep_node
	206	* - Puts the VOP's ID into its uclass platform data
	207	* - Probes the device to set it up
	208	* - Reads the EDID timing information
	209	* - Sets up the VOP clocks, etc. for the selected pixel clock and display mode
	210	* - Enables the display (the display device handles this and will do different
	211	* things depending on the display type)
	212	* - Tells the uclass about the display resolution so that the console will
	213	* appear correctly
	214	*
	215	* @dev: VOP device that we want to connect to the display
	216	* @fbbase: Frame buffer address
7b7ad5c3 SG	217	* @ep_node: Device tree node to process - this is the offset of an endpoint
	218	* node within the VOP's 'port' list.
	219	* @return 0 if OK, -ve if something went wrong
	220	*/
d46d4047	221	static int rk_display_init(struct udevice *dev, ulong fbbase, int ep_node)
7b7ad5c3 SG	222	{
	223	struct video_priv *uc_priv = dev_get_uclass_priv(dev);
	224	const void *blob = gd->fdt_blob;
	225	struct rk_vop_priv *priv = dev_get_priv(dev);
	226	int vop_id, remote_vop_id;
	227	struct rk3288_vop *regs = priv->regs;
	228	struct display_timing timing;
	229	struct udevice *disp;
	230	int ret, remote, i, offset;
	231	struct display_plat *disp_uc_plat;
135aa950	232	struct clk clk;
8aed0d77	233	enum video_log2_bpp l2bpp;
7b7ad5c3 SG	234
	235	vop_id = fdtdec_get_int(blob, ep_node, "reg", -1);
	236	debug("vop_id=%d\n", vop_id);
	237	remote = fdtdec_lookup_phandle(blob, ep_node, "remote-endpoint");
	238	if (remote < 0)
	239	return -EINVAL;
	240	remote_vop_id = fdtdec_get_int(blob, remote, "reg", -1);
	241	debug("remote vop_id=%d\n", remote_vop_id);
	242
	243	for (i = 0, offset = remote; i < 3 && offset > 0; i++)
	244	offset = fdt_parent_offset(blob, offset);
	245	if (offset < 0) {
	246	debug("%s: Invalid remote-endpoint position\n", dev->name);
	247	return -EINVAL;
	248	}
	249
	250	ret = uclass_find_device_by_of_offset(UCLASS_DISPLAY, offset, &disp);
	251	if (ret) {
	252	debug("%s: device '%s' display not found (ret=%d)\n", __func__,
	253	dev->name, ret);
	254	return ret;
	255	}
	256
	257	disp_uc_plat = dev_get_uclass_platdata(disp);
	258	debug("Found device '%s', disp_uc_priv=%p\n", disp->name, disp_uc_plat);
987a404a SG	259	if (display_in_use(disp)) {
	260	debug(" - device in use\n");
	261	return -EBUSY;
	262	}
	263
7b7ad5c3 SG	264	disp_uc_plat->source_id = remote_vop_id;
	265	disp_uc_plat->src_dev = dev;
	266
	267	ret = device_probe(disp);
	268	if (ret) {
	269	debug("%s: device '%s' display won't probe (ret=%d)\n",
	270	__func__, dev->name, ret);
	271	return ret;
	272	}
	273
	274	ret = display_read_timing(disp, &timing);
	275	if (ret) {
	276	debug("%s: Failed to read timings\n", __func__);
	277	return ret;
	278	}
	279
9ed68260	280	ret = clk_get_by_index(dev, 1, &clk);
135aa950 SW	281	if (!ret)
135aa950 SW	282	ret = clk_set_rate(&clk, timing.pixelclock.typ);
e07e5bde	283	if (IS_ERR_VALUE(ret)) {
7b7ad5c3 SG	284	debug("%s: Failed to set pixel clock: ret=%d\n", __func__, ret);
	285	return ret;
	286	}
	287
8aed0d77 EG	288	/* Set bitwidth for vop display according to vop mode */
	289	switch (vop_id) {
	290	case VOP_MODE_EDP:
8aed0d77 EG	291	case VOP_MODE_LVDS:
	292	l2bpp = VIDEO_BPP16;
	293	break;
d46d4047	294	case VOP_MODE_HDMI:
8aed0d77 EG	295	case VOP_MODE_MIPI:
	296	l2bpp = VIDEO_BPP32;
	297	break;
	298	default:
	299	l2bpp = VIDEO_BPP16;
	300	}
7b7ad5c3	301
d46d4047	302	rkvop_mode_set(dev, &timing, vop_id);
7b7ad5c3 SG	303	rkvop_enable(regs, fbbase, 1 << l2bpp, &timing);
	304
	305	ret = display_enable(disp, 1 << l2bpp, &timing);
	306	if (ret)
	307	return ret;
	308
	309	uc_priv->xsize = timing.hactive.typ;
	310	uc_priv->ysize = timing.vactive.typ;
	311	uc_priv->bpix = l2bpp;
	312	debug("fb=%lx, size=%d %d\n", fbbase, uc_priv->xsize, uc_priv->ysize);
	313
	314	return 0;
	315	}
	316
d46d4047 PT	317	void rk_vop_probe_regulators(struct udevice *dev,
	318	const char * const *names, int cnt)
	319	{
	320	int i, ret;
	321	const char *name;
	322	struct udevice *reg;
	323
	324	for (i = 0; i < cnt; ++i) {
	325	name = names[i];
	326	debug("%s: probing regulator '%s'\n", dev->name, name);
	327
	328	ret = regulator_autoset_by_name(name, &reg);
	329	if (!ret)
	330	ret = regulator_set_enable(reg, true);
	331	}
	332	}
	333
	334	int rk_vop_probe(struct udevice *dev)
7b7ad5c3 SG	335	{
	336	struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
	337	const void *blob = gd->fdt_blob;
	338	struct rk_vop_priv *priv = dev_get_priv(dev);
d46d4047 PT	339	int ret = 0;
d46d4047 PT	340	int port, node;
7b7ad5c3 SG	341
	342	/* Before relocation we don't need to do anything */
	343	if (!(gd->flags & GD_FLG_RELOC))
	344	return 0;
	345
a821c4af	346	priv->regs = (struct rk3288_vop *)devfdt_get_addr(dev);
7b7ad5c3	347
7b7ad5c3 SG	348	/*
	349	* Try all the ports until we find one that works. In practice this
	350	* tries EDP first if available, then HDMI.
987a404a SG	351	*
	352	* Note that rockchip_vop_set_clk() always uses NPLL as the source
	353	* clock so it is currently not possible to use more than one display
	354	* device simultaneously.
7b7ad5c3	355	*/
e160f7d4	356	port = fdt_subnode_offset(blob, dev_of_offset(dev), "port");
7b7ad5c3 SG	357	if (port < 0)
	358	return -EINVAL;
	359	for (node = fdt_first_subnode(blob, port);
	360	node > 0;
	361	node = fdt_next_subnode(blob, node)) {
8aed0d77	362	ret = rk_display_init(dev, plat->base, node);
7b7ad5c3 SG	363	if (ret)
	364	debug("Device failed: ret=%d\n", ret);
	365	if (!ret)
	366	break;
	367	}
b55e04a0	368	video_set_flush_dcache(dev, 1);
7b7ad5c3 SG	369
	370	return ret;
	371	}
	372
d46d4047	373	int rk_vop_bind(struct udevice *dev)
7b7ad5c3 SG	374	{
	375	struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
	376
89b2b618 PT	377	plat->size = 4 * (CONFIG_VIDEO_ROCKCHIP_MAX_XRES *
89b2b618 PT	378	CONFIG_VIDEO_ROCKCHIP_MAX_YRES);
7b7ad5c3 SG	379
	380	return 0;
	381	}