[people/ms/u-boot.git] / drivers / video / rockchip / rk_vop.c

/*
 * Copyright (c) 2015 Google, Inc
 * Copyright 2014 Rockchip Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <clk.h>
#include <display.h>
#include <dm.h>
#include <edid.h>
#include <regmap.h>
#include <syscon.h>
#include <video.h>
#include <asm/gpio.h>
#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/cru_rk3288.h>
#include <asm/arch/grf_rk3288.h>
#include <asm/arch/edp_rk3288.h>
#include <asm/arch/hdmi_rk3288.h>
#include <asm/arch/vop_rk3288.h>
#include <dm/device-internal.h>
#include <dm/uclass-internal.h>
#include <dt-bindings/clock/rk3288-cru.h>
#include <power/regulator.h>

DECLARE_GLOBAL_DATA_PTR;

struct rk_vop_priv {
	struct rk3288_vop *regs;
	struct rk3288_grf *grf;
};

void rkvop_enable(struct rk3288_vop *regs, ulong fbbase,
		  int fb_bits_per_pixel, const struct display_timing *edid)
{
	u32 lb_mode;
	u32 rgb_mode;
	u32 hactive = edid->hactive.typ;
	u32 vactive = edid->vactive.typ;

	writel(V_ACT_WIDTH(hactive - 1) | V_ACT_HEIGHT(vactive - 1),
	       &regs->win0_act_info);

	writel(V_DSP_XST(edid->hsync_len.typ + edid->hback_porch.typ) |
	       V_DSP_YST(edid->vsync_len.typ + edid->vback_porch.typ),
	       &regs->win0_dsp_st);

	writel(V_DSP_WIDTH(hactive - 1) |
		V_DSP_HEIGHT(vactive - 1),
		&regs->win0_dsp_info);

	clrsetbits_le32(&regs->win0_color_key, M_WIN0_KEY_EN | M_WIN0_KEY_COLOR,
			V_WIN0_KEY_EN(0) | V_WIN0_KEY_COLOR(0));

	switch (fb_bits_per_pixel) {
	case 16:
		rgb_mode = RGB565;
		writel(V_RGB565_VIRWIDTH(hactive), &regs->win0_vir);
		break;
	case 24:
		rgb_mode = RGB888;
		writel(V_RGB888_VIRWIDTH(hactive), &regs->win0_vir);
		break;
	case 32:
	default:
		rgb_mode = ARGB8888;
		writel(V_ARGB888_VIRWIDTH(hactive), &regs->win0_vir);
		break;
	}

	if (hactive > 2560)
		lb_mode = LB_RGB_3840X2;
	else if (hactive > 1920)
		lb_mode = LB_RGB_2560X4;
	else if (hactive > 1280)
		lb_mode = LB_RGB_1920X5;
	else
		lb_mode = LB_RGB_1280X8;

	clrsetbits_le32(&regs->win0_ctrl0,
			M_WIN0_LB_MODE | M_WIN0_DATA_FMT | M_WIN0_EN,
			V_WIN0_LB_MODE(lb_mode) | V_WIN0_DATA_FMT(rgb_mode) |
			V_WIN0_EN(1));

	writel(fbbase, &regs->win0_yrgb_mst);
	writel(0x01, &regs->reg_cfg_done); /* enable reg config */
}

void rkvop_mode_set(struct rk3288_vop *regs,
		    const struct display_timing *edid, enum vop_modes mode)
{
	u32 hactive = edid->hactive.typ;
	u32 vactive = edid->vactive.typ;
	u32 hsync_len = edid->hsync_len.typ;
	u32 hback_porch = edid->hback_porch.typ;
	u32 vsync_len = edid->vsync_len.typ;
	u32 vback_porch = edid->vback_porch.typ;
	u32 hfront_porch = edid->hfront_porch.typ;
	u32 vfront_porch = edid->vfront_porch.typ;
	uint flags;
	int mode_flags;

	switch (mode) {
	case VOP_MODE_HDMI:
		clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
				V_HDMI_OUT_EN(1));
		break;
	case VOP_MODE_EDP:
	default:
		clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
				V_EDP_OUT_EN(1));
		break;
	case VOP_MODE_LVDS:
		clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
				V_RGB_OUT_EN(1));
		break;
	}

	if (mode == VOP_MODE_HDMI || mode == VOP_MODE_EDP)
		/* RGBaaa */
		mode_flags = 15;
	else
		/* RGB888 */
		mode_flags = 0;

	flags = V_DSP_OUT_MODE(mode_flags) |
		V_DSP_HSYNC_POL(!!(edid->flags & DISPLAY_FLAGS_HSYNC_HIGH)) |
		V_DSP_VSYNC_POL(!!(edid->flags & DISPLAY_FLAGS_VSYNC_HIGH));

	clrsetbits_le32(&regs->dsp_ctrl0,
			M_DSP_OUT_MODE | M_DSP_VSYNC_POL | M_DSP_HSYNC_POL,
			flags);

	writel(V_HSYNC(hsync_len) |
	       V_HORPRD(hsync_len + hback_porch + hactive + hfront_porch),
			&regs->dsp_htotal_hs_end);

	writel(V_HEAP(hsync_len + hback_porch + hactive) |
	       V_HASP(hsync_len + hback_porch),
	       &regs->dsp_hact_st_end);

	writel(V_VSYNC(vsync_len) |
	       V_VERPRD(vsync_len + vback_porch + vactive + vfront_porch),
	       &regs->dsp_vtotal_vs_end);

	writel(V_VAEP(vsync_len + vback_porch + vactive)|
	       V_VASP(vsync_len + vback_porch),
	       &regs->dsp_vact_st_end);

	writel(V_HEAP(hsync_len + hback_porch + hactive) |
	       V_HASP(hsync_len + hback_porch),
	       &regs->post_dsp_hact_info);

	writel(V_VAEP(vsync_len + vback_porch + vactive)|
	       V_VASP(vsync_len + vback_porch),
	       &regs->post_dsp_vact_info);

	writel(0x01, &regs->reg_cfg_done); /* enable reg config */
}

/**
 * rk_display_init() - Try to enable the given display device
 *
 * This function performs many steps:
 * - Finds the display device being referenced by @ep_node
 * - Puts the VOP's ID into its uclass platform data
 * - Probes the device to set it up
 * - Reads the EDID timing information
 * - Sets up the VOP clocks, etc. for the selected pixel clock and display mode
 * - Enables the display (the display device handles this and will do different
 *     things depending on the display type)
 * - Tells the uclass about the display resolution so that the console will
 *     appear correctly
 *
 * @dev:	VOP device that we want to connect to the display
 * @fbbase:	Frame buffer address
 * @l2bpp	Log2 of bits-per-pixels for the display
 * @ep_node:	Device tree node to process - this is the offset of an endpoint
 *		node within the VOP's 'port' list.
 * @return 0 if OK, -ve if something went wrong
 */
int rk_display_init(struct udevice *dev, ulong fbbase,
		    enum video_log2_bpp l2bpp, int ep_node)
{
	struct video_priv *uc_priv = dev_get_uclass_priv(dev);
	const void *blob = gd->fdt_blob;
	struct rk_vop_priv *priv = dev_get_priv(dev);
	int vop_id, remote_vop_id;
	struct rk3288_vop *regs = priv->regs;
	struct display_timing timing;
	struct udevice *disp;
	int ret, remote, i, offset;
	struct display_plat *disp_uc_plat;
	struct udevice *dev_clk;
	struct clk clk;

	vop_id = fdtdec_get_int(blob, ep_node, "reg", -1);
	debug("vop_id=%d\n", vop_id);
	remote = fdtdec_lookup_phandle(blob, ep_node, "remote-endpoint");
	if (remote < 0)
		return -EINVAL;
	remote_vop_id = fdtdec_get_int(blob, remote, "reg", -1);
	debug("remote vop_id=%d\n", remote_vop_id);

	for (i = 0, offset = remote; i < 3 && offset > 0; i++)
		offset = fdt_parent_offset(blob, offset);
	if (offset < 0) {
		debug("%s: Invalid remote-endpoint position\n", dev->name);
		return -EINVAL;
	}

	ret = uclass_find_device_by_of_offset(UCLASS_DISPLAY, offset, &disp);
	if (ret) {
		debug("%s: device '%s' display not found (ret=%d)\n", __func__,
		      dev->name, ret);
		return ret;
	}

	disp_uc_plat = dev_get_uclass_platdata(disp);
	debug("Found device '%s', disp_uc_priv=%p\n", disp->name, disp_uc_plat);
	disp_uc_plat->source_id = remote_vop_id;
	disp_uc_plat->src_dev = dev;

	ret = device_probe(disp);
	if (ret) {
		debug("%s: device '%s' display won't probe (ret=%d)\n",
		      __func__, dev->name, ret);
		return ret;
	}

	ret = display_read_timing(disp, &timing);
	if (ret) {
		debug("%s: Failed to read timings\n", __func__);
		return ret;
	}

	ret = rockchip_get_clk(&dev_clk);
	if (!ret) {
		clk.id = DCLK_VOP0 + remote_vop_id;
		ret = clk_request(dev_clk, &clk);
	}
	if (!ret)
		ret = clk_set_rate(&clk, timing.pixelclock.typ);
	if (ret) {
		debug("%s: Failed to set pixel clock: ret=%d\n", __func__, ret);
		return ret;
	}

	rkvop_mode_set(regs, &timing, vop_id);

	rkvop_enable(regs, fbbase, 1 << l2bpp, &timing);

	ret = display_enable(disp, 1 << l2bpp, &timing);
	if (ret)
		return ret;

	uc_priv->xsize = timing.hactive.typ;
	uc_priv->ysize = timing.vactive.typ;
	uc_priv->bpix = l2bpp;
	debug("fb=%lx, size=%d %d\n", fbbase, uc_priv->xsize, uc_priv->ysize);

	return 0;
}

static int rk_vop_probe(struct udevice *dev)
{
	struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
	const void *blob = gd->fdt_blob;
	struct rk_vop_priv *priv = dev_get_priv(dev);
	struct udevice *reg;
	int ret, port, node;

	/* Before relocation we don't need to do anything */
	if (!(gd->flags & GD_FLG_RELOC))
		return 0;

	priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
	priv->regs = (struct rk3288_vop *)dev_get_addr(dev);

	/* lcdc(vop) iodomain select 1.8V */
	rk_setreg(&priv->grf->io_vsel, 1 << 0);

	/*
	 * Try some common regulators. We should really get these from the
	 * device tree somehow.
	 */
	ret = regulator_autoset_by_name("vcc18_lcd", &reg);
	if (ret)
		debug("%s: Cannot autoset regulator vcc18_lcd\n", __func__);
	ret = regulator_autoset_by_name("VCC18_LCD", &reg);
	if (ret)
		debug("%s: Cannot autoset regulator VCC18_LCD\n", __func__);
	ret = regulator_autoset_by_name("vdd10_lcd_pwren_h", &reg);
	if (ret) {
		debug("%s: Cannot autoset regulator vdd10_lcd_pwren_h\n",
		      __func__);
	}
	ret = regulator_autoset_by_name("vdd10_lcd", &reg);
	if (ret) {
		debug("%s: Cannot autoset regulator vdd10_lcd\n",
		      __func__);
	}
	ret = regulator_autoset_by_name("VDD10_LCD", &reg);
	if (ret) {
		debug("%s: Cannot autoset regulator VDD10_LCD\n",
		      __func__);
	}
	ret = regulator_autoset_by_name("vcc33_lcd", &reg);
	if (ret)
		debug("%s: Cannot autoset regulator vcc33_lcd\n", __func__);

	/*
	 * Try all the ports until we find one that works. In practice this
	 * tries EDP first if available, then HDMI.
	 */
	port = fdt_subnode_offset(blob, dev->of_offset, "port");
	if (port < 0)
		return -EINVAL;
	for (node = fdt_first_subnode(blob, port);
	     node > 0;
	     node = fdt_next_subnode(blob, node)) {
		ret = rk_display_init(dev, plat->base, VIDEO_BPP16, node);
		if (ret)
			debug("Device failed: ret=%d\n", ret);
		if (!ret)
			break;
	}
	video_set_flush_dcache(dev, 1);

	return ret;
}

static int rk_vop_bind(struct udevice *dev)
{
	struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);

	plat->size = 1920 * 1080 * 2;

	return 0;
}

static const struct video_ops rk_vop_ops = {
};

static const struct udevice_id rk_vop_ids[] = {
	{ .compatible = "rockchip,rk3288-vop" },
	{ }
};

U_BOOT_DRIVER(rk_vop) = {
	.name	= "rk_vop",
	.id	= UCLASS_VIDEO,
	.of_match = rk_vop_ids,
	.ops	= &rk_vop_ops,
	.bind	= rk_vop_bind,
	.probe	= rk_vop_probe,
	.priv_auto_alloc_size	= sizeof(struct rk_vop_priv),
};
Commit	Line	Data
7b7ad5c3 SG	1	/*
	2	* Copyright (c) 2015 Google, Inc
	3	* Copyright 2014 Rockchip Inc.
	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
	7
	8	#include <common.h>
	9	#include <clk.h>
	10	#include <display.h>
	11	#include <dm.h>
	12	#include <edid.h>
	13	#include <regmap.h>
	14	#include <syscon.h>
	15	#include <video.h>
	16	#include <asm/gpio.h>
	17	#include <asm/hardware.h>
	18	#include <asm/io.h>
	19	#include <asm/arch/clock.h>
	20	#include <asm/arch/cru_rk3288.h>
	21	#include <asm/arch/grf_rk3288.h>
	22	#include <asm/arch/edp_rk3288.h>
	23	#include <asm/arch/hdmi_rk3288.h>
	24	#include <asm/arch/vop_rk3288.h>
	25	#include <dm/device-internal.h>
	26	#include <dm/uclass-internal.h>
	27	#include <dt-bindings/clock/rk3288-cru.h>
	28	#include <power/regulator.h>
	29
	30	DECLARE_GLOBAL_DATA_PTR;
	31
	32	struct rk_vop_priv {
	33	struct rk3288_vop *regs;
	34	struct rk3288_grf *grf;
	35	};
	36
	37	void rkvop_enable(struct rk3288_vop *regs, ulong fbbase,
	38	int fb_bits_per_pixel, const struct display_timing *edid)
	39	{
	40	u32 lb_mode;
	41	u32 rgb_mode;
	42	u32 hactive = edid->hactive.typ;
	43	u32 vactive = edid->vactive.typ;
	44
	45	writel(V_ACT_WIDTH(hactive - 1) \| V_ACT_HEIGHT(vactive - 1),
	46	&regs->win0_act_info);
	47
	48	writel(V_DSP_XST(edid->hsync_len.typ + edid->hback_porch.typ) \|
	49	V_DSP_YST(edid->vsync_len.typ + edid->vback_porch.typ),
	50	&regs->win0_dsp_st);
	51
	52	writel(V_DSP_WIDTH(hactive - 1) \|
	53	V_DSP_HEIGHT(vactive - 1),
	54	&regs->win0_dsp_info);
	55
	56	clrsetbits_le32(&regs->win0_color_key, M_WIN0_KEY_EN \| M_WIN0_KEY_COLOR,
	57	V_WIN0_KEY_EN(0) \| V_WIN0_KEY_COLOR(0));
	58
	59	switch (fb_bits_per_pixel) {
	60	case 16:
	61	rgb_mode = RGB565;
	62	writel(V_RGB565_VIRWIDTH(hactive), &regs->win0_vir);
	63	break;
	64	case 24:
65	rgb_mode = RGB888;
66	writel(V_RGB888_VIRWIDTH(hactive), &regs->win0_vir);
67	break;
68	case 32:
69	default:
70	rgb_mode = ARGB8888;
71	writel(V_ARGB888_VIRWIDTH(hactive), &regs->win0_vir);
72	break;
73	}
74
75	if (hactive > 2560)
76	lb_mode = LB_RGB_3840X2;
77	else if (hactive > 1920)
78	lb_mode = LB_RGB_2560X4;
79	else if (hactive > 1280)
80	lb_mode = LB_RGB_1920X5;
81	else
82	lb_mode = LB_RGB_1280X8;
83
84	clrsetbits_le32(&regs->win0_ctrl0,
85	M_WIN0_LB_MODE \| M_WIN0_DATA_FMT \| M_WIN0_EN,
86	V_WIN0_LB_MODE(lb_mode) \| V_WIN0_DATA_FMT(rgb_mode) \|
87	V_WIN0_EN(1));
88
89	writel(fbbase, &regs->win0_yrgb_mst);
90	writel(0x01, &regs->reg_cfg_done); /* enable reg config */
91	}
92
93	void rkvop_mode_set(struct rk3288_vop *regs,
94	const struct display_timing *edid, enum vop_modes mode)
95	{
96	u32 hactive = edid->hactive.typ;
97	u32 vactive = edid->vactive.typ;
98	u32 hsync_len = edid->hsync_len.typ;
99	u32 hback_porch = edid->hback_porch.typ;
100	u32 vsync_len = edid->vsync_len.typ;
101	u32 vback_porch = edid->vback_porch.typ;
102	u32 hfront_porch = edid->hfront_porch.typ;
103	u32 vfront_porch = edid->vfront_porch.typ;
104	uint flags;
85307835	105	int mode_flags;
7b7ad5c3 SG	106
	107	switch (mode) {
	108	case VOP_MODE_HDMI:
	109	clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
	110	V_HDMI_OUT_EN(1));
	111	break;
	112	case VOP_MODE_EDP:
	113	default:
	114	clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
	115	V_EDP_OUT_EN(1));
	116	break;
85307835 JC	117	case VOP_MODE_LVDS:
	118	clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
	119	V_RGB_OUT_EN(1));
	120	break;
7b7ad5c3 SG	121	}
7b7ad5c3 SG	122
85307835 JC	123	if (mode == VOP_MODE_HDMI \|\| mode == VOP_MODE_EDP)
	124	/* RGBaaa */
	125	mode_flags = 15;
	126	else
	127	/* RGB888 */
	128	mode_flags = 0;
	129
	130	flags = V_DSP_OUT_MODE(mode_flags) \|
7b7ad5c3 SG	131	V_DSP_HSYNC_POL(!!(edid->flags & DISPLAY_FLAGS_HSYNC_HIGH)) \|
	132	V_DSP_VSYNC_POL(!!(edid->flags & DISPLAY_FLAGS_VSYNC_HIGH));
	133
	134	clrsetbits_le32(&regs->dsp_ctrl0,
	135	M_DSP_OUT_MODE \| M_DSP_VSYNC_POL \| M_DSP_HSYNC_POL,
	136	flags);
	137
	138	writel(V_HSYNC(hsync_len) \|
	139	V_HORPRD(hsync_len + hback_porch + hactive + hfront_porch),
	140	&regs->dsp_htotal_hs_end);
	141
	142	writel(V_HEAP(hsync_len + hback_porch + hactive) \|
	143	V_HASP(hsync_len + hback_porch),
	144	&regs->dsp_hact_st_end);
	145
	146	writel(V_VSYNC(vsync_len) \|
	147	V_VERPRD(vsync_len + vback_porch + vactive + vfront_porch),
	148	&regs->dsp_vtotal_vs_end);
	149
	150	writel(V_VAEP(vsync_len + vback_porch + vactive)\|
	151	V_VASP(vsync_len + vback_porch),
	152	&regs->dsp_vact_st_end);
	153
	154	writel(V_HEAP(hsync_len + hback_porch + hactive) \|
	155	V_HASP(hsync_len + hback_porch),
	156	&regs->post_dsp_hact_info);
	157
	158	writel(V_VAEP(vsync_len + vback_porch + vactive)\|
	159	V_VASP(vsync_len + vback_porch),
	160	&regs->post_dsp_vact_info);
	161
	162	writel(0x01, &regs->reg_cfg_done); /* enable reg config */
	163	}
	164
	165	/**
	166	* rk_display_init() - Try to enable the given display device
	167	*
	168	* This function performs many steps:
	169	* - Finds the display device being referenced by @ep_node
	170	* - Puts the VOP's ID into its uclass platform data
	171	* - Probes the device to set it up
	172	* - Reads the EDID timing information
	173	* - Sets up the VOP clocks, etc. for the selected pixel clock and display mode
	174	* - Enables the display (the display device handles this and will do different
	175	* things depending on the display type)
	176	* - Tells the uclass about the display resolution so that the console will
	177	* appear correctly
	178	*
	179	* @dev: VOP device that we want to connect to the display
	180	* @fbbase: Frame buffer address
	181	* @l2bpp Log2 of bits-per-pixels for the display
	182	* @ep_node: Device tree node to process - this is the offset of an endpoint
	183	* node within the VOP's 'port' list.
	184	* @return 0 if OK, -ve if something went wrong
	185	*/
	186	int rk_display_init(struct udevice *dev, ulong fbbase,
	187	enum video_log2_bpp l2bpp, int ep_node)
	188	{
	189	struct video_priv *uc_priv = dev_get_uclass_priv(dev);
	190	const void *blob = gd->fdt_blob;
	191	struct rk_vop_priv *priv = dev_get_priv(dev);
	192	int vop_id, remote_vop_id;
	193	struct rk3288_vop *regs = priv->regs;
	194	struct display_timing timing;
195	struct udevice *disp;
196	int ret, remote, i, offset;
197	struct display_plat *disp_uc_plat;
135aa950 SW	198	struct udevice *dev_clk;
135aa950 SW	199	struct clk clk;
7b7ad5c3 SG	200
	201	vop_id = fdtdec_get_int(blob, ep_node, "reg", -1);
	202	debug("vop_id=%d\n", vop_id);
	203	remote = fdtdec_lookup_phandle(blob, ep_node, "remote-endpoint");
	204	if (remote < 0)
	205	return -EINVAL;
	206	remote_vop_id = fdtdec_get_int(blob, remote, "reg", -1);
	207	debug("remote vop_id=%d\n", remote_vop_id);
	208
	209	for (i = 0, offset = remote; i < 3 && offset > 0; i++)
	210	offset = fdt_parent_offset(blob, offset);
	211	if (offset < 0) {
	212	debug("%s: Invalid remote-endpoint position\n", dev->name);
	213	return -EINVAL;
	214	}
	215
	216	ret = uclass_find_device_by_of_offset(UCLASS_DISPLAY, offset, &disp);
	217	if (ret) {
	218	debug("%s: device '%s' display not found (ret=%d)\n", __func__,
	219	dev->name, ret);
	220	return ret;
	221	}
	222
	223	disp_uc_plat = dev_get_uclass_platdata(disp);
	224	debug("Found device '%s', disp_uc_priv=%p\n", disp->name, disp_uc_plat);
	225	disp_uc_plat->source_id = remote_vop_id;
	226	disp_uc_plat->src_dev = dev;
	227
	228	ret = device_probe(disp);
	229	if (ret) {
	230	debug("%s: device '%s' display won't probe (ret=%d)\n",
	231	__func__, dev->name, ret);
	232	return ret;
	233	}
	234
	235	ret = display_read_timing(disp, &timing);
	236	if (ret) {
	237	debug("%s: Failed to read timings\n", __func__);
	238	return ret;
	239	}
	240
c3aad6f6	241	ret = rockchip_get_clk(&dev_clk);
7b7ad5c3	242	if (!ret) {
135aa950 SW	243	clk.id = DCLK_VOP0 + remote_vop_id;
135aa950 SW	244	ret = clk_request(dev_clk, &clk);
7b7ad5c3	245	}
135aa950 SW	246	if (!ret)
135aa950 SW	247	ret = clk_set_rate(&clk, timing.pixelclock.typ);
7b7ad5c3 SG	248	if (ret) {
	249	debug("%s: Failed to set pixel clock: ret=%d\n", __func__, ret);
	250	return ret;
	251	}
	252
	253	rkvop_mode_set(regs, &timing, vop_id);
	254
	255	rkvop_enable(regs, fbbase, 1 << l2bpp, &timing);
	256
	257	ret = display_enable(disp, 1 << l2bpp, &timing);
	258	if (ret)
	259	return ret;
	260
	261	uc_priv->xsize = timing.hactive.typ;
	262	uc_priv->ysize = timing.vactive.typ;
	263	uc_priv->bpix = l2bpp;
	264	debug("fb=%lx, size=%d %d\n", fbbase, uc_priv->xsize, uc_priv->ysize);
	265
	266	return 0;
	267	}
	268
	269	static int rk_vop_probe(struct udevice *dev)
	270	{
	271	struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
	272	const void *blob = gd->fdt_blob;
	273	struct rk_vop_priv *priv = dev_get_priv(dev);
	274	struct udevice *reg;
	275	int ret, port, node;
	276
	277	/* Before relocation we don't need to do anything */
	278	if (!(gd->flags & GD_FLG_RELOC))
	279	return 0;
	280
	281	priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
	282	priv->regs = (struct rk3288_vop *)dev_get_addr(dev);
	283
	284	/* lcdc(vop) iodomain select 1.8V */
	285	rk_setreg(&priv->grf->io_vsel, 1 << 0);
	286
	287	/*
	288	* Try some common regulators. We should really get these from the
	289	* device tree somehow.
	290	*/
	291	ret = regulator_autoset_by_name("vcc18_lcd", &reg);
	292	if (ret)
	293	debug("%s: Cannot autoset regulator vcc18_lcd\n", __func__);
	294	ret = regulator_autoset_by_name("VCC18_LCD", &reg);
	295	if (ret)
	296	debug("%s: Cannot autoset regulator VCC18_LCD\n", __func__);
	297	ret = regulator_autoset_by_name("vdd10_lcd_pwren_h", &reg);
	298	if (ret) {
	299	debug("%s: Cannot autoset regulator vdd10_lcd_pwren_h\n",
	300	__func__);
	301	}
	302	ret = regulator_autoset_by_name("vdd10_lcd", &reg);
	303	if (ret) {
	304	debug("%s: Cannot autoset regulator vdd10_lcd\n",
	305	__func__);
	306	}
	307	ret = regulator_autoset_by_name("VDD10_LCD", &reg);
	308	if (ret) {
	309	debug("%s: Cannot autoset regulator VDD10_LCD\n",
	310	__func__);
	311	}
312	ret = regulator_autoset_by_name("vcc33_lcd", &reg);
313	if (ret)
314	debug("%s: Cannot autoset regulator vcc33_lcd\n", __func__);
315
316	/*
317	* Try all the ports until we find one that works. In practice this
318	* tries EDP first if available, then HDMI.
319	*/
320	port = fdt_subnode_offset(blob, dev->of_offset, "port");
321	if (port < 0)
322	return -EINVAL;
323	for (node = fdt_first_subnode(blob, port);
324	node > 0;
325	node = fdt_next_subnode(blob, node)) {
326	ret = rk_display_init(dev, plat->base, VIDEO_BPP16, node);
327	if (ret)
328	debug("Device failed: ret=%d\n", ret);
329	if (!ret)
330	break;
331	}
b55e04a0	332	video_set_flush_dcache(dev, 1);
7b7ad5c3 SG	333
	334	return ret;
	335	}
	336
	337	static int rk_vop_bind(struct udevice *dev)
	338	{
	339	struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
	340
	341	plat->size = 1920 * 1080 * 2;
	342
	343	return 0;
	344	}
	345
	346	static const struct video_ops rk_vop_ops = {
	347	};
	348
	349	static const struct udevice_id rk_vop_ids[] = {
	350	{ .compatible = "rockchip,rk3288-vop" },
	351	{ }
	352	};
	353
	354	U_BOOT_DRIVER(rk_vop) = {
	355	.name = "rk_vop",
	356	.id = UCLASS_VIDEO,
	357	.of_match = rk_vop_ids,
	358	.ops = &rk_vop_ops,
	359	.bind = rk_vop_bind,
	360	.probe = rk_vop_probe,
	361	.priv_auto_alloc_size = sizeof(struct rk_vop_priv),
	362	};