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935ecca1 WD |
1 | |
2 | ||
3 | ||
4 | #ifndef _440_i2c_h_ | |
5 | #define _440_i2c_h_ | |
6 | ||
7 | #define I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000400) | |
8 | ||
9 | #define I2C_REGISTERS_BASE_ADDRESS I2C_BASE_ADDR | |
10 | #define IIC_MDBUF (I2C_REGISTERS_BASE_ADDRESS+IICMDBUF) | |
11 | #define IIC_SDBUF (I2C_REGISTERS_BASE_ADDRESS+IICSDBUF) | |
12 | #define IIC_LMADR (I2C_REGISTERS_BASE_ADDRESS+IICLMADR) | |
13 | #define IIC_HMADR (I2C_REGISTERS_BASE_ADDRESS+IICHMADR) | |
14 | #define IIC_CNTL (I2C_REGISTERS_BASE_ADDRESS+IICCNTL) | |
15 | #define IIC_MDCNTL (I2C_REGISTERS_BASE_ADDRESS+IICMDCNTL) | |
16 | #define IIC_STS (I2C_REGISTERS_BASE_ADDRESS+IICSTS) | |
17 | #define IIC_EXTSTS (I2C_REGISTERS_BASE_ADDRESS+IICEXTSTS) | |
18 | #define IIC_LSADR (I2C_REGISTERS_BASE_ADDRESS+IICLSADR) | |
19 | #define IIC_HSADR (I2C_REGISTERS_BASE_ADDRESS+IICHSADR) | |
20 | #define IIC_CLKDIV (I2C_REGISTERS_BASE_ADDRESS+IICCLKDIV) | |
21 | #define IIC_INTRMSK (I2C_REGISTERS_BASE_ADDRESS+IICINTRMSK) | |
22 | #define IIC_XFRCNT (I2C_REGISTERS_BASE_ADDRESS+IICXFRCNT) | |
23 | #define IIC_XTCNTLSS (I2C_REGISTERS_BASE_ADDRESS+IICXTCNTLSS) | |
24 | #define IIC_DIRECTCNTL (I2C_REGISTERS_BASE_ADDRESS+IICDIRECTCNTL) | |
25 | ||
26 | /* MDCNTL Register Bit definition */ | |
27 | #define IIC_MDCNTL_HSCL 0x01 | |
28 | #define IIC_MDCNTL_EUBS 0x02 | |
29 | #define IIC_MDCNTL_EINT 0x04 | |
30 | #define IIC_MDCNTL_ESM 0x08 | |
31 | #define IIC_MDCNTL_FSM 0x10 | |
32 | #define IIC_MDCNTL_EGC 0x20 | |
33 | #define IIC_MDCNTL_FMDB 0x40 | |
34 | #define IIC_MDCNTL_FSDB 0x80 | |
35 | ||
36 | /* CNTL Register Bit definition */ | |
37 | #define IIC_CNTL_PT 0x01 | |
38 | #define IIC_CNTL_READ 0x02 | |
39 | #define IIC_CNTL_CHT 0x04 | |
40 | #define IIC_CNTL_RPST 0x08 | |
41 | /* bit 2/3 for Transfer count*/ | |
42 | #define IIC_CNTL_AMD 0x40 | |
43 | #define IIC_CNTL_HMT 0x80 | |
44 | ||
45 | /* STS Register Bit definition */ | |
46 | #define IIC_STS_PT 0X01 | |
47 | #define IIC_STS_IRQA 0x02 | |
48 | #define IIC_STS_ERR 0X04 | |
49 | #define IIC_STS_SCMP 0x08 | |
50 | #define IIC_STS_MDBF 0x10 | |
51 | #define IIC_STS_MDBS 0X20 | |
52 | #define IIC_STS_SLPR 0x40 | |
53 | #define IIC_STS_SSS 0x80 | |
54 | ||
55 | /* EXTSTS Register Bit definition */ | |
56 | #define IIC_EXTSTS_XFRA 0X01 | |
57 | #define IIC_EXTSTS_ICT 0X02 | |
58 | #define IIC_EXTSTS_LA 0X04 | |
59 | ||
60 | /* XTCNTLSS Register Bit definition */ | |
61 | #define IIC_XTCNTLSS_SRST 0x01 | |
62 | #define IIC_XTCNTLSS_EPI 0x02 | |
63 | #define IIC_XTCNTLSS_SDBF 0x04 | |
64 | #define IIC_XTCNTLSS_SBDD 0x08 | |
65 | #define IIC_XTCNTLSS_SWS 0x10 | |
66 | #define IIC_XTCNTLSS_SWC 0x20 | |
67 | #define IIC_XTCNTLSS_SRS 0x40 | |
68 | #define IIC_XTCNTLSS_SRC 0x80 | |
69 | #endif |