[people/ms/u-boot.git] / include / asm-arm / arch-omap24xx / clocks.h

/*
 * (C) Copyright 2004
 * Texas Instruments, <www.ti.com>
 * Richard Woodruff <r-woodruff2@ti.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
  */
#ifndef _OMAP24XX_CLOCKS_H_
#define _OMAP24XX_CLOCKS_H_

#define COMMIT_DIVIDERS  0x1

#define MODE_BYPASS_FAST 0x2
#define APLL_LOCK        0xc
#ifdef CONFIG_APTIX
#define DPLL_LOCK        0x1   /* stay in bypass mode */
#else
#define DPLL_LOCK        0x3   /* DPLL lock */
#endif

/****************************************************************************;
; PRCM Scheme II
;
; Enable clocks and DPLL for:
;  DPLL=300,	DPLLout=600	M=1,N=50   CM_CLKSEL1_PLL[21:8]  12/2*50
;  Core=600	(core domain)   DPLLx2     CM_CLKSEL2_PLL[1:0]
;  MPUF=300	(mpu domain)    2          CM_CLKSEL_MPU[4:0]
;  DSPF=200    (dsp domain)    3          CM_CLKSEL_DSP[4:0]
;  DSPI=100                    6          CM_CLKSEL_DSP[6:5]
;  DSP_S          bypass	               CM_CLKSEL_DSP[7]
;  IVAF=200    (dsp domain)    3          CM_CLKSEL_DSP[12:8]
;  IVAF=100        auto
;  IVAI            auto
;  IVA_MPU         auto
;  IVA_S          bypass                  CM_CLKSEL_DSP[13]
;  GFXF=50      (gfx domain)	12         CM_CLKSEL_FGX[2:0]
;  SSI_SSRF=200                 3         CM_CLKSEL1_CORE[24:20]
;  SSI_SSTF=100     auto
;  L3=100Mhz (sdram)            6         CM_CLKSEL1_CORE[4:0]
;  L4=100Mhz                    6
;  C_L4_USB=50                 12         CM_CLKSEL1_CORE[6:5]
***************************************************************************/
#define II_DPLL_OUT_X2   0x2    /* x2 core out */
#define II_MPU_DIV       0x2    /* mpu = core/2 */
#define II_DSP_DIV       0x343  /* dsp & iva divider */
#define II_GFX_DIV       0x2
#define II_BUS_DIV       0x04601026
#define II_DPLL_300      0x01832100

/****************************************************************************;
; PRCM Scheme III
;
; Enable clocks and DPLL for:
;  DPLL=266,	DPLLout=532	M=5+1,N=133 CM_CLKSEL1_PLL[21:8]  12/6*133=266
;  Core=532	(core domain)   DPLLx2      CM_CLKSEL2_PLL[1:0]
;  MPUF=266	(mpu domain)    /2          CM_CLKSEL_MPU[4:0]
;  DSPF=177.3     (dsp domain)  /3          CM_CLKSEL_DSP[4:0]
;  DSPI=88.67                   /6          CM_CLKSEL_DSP[6:5]
;  DSP_S         ACTIVATED	            CM_CLKSEL_DSP[7]
;  IVAF=88.67    (dsp domain)   /3          CM_CLKSEL_DSP[12:8]
;  IVAF=88.67        auto
;  IVAI            auto
;  IVA_MPU         auto
;  IVA_S         ACTIVATED                  CM_CLKSEL_DSP[13]
;  GFXF=66.5      (gfx domain)	/8          CM_CLKSEL_FGX[2:0]:
;  SSI_SSRF=177.3               /3          CM_CLKSEL1_CORE[24:20]
;  SSI_SSTF=88.67     auto
;  L3=133Mhz (sdram)            /4          CM_CLKSEL1_CORE[4:0]
;  L4=66.5Mhz                   /8
;  C_L4_USB=33.25               /16         CM_CLKSEL1_CORE[6:5]
***************************************************************************/
#define III_DPLL_OUT_X2   0x2    /* x2 core out */
#define III_MPU_DIV       0x2    /* mpu = core/2 */
#define III_DSP_DIV       0x23C3 /* dsp & iva divider sych enabled*/
#define III_GFX_DIV       0x2
#define III_BUS_DIV       0x08301044
#define III_DPLL_266      0x01885500

/* set defaults for boot up */
#ifdef PRCM_CONFIG_II
# define DPLL_OUT         II_DPLL_OUT_X2
# define MPU_DIV          II_MPU_DIV
# define DSP_DIV          II_DSP_DIV
# define GFX_DIV          II_GFX_DIV
# define BUS_DIV          II_BUS_DIV
# define DPLL_VAL         II_DPLL_300
#elif PRCM_CONFIG_III
# define DPLL_OUT         III_DPLL_OUT_X2
# define MPU_DIV          III_MPU_DIV
# define DSP_DIV          III_DSP_DIV
# define GFX_DIV          III_GFX_DIV
# define BUS_DIV          III_BUS_DIV
# define DPLL_VAL         III_DPLL_266
#endif

/* lock delay time out */
#define LDELAY           12000000

#endif
Commit	Line	Data
8ed96046 WD	1	/*
	2	* (C) Copyright 2004
	3	* Texas Instruments, <www.ti.com>
	4	* Richard Woodruff <r-woodruff2@ti.com>
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License as
	8	* published by the Free Software Foundation; either version 2 of
	9	* the License, or (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	19	* MA 02111-1307 USA
	20	*/
	21	#ifndef _OMAP24XX_CLOCKS_H_
	22	#define _OMAP24XX_CLOCKS_H_
	23
	24	#define COMMIT_DIVIDERS 0x1
	25
	26	#define MODE_BYPASS_FAST 0x2
	27	#define APLL_LOCK 0xc
	28	#ifdef CONFIG_APTIX
	29	#define DPLL_LOCK 0x1 /* stay in bypass mode */
	30	#else
	31	#define DPLL_LOCK 0x3 /* DPLL lock */
	32	#endif
	33
	34	/****************************************************************************;
	35	; PRCM Scheme II
	36	;
	37	; Enable clocks and DPLL for:
53677ef1 WD	38	; DPLL=300, DPLLout=600 M=1,N=50 CM_CLKSEL1_PLL[21:8] 12/2*50
	39	; Core=600 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0]
	40	; MPUF=300 (mpu domain) 2 CM_CLKSEL_MPU[4:0]
8ed96046 WD	41	; DSPF=200 (dsp domain) 3 CM_CLKSEL_DSP[4:0]
	42	; DSPI=100 6 CM_CLKSEL_DSP[6:5]
	43	; DSP_S bypass CM_CLKSEL_DSP[7]
	44	; IVAF=200 (dsp domain) 3 CM_CLKSEL_DSP[12:8]
	45	; IVAF=100 auto
	46	; IVAI auto
	47	; IVA_MPU auto
	48	; IVA_S bypass CM_CLKSEL_DSP[13]
	49	; GFXF=50 (gfx domain) 12 CM_CLKSEL_FGX[2:0]
	50	; SSI_SSRF=200 3 CM_CLKSEL1_CORE[24:20]
	51	; SSI_SSTF=100 auto
	52	; L3=100Mhz (sdram) 6 CM_CLKSEL1_CORE[4:0]
	53	; L4=100Mhz 6
	54	; C_L4_USB=50 12 CM_CLKSEL1_CORE[6:5]
	55	***************************************************************************/
	56	#define II_DPLL_OUT_X2 0x2 /* x2 core out */
	57	#define II_MPU_DIV 0x2 /* mpu = core/2 */
	58	#define II_DSP_DIV 0x343 /* dsp & iva divider */
	59	#define II_GFX_DIV 0x2
49a7581c	60	#define II_BUS_DIV 0x04601026
8ed96046 WD	61	#define II_DPLL_300 0x01832100
8ed96046 WD	62
289f932c WD	63	/****************************************************************************;
	64	; PRCM Scheme III
	65	;
	66	; Enable clocks and DPLL for:
53677ef1 WD	67	; DPLL=266, DPLLout=532 M=5+1,N=133 CM_CLKSEL1_PLL[21:8] 12/6*133=266
	68	; Core=532 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0]
	69	; MPUF=266 (mpu domain) /2 CM_CLKSEL_MPU[4:0]
289f932c WD	70	; DSPF=177.3 (dsp domain) /3 CM_CLKSEL_DSP[4:0]
	71	; DSPI=88.67 /6 CM_CLKSEL_DSP[6:5]
	72	; DSP_S ACTIVATED CM_CLKSEL_DSP[7]
	73	; IVAF=88.67 (dsp domain) /3 CM_CLKSEL_DSP[12:8]
	74	; IVAF=88.67 auto
	75	; IVAI auto
	76	; IVA_MPU auto
	77	; IVA_S ACTIVATED CM_CLKSEL_DSP[13]
	78	; GFXF=66.5 (gfx domain) /8 CM_CLKSEL_FGX[2:0]:
	79	; SSI_SSRF=177.3 /3 CM_CLKSEL1_CORE[24:20]
	80	; SSI_SSTF=88.67 auto
	81	; L3=133Mhz (sdram) /4 CM_CLKSEL1_CORE[4:0]
	82	; L4=66.5Mhz /8
	83	; C_L4_USB=33.25 /16 CM_CLKSEL1_CORE[6:5]
	84	***************************************************************************/
	85	#define III_DPLL_OUT_X2 0x2 /* x2 core out */
	86	#define III_MPU_DIV 0x2 /* mpu = core/2 */
	87	#define III_DSP_DIV 0x23C3 /* dsp & iva divider sych enabled*/
	88	#define III_GFX_DIV 0x2
49a7581c	89	#define III_BUS_DIV 0x08301044
289f932c WD	90	#define III_DPLL_266 0x01885500
289f932c WD	91
8ed96046 WD	92	/* set defaults for boot up */
8ed96046 WD	93	#ifdef PRCM_CONFIG_II
289f932c WD	94	# define DPLL_OUT II_DPLL_OUT_X2
	95	# define MPU_DIV II_MPU_DIV
	96	# define DSP_DIV II_DSP_DIV
	97	# define GFX_DIV II_GFX_DIV
	98	# define BUS_DIV II_BUS_DIV
289f932c WD	99	# define DPLL_VAL II_DPLL_300
	100	#elif PRCM_CONFIG_III
	101	# define DPLL_OUT III_DPLL_OUT_X2
	102	# define MPU_DIV III_MPU_DIV
	103	# define DSP_DIV III_DSP_DIV
	104	# define GFX_DIV III_GFX_DIV
	105	# define BUS_DIV III_BUS_DIV
289f932c	106	# define DPLL_VAL III_DPLL_266
8ed96046 WD	107	#endif
	108
	109	/* lock delay time out */
	110	#define LDELAY 12000000
	111
	112	#endif