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Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx
[people/ms/u-boot.git] / include / asm-ppc / immap_85xx.h
CommitLineData
42d1f039
WD		 1/*
2 * MPC85xx Internal Memory Map
3 *
837f1ba0
ES		 4 * Copyright 2007 Freescale Semiconductor.
5 *
42d1f039
WD		 6 * Copyright(c) 2002,2003 Motorola Inc.
7 * Xianghua Xiao (x.xiao@motorola.com)
8 *
9 */
10
11#ifndef __IMMAP_85xx__
12#define __IMMAP_85xx__
13
3dfa9cfd
JL		 14#include <asm/types.h>
15#include <asm/fsl_i2c.h>
4e190b03 16#include <asm/fsl_lbc.h>
3dfa9cfd 17
de1d0a69
JL		 18/*
19 * Local-Access Registers and ECM Registers(0x0000-0x2000)
20 */
42d1f039
WD		 21typedef struct ccsr_local_ecm {
22 uint ccsrbar; /* 0x0 - Control Configuration Status Registers Base Address Register */
23 char res1[4];
24 uint altcbar; /* 0x8 - Alternate Configuration Base Address Register */
25 char res2[4];
26 uint altcar; /* 0x10 - Alternate Configuration Attribute Register */
27 char res3[12];
28 uint bptr; /* 0x20 - Boot Page Translation Register */
29 char res4[3044];
30 uint lawbar0; /* 0xc08 - Local Access Window 0 Base Address Register */
31 char res5[4];
32 uint lawar0; /* 0xc10 - Local Access Window 0 Attributes Register */
33 char res6[20];
34 uint lawbar1; /* 0xc28 - Local Access Window 1 Base Address Register */
35 char res7[4];
36 uint lawar1; /* 0xc30 - Local Access Window 1 Attributes Register */
37 char res8[20];
38 uint lawbar2; /* 0xc48 - Local Access Window 2 Base Address Register */
39 char res9[4];
40 uint lawar2; /* 0xc50 - Local Access Window 2 Attributes Register */
41 char res10[20];
42 uint lawbar3; /* 0xc68 - Local Access Window 3 Base Address Register */
43 char res11[4];
44 uint lawar3; /* 0xc70 - Local Access Window 3 Attributes Register */
45 char res12[20];
46 uint lawbar4; /* 0xc88 - Local Access Window 4 Base Address Register */
47 char res13[4];
48 uint lawar4; /* 0xc90 - Local Access Window 4 Attributes Register */
49 char res14[20];
50 uint lawbar5; /* 0xca8 - Local Access Window 5 Base Address Register */
51 char res15[4];
52 uint lawar5; /* 0xcb0 - Local Access Window 5 Attributes Register */
53 char res16[20];
54 uint lawbar6; /* 0xcc8 - Local Access Window 6 Base Address Register */
55 char res17[4];
56 uint lawar6; /* 0xcd0 - Local Access Window 6 Attributes Register */
57 char res18[20];
58 uint lawbar7; /* 0xce8 - Local Access Window 7 Base Address Register */
59 char res19[4];
60 uint lawar7; /* 0xcf0 - Local Access Window 7 Attributes Register */
1aeed8d7 61 char res20[780]; /* XXX: LAW 8, LAW9 for 8572 */
42d1f039
WD		 62 uint eebacr; /* 0x1000 - ECM CCB Address Configuration Register */
63 char res21[12];
64 uint eebpcr; /* 0x1010 - ECM CCB Port Configuration Register */
65 char res22[3564];
66 uint eedr; /* 0x1e00 - ECM Error Detect Register */
67 char res23[4];
68 uint eeer; /* 0x1e08 - ECM Error Enable Register */
69 uint eeatr; /* 0x1e0c - ECM Error Attributes Capture Register */
70 uint eeadr; /* 0x1e10 - ECM Error Address Capture Register */
71 char res24[492];
72} ccsr_local_ecm_t;
73
de1d0a69
JL		 74/*
75 * DDR memory controller registers(0x2000-0x3000)
76 */
42d1f039
WD		 77typedef struct ccsr_ddr {
78 uint cs0_bnds; /* 0x2000 - DDR Chip Select 0 Memory Bounds */
79 char res1[4];
80 uint cs1_bnds; /* 0x2008 - DDR Chip Select 1 Memory Bounds */
81 char res2[4];
82 uint cs2_bnds; /* 0x2010 - DDR Chip Select 2 Memory Bounds */
83 char res3[4];
84 uint cs3_bnds; /* 0x2018 - DDR Chip Select 3 Memory Bounds */
85 char res4[100];
86 uint cs0_config; /* 0x2080 - DDR Chip Select Configuration */
87 uint cs1_config; /* 0x2084 - DDR Chip Select Configuration */
88 uint cs2_config; /* 0x2088 - DDR Chip Select Configuration */
89 uint cs3_config; /* 0x208c - DDR Chip Select Configuration */
5893b3d0
JY		 90 char res4a[48];
91 uint cs0_config_2; /* 0x20c0 - DDR Chip Select Configuration 2 */
92 uint cs1_config_2; /* 0x20c4 - DDR Chip Select Configuration 2 */
93 uint cs2_config_2; /* 0x20c8 - DDR Chip Select Configuration 2 */
94 uint cs3_config_2; /* 0x20cc - DDR Chip Select Configuration 2 */
95 char res5[48];
45239cf4 96 uint timing_cfg_3; /* 0x2100 - DDR SDRAM Timing Configuration Register 3 */
d9b94f28 97 uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */
42d1f039
WD		 98 uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */
99 uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */
100 uint sdram_cfg; /* 0x2110 - DDR SDRAM Control Configuration */
d9b94f28 101 uint sdram_cfg_2; /* 0x2114 - DDR SDRAM Control Configuration 2 */
42d1f039 102 uint sdram_mode; /* 0x2118 - DDR SDRAM Mode Configuration */
d9b94f28
JL		 103 uint sdram_mode_2; /* 0x211c - DDR SDRAM Mode Configuration 2*/
104 uint sdram_md_cntl; /* 0x2120 - DDR SDRAM Mode Control */
42d1f039 105 uint sdram_interval; /* 0x2124 - DDR SDRAM Interval Configuration */
d9b94f28
JL		 106 uint sdram_data_init; /* 0x2128 - DDR SDRAM Data initialization */
107 char res6[4];
547b4cb2 108 uint sdram_clk_cntl; /* 0x2130 - DDR SDRAM Clock Control */
d9b94f28 109 char res7[20];
ef7d30b1
KG		 110 uint init_addr; /* 0x2148 - DDR training initialization address */
111 uint init_ext_addr; /* 0x214C - DDR training initialization extended address */
5893b3d0
JY		 112 char res8_1[16];
113 uint timing_cfg_4; /* 0x2160 - DDR SDRAM Timing Configuration Register 4 */
114 uint timing_cfg_5; /* 0x2164 - DDR SDRAM Timing Configuration Register 5 */
115 char reg8_1a[8];
116 uint ddr_zq_cntl; /* 0x2170 - DDR ZQ calibration control*/
117 uint ddr_wrlvl_cntl; /* 0x2174 - DDR write leveling control*/
118 uint ddr_pd_cntl; /* 0x2178 - DDR pre-drive conditioning control*/
119 uint ddr_sr_cntr; /* 0x217C - DDR self refresh counter */
120 uint ddr_sdram_rcw_1; /* 0x2180 - DDR Register Control Words 1 */
121 uint ddr_sdram_rcw_2; /* 0x2184 - DDR Register Control Words 2 */
122 char res8_1b[2672];
d9b94f28
JL		 123 uint ip_rev1; /* 0x2BF8 - DDR IP Block Revision 1 */
124 uint ip_rev2; /* 0x2BFC - DDR IP Block Revision 2 */
125 char res8_2[512];
42d1f039
WD		 126 uint data_err_inject_hi; /* 0x2e00 - DDR Memory Data Path Error Injection Mask High */
127 uint data_err_inject_lo; /* 0x2e04 - DDR Memory Data Path Error Injection Mask Low */
128 uint ecc_err_inject; /* 0x2e08 - DDR Memory Data Path Error Injection Mask ECC */
129 char res9[20];
130 uint capture_data_hi; /* 0x2e20 - DDR Memory Data Path Read Capture High */
131 uint capture_data_lo; /* 0x2e24 - DDR Memory Data Path Read Capture Low */
132 uint capture_ecc; /* 0x2e28 - DDR Memory Data Path Read Capture ECC */
133 char res10[20];
134 uint err_detect; /* 0x2e40 - DDR Memory Error Detect */
135 uint err_disable; /* 0x2e44 - DDR Memory Error Disable */
136 uint err_int_en; /* 0x2e48 - DDR */
137 uint capture_attributes; /* 0x2e4c - DDR Memory Error Attributes Capture */
138 uint capture_address; /* 0x2e50 - DDR Memory Error Address Capture */
139 uint capture_ext_address; /* 0x2e54 - DDR Memory Error Extended Address Capture */
140 uint err_sbe; /* 0x2e58 - DDR Memory Single-Bit ECC Error Management */
141 char res11[164];
142 uint debug_1; /* 0x2f00 */
143 uint debug_2;
144 uint debug_3;
145 uint debug_4;
146 char res12[240];
147} ccsr_ddr_t;
148
de1d0a69
JL		 149/*
150 * I2C Registers(0x3000-0x4000)
151 */
42d1f039 152typedef struct ccsr_i2c {
3dfa9cfd
JL		 153 struct fsl_i2c i2c[1];
154 u8 res[4096 - 1 * sizeof(struct fsl_i2c)];
42d1f039
WD		 155} ccsr_i2c_t;
156
03f5c550
WD		 157#if defined(CONFIG_MPC8540) \
158 || defined(CONFIG_MPC8541) \
d9b94f28 159 || defined(CONFIG_MPC8548) \
03f5c550 160 || defined(CONFIG_MPC8555)
42d1f039
WD		 161/* DUART Registers(0x4000-0x5000) */
162typedef struct ccsr_duart {
163 char res1[1280];
164 u_char urbr1_uthr1_udlb1;/* 0x4500 - URBR1, UTHR1, UDLB1 with the same address offset of 0x04500 */
165 u_char uier1_udmb1; /* 0x4501 - UIER1, UDMB1 with the same address offset of 0x04501 */
166 u_char uiir1_ufcr1_uafr1;/* 0x4502 - UIIR1, UFCR1, UAFR1 with the same address offset of 0x04502 */
167 u_char ulcr1; /* 0x4503 - UART1 Line Control Register */
168 u_char umcr1; /* 0x4504 - UART1 Modem Control Register */
169 u_char ulsr1; /* 0x4505 - UART1 Line Status Register */
170 u_char umsr1; /* 0x4506 - UART1 Modem Status Register */
171 u_char uscr1; /* 0x4507 - UART1 Scratch Register */
172 char res2[8];
173 u_char udsr1; /* 0x4510 - UART1 DMA Status Register */
174 char res3[239];
175 u_char urbr2_uthr2_udlb2;/* 0x4600 - URBR2, UTHR2, UDLB2 with the same address offset of 0x04600 */
176 u_char uier2_udmb2; /* 0x4601 - UIER2, UDMB2 with the same address offset of 0x04601 */
177 u_char uiir2_ufcr2_uafr2;/* 0x4602 - UIIR2, UFCR2, UAFR2 with the same address offset of 0x04602 */
178 u_char ulcr2; /* 0x4603 - UART2 Line Control Register */
179 u_char umcr2; /* 0x4604 - UART2 Modem Control Register */
180 u_char ulsr2; /* 0x4605 - UART2 Line Status Register */
181 u_char umsr2; /* 0x4606 - UART2 Modem Status Register */
182 u_char uscr2; /* 0x4607 - UART2 Scratch Register */
183 char res4[8];
184 u_char udsr2; /* 0x4610 - UART2 DMA Status Register */
185 char res5[2543];
186} ccsr_duart_t;
187#else /* MPC8560 uses UART on its CPM */
188typedef struct ccsr_duart {
189 char res[4096];
190} ccsr_duart_t;
191#endif
192
193/* Local Bus Controller Registers(0x5000-0x6000) */
194/* Omitting OCeaN(0x6000) and Reserved(0x7000) block */
195
196typedef struct ccsr_lbc {
197 uint br0; /* 0x5000 - LBC Base Register 0 */
198 uint or0; /* 0x5004 - LBC Options Register 0 */
199 uint br1; /* 0x5008 - LBC Base Register 1 */
200 uint or1; /* 0x500c - LBC Options Register 1 */
201 uint br2; /* 0x5010 - LBC Base Register 2 */
202 uint or2; /* 0x5014 - LBC Options Register 2 */
203 uint br3; /* 0x5018 - LBC Base Register 3 */
204 uint or3; /* 0x501c - LBC Options Register 3 */
205 uint br4; /* 0x5020 - LBC Base Register 4 */
206 uint or4; /* 0x5024 - LBC Options Register 4 */
207 uint br5; /* 0x5028 - LBC Base Register 5 */
208 uint or5; /* 0x502c - LBC Options Register 5 */
209 uint br6; /* 0x5030 - LBC Base Register 6 */
210 uint or6; /* 0x5034 - LBC Options Register 6 */
211 uint br7; /* 0x5038 - LBC Base Register 7 */
212 uint or7; /* 0x503c - LBC Options Register 7 */
213 char res1[40];
214 uint mar; /* 0x5068 - LBC UPM Address Register */
215 char res2[4];
216 uint mamr; /* 0x5070 - LBC UPMA Mode Register */
217 uint mbmr; /* 0x5074 - LBC UPMB Mode Register */
218 uint mcmr; /* 0x5078 - LBC UPMC Mode Register */
219 char res3[8];
220 uint mrtpr; /* 0x5084 - LBC Memory Refresh Timer Prescaler Register */
221 uint mdr; /* 0x5088 - LBC UPM Data Register */
222 char res4[8];
223 uint lsdmr; /* 0x5094 - LBC SDRAM Mode Register */
224 char res5[8];
225 uint lurt; /* 0x50a0 - LBC UPM Refresh Timer */
226 uint lsrt; /* 0x50a4 - LBC SDRAM Refresh Timer */
227 char res6[8];
228 uint ltesr; /* 0x50b0 - LBC Transfer Error Status Register */
229 uint ltedr; /* 0x50b4 - LBC Transfer Error Disable Register */
230 uint lteir; /* 0x50b8 - LBC Transfer Error Interrupt Register */
231 uint lteatr; /* 0x50bc - LBC Transfer Error Attributes Register */
232 uint ltear; /* 0x50c0 - LBC Transfer Error Address Register */
233 char res7[12];
234 uint lbcr; /* 0x50d0 - LBC Configuration Register */
235 uint lcrr; /* 0x50d4 - LBC Clock Ratio Register */
5893b3d0 236 char res8[3880];
42d1f039
WD		 237} ccsr_lbc_t;
238
de1d0a69
JL		 239/*
240 * PCI Registers(0x8000-0x9000)
de1d0a69 241 */
42d1f039
WD		 242typedef struct ccsr_pcix {
243 uint cfg_addr; /* 0x8000 - PCIX Configuration Address Register */
244 uint cfg_data; /* 0x8004 - PCIX Configuration Data Register */
245 uint int_ack; /* 0x8008 - PCIX Interrupt Acknowledge Register */
246 char res1[3060];
247 uint potar0; /* 0x8c00 - PCIX Outbound Transaction Address Register 0 */
248 uint potear0; /* 0x8c04 - PCIX Outbound Translation Extended Address Register 0 */
249 uint powbar0; /* 0x8c08 - PCIX Outbound Window Base Address Register 0 */
250 uint powbear0; /* 0x8c0c - PCIX Outbound Window Base Extended Address Register 0 */
251 uint powar0; /* 0x8c10 - PCIX Outbound Window Attributes Register 0 */
252 char res2[12];
253 uint potar1; /* 0x8c20 - PCIX Outbound Transaction Address Register 1 */
254 uint potear1; /* 0x8c24 - PCIX Outbound Translation Extended Address Register 1 */
255 uint powbar1; /* 0x8c28 - PCIX Outbound Window Base Address Register 1 */
256 uint powbear1; /* 0x8c2c - PCIX Outbound Window Base Extended Address Register 1 */
257 uint powar1; /* 0x8c30 - PCIX Outbound Window Attributes Register 1 */
258 char res3[12];
259 uint potar2; /* 0x8c40 - PCIX Outbound Transaction Address Register 2 */
260 uint potear2; /* 0x8c44 - PCIX Outbound Translation Extended Address Register 2 */
261 uint powbar2; /* 0x8c48 - PCIX Outbound Window Base Address Register 2 */
262 uint powbear2; /* 0x8c4c - PCIX Outbound Window Base Extended Address Register 2 */
263 uint powar2; /* 0x8c50 - PCIX Outbound Window Attributes Register 2 */
264 char res4[12];
265 uint potar3; /* 0x8c60 - PCIX Outbound Transaction Address Register 3 */
266 uint potear3; /* 0x8c64 - PCIX Outbound Translation Extended Address Register 3 */
267 uint powbar3; /* 0x8c68 - PCIX Outbound Window Base Address Register 3 */
268 uint powbear3; /* 0x8c6c - PCIX Outbound Window Base Extended Address Register 3 */
269 uint powar3; /* 0x8c70 - PCIX Outbound Window Attributes Register 3 */
270 char res5[12];
271 uint potar4; /* 0x8c80 - PCIX Outbound Transaction Address Register 4 */
272 uint potear4; /* 0x8c84 - PCIX Outbound Translation Extended Address Register 4 */
273 uint powbar4; /* 0x8c88 - PCIX Outbound Window Base Address Register 4 */
274 uint powbear4; /* 0x8c8c - PCIX Outbound Window Base Extended Address Register 4 */
275 uint powar4; /* 0x8c90 - PCIX Outbound Window Attributes Register 4 */
276 char res6[268];
277 uint pitar3; /* 0x8da0 - PCIX Inbound Translation Address Register 3 */
278 uint pitear3; /* 0x8da4 - PCIX Inbound Translation Extended Address Register 3 */
279 uint piwbar3; /* 0x8da8 - PCIX Inbound Window Base Address Register 3 */
280 uint piwbear3; /* 0x8dac - PCIX Inbound Window Base Extended Address Register 3 */
281 uint piwar3; /* 0x8db0 - PCIX Inbound Window Attributes Register 3 */
282 char res7[12];
283 uint pitar2; /* 0x8dc0 - PCIX Inbound Translation Address Register 2 */
284 uint pitear2; /* 0x8dc4 - PCIX Inbound Translation Extended Address Register 2 */
285 uint piwbar2; /* 0x8dc8 - PCIX Inbound Window Base Address Register 2 */
286 uint piwbear2; /* 0x8dcc - PCIX Inbound Window Base Extended Address Register 2 */
287 uint piwar2; /* 0x8dd0 - PCIX Inbound Window Attributes Register 2 */
288 char res8[12];
289 uint pitar1; /* 0x8de0 - PCIX Inbound Translation Address Register 1 */
290 uint pitear1; /* 0x8de4 - PCIX Inbound Translation Extended Address Register 1 */
291 uint piwbar1; /* 0x8de8 - PCIX Inbound Window Base Address Register 1 */
292 char res9[4];
293 uint piwar1; /* 0x8df0 - PCIX Inbound Window Attributes Register 1 */
294 char res10[12];
295 uint pedr; /* 0x8e00 - PCIX Error Detect Register */
296 uint pecdr; /* 0x8e04 - PCIX Error Capture Disable Register */
297 uint peer; /* 0x8e08 - PCIX Error Enable Register */
298 uint peattrcr; /* 0x8e0c - PCIX Error Attributes Capture Register */
299 uint peaddrcr; /* 0x8e10 - PCIX Error Address Capture Register */
300 uint peextaddrcr; /* 0x8e14 - PCIX Error Extended Address Capture Register */
301 uint pedlcr; /* 0x8e18 - PCIX Error Data Low Capture Register */
302 uint pedhcr; /* 0x8e1c - PCIX Error Error Data High Capture Register */
97074ed9
MM		 303 uint gas_timr; /* 0x8e20 - PCIX Gasket Timer Register */
304 char res11[476];
42d1f039
WD		 305} ccsr_pcix_t;
306
97074ed9
MM		 307#define PCIX_COMMAND 0x62
308#define POWAR_EN 0x80000000
309#define POWAR_IO_READ 0x00080000
310#define POWAR_MEM_READ 0x00040000
311#define POWAR_IO_WRITE 0x00008000
312#define POWAR_MEM_WRITE 0x00004000
313#define POWAR_MEM_512M 0x0000001c
314#define POWAR_IO_1M 0x00000013
315
316#define PIWAR_EN 0x80000000
317#define PIWAR_PF 0x20000000
318#define PIWAR_LOCAL 0x00f00000
319#define PIWAR_READ_SNOOP 0x00050000
320#define PIWAR_WRITE_SNOOP 0x00005000
321#define PIWAR_MEM_2G 0x0000001e
322
323
de1d0a69
JL		 324/*
325 * L2 Cache Registers(0x2_0000-0x2_1000)
326 */
42d1f039
WD		 327typedef struct ccsr_l2cache {
328 uint l2ctl; /* 0x20000 - L2 configuration register 0 */
329 char res1[12];
330 uint l2cewar0; /* 0x20010 - L2 cache external write address register 0 */
331 char res2[4];
332 uint l2cewcr0; /* 0x20018 - L2 cache external write control register 0 */
333 char res3[4];
334 uint l2cewar1; /* 0x20020 - L2 cache external write address register 1 */
335 char res4[4];
336 uint l2cewcr1; /* 0x20028 - L2 cache external write control register 1 */
337 char res5[4];
338 uint l2cewar2; /* 0x20030 - L2 cache external write address register 2 */
339 char res6[4];
340 uint l2cewcr2; /* 0x20038 - L2 cache external write control register 2 */
341 char res7[4];
342 uint l2cewar3; /* 0x20040 - L2 cache external write address register 3 */
343 char res8[4];
344 uint l2cewcr3; /* 0x20048 - L2 cache external write control register 3 */
345 char res9[180];
346 uint l2srbar0; /* 0x20100 - L2 memory-mapped SRAM base address register 0 */
347 char res10[4];
348 uint l2srbar1; /* 0x20108 - L2 memory-mapped SRAM base address register 1 */
349 char res11[3316];
350 uint l2errinjhi; /* 0x20e00 - L2 error injection mask high register */
351 uint l2errinjlo; /* 0x20e04 - L2 error injection mask low register */
352 uint l2errinjctl; /* 0x20e08 - L2 error injection tag/ECC control register */
353 char res12[20];
354 uint l2captdatahi; /* 0x20e20 - L2 error data high capture register */
355 uint l2captdatalo; /* 0x20e24 - L2 error data low capture register */
356 uint l2captecc; /* 0x20e28 - L2 error ECC capture register */
357 char res13[20];
358 uint l2errdet; /* 0x20e40 - L2 error detect register */
359 uint l2errdis; /* 0x20e44 - L2 error disable register */
360 uint l2errinten; /* 0x20e48 - L2 error interrupt enable register */
361 uint l2errattr; /* 0x20e4c - L2 error attributes capture register */
362 uint l2erraddr; /* 0x20e50 - L2 error address capture register */
363 char res14[4];
364 uint l2errctl; /* 0x20e58 - L2 error control register */
365 char res15[420];
366} ccsr_l2cache_t;
367
de1d0a69
JL		 368/*
369 * DMA Registers(0x2_1000-0x2_2000)
370 */
42d1f039
WD		 371typedef struct ccsr_dma {
372 char res1[256];
373 uint mr0; /* 0x21100 - DMA 0 Mode Register */
374 uint sr0; /* 0x21104 - DMA 0 Status Register */
375 char res2[4];
376 uint clndar0; /* 0x2110c - DMA 0 Current Link Descriptor Address Register */
377 uint satr0; /* 0x21110 - DMA 0 Source Attributes Register */
378 uint sar0; /* 0x21114 - DMA 0 Source Address Register */
379 uint datr0; /* 0x21118 - DMA 0 Destination Attributes Register */
380 uint dar0; /* 0x2111c - DMA 0 Destination Address Register */
381 uint bcr0; /* 0x21120 - DMA 0 Byte Count Register */
382 char res3[4];
383 uint nlndar0; /* 0x21128 - DMA 0 Next Link Descriptor Address Register */
384 char res4[8];
385 uint clabdar0; /* 0x21134 - DMA 0 Current List - Alternate Base Descriptor Address Register */
386 char res5[4];
387 uint nlsdar0; /* 0x2113c - DMA 0 Next List Descriptor Address Register */
388 uint ssr0; /* 0x21140 - DMA 0 Source Stride Register */
389 uint dsr0; /* 0x21144 - DMA 0 Destination Stride Register */
390 char res6[56];
391 uint mr1; /* 0x21180 - DMA 1 Mode Register */
392 uint sr1; /* 0x21184 - DMA 1 Status Register */
393 char res7[4];
394 uint clndar1; /* 0x2118c - DMA 1 Current Link Descriptor Address Register */
395 uint satr1; /* 0x21190 - DMA 1 Source Attributes Register */
396 uint sar1; /* 0x21194 - DMA 1 Source Address Register */
397 uint datr1; /* 0x21198 - DMA 1 Destination Attributes Register */
398 uint dar1; /* 0x2119c - DMA 1 Destination Address Register */
399 uint bcr1; /* 0x211a0 - DMA 1 Byte Count Register */
400 char res8[4];
401 uint nlndar1; /* 0x211a8 - DMA 1 Next Link Descriptor Address Register */
402 char res9[8];
403 uint clabdar1; /* 0x211b4 - DMA 1 Current List - Alternate Base Descriptor Address Register */
404 char res10[4];
405 uint nlsdar1; /* 0x211bc - DMA 1 Next List Descriptor Address Register */
406 uint ssr1; /* 0x211c0 - DMA 1 Source Stride Register */
407 uint dsr1; /* 0x211c4 - DMA 1 Destination Stride Register */
408 char res11[56];
409 uint mr2; /* 0x21200 - DMA 2 Mode Register */
410 uint sr2; /* 0x21204 - DMA 2 Status Register */
411 char res12[4];
412 uint clndar2; /* 0x2120c - DMA 2 Current Link Descriptor Address Register */
413 uint satr2; /* 0x21210 - DMA 2 Source Attributes Register */
414 uint sar2; /* 0x21214 - DMA 2 Source Address Register */
415 uint datr2; /* 0x21218 - DMA 2 Destination Attributes Register */
416 uint dar2; /* 0x2121c - DMA 2 Destination Address Register */
417 uint bcr2; /* 0x21220 - DMA 2 Byte Count Register */
418 char res13[4];
419 uint nlndar2; /* 0x21228 - DMA 2 Next Link Descriptor Address Register */
420 char res14[8];
421 uint clabdar2; /* 0x21234 - DMA 2 Current List - Alternate Base Descriptor Address Register */
422 char res15[4];
423 uint nlsdar2; /* 0x2123c - DMA 2 Next List Descriptor Address Register */
424 uint ssr2; /* 0x21240 - DMA 2 Source Stride Register */
425 uint dsr2; /* 0x21244 - DMA 2 Destination Stride Register */
426 char res16[56];
427 uint mr3; /* 0x21280 - DMA 3 Mode Register */
428 uint sr3; /* 0x21284 - DMA 3 Status Register */
429 char res17[4];
430 uint clndar3; /* 0x2128c - DMA 3 Current Link Descriptor Address Register */
431 uint satr3; /* 0x21290 - DMA 3 Source Attributes Register */
432 uint sar3; /* 0x21294 - DMA 3 Source Address Register */
433 uint datr3; /* 0x21298 - DMA 3 Destination Attributes Register */
434 uint dar3; /* 0x2129c - DMA 3 Destination Address Register */
435 uint bcr3; /* 0x212a0 - DMA 3 Byte Count Register */
436 char res18[4];
437 uint nlndar3; /* 0x212a8 - DMA 3 Next Link Descriptor Address Register */
438 char res19[8];
439 uint clabdar3; /* 0x212b4 - DMA 3 Current List - Alternate Base Descriptor Address Register */
440 char res20[4];
441 uint nlsdar3; /* 0x212bc - DMA 3 Next List Descriptor Address Register */
442 uint ssr3; /* 0x212c0 - DMA 3 Source Stride Register */
443 uint dsr3; /* 0x212c4 - DMA 3 Destination Stride Register */
444 char res21[56];
445 uint dgsr; /* 0x21300 - DMA General Status Register */
446 char res22[11516];
447} ccsr_dma_t;
448
de1d0a69
JL		 449/*
450 * tsec1 tsec2: 24000-26000
451 */
42d1f039
WD		 452typedef struct ccsr_tsec {
453 char res1[16];
454 uint ievent; /* 0x24010 - Interrupt Event Register */
455 uint imask; /* 0x24014 - Interrupt Mask Register */
456 uint edis; /* 0x24018 - Error Disabled Register */
457 char res2[4];
458 uint ecntrl; /* 0x24020 - Ethernet Control Register */
459 uint minflr; /* 0x24024 - Minimum Frame Length Register */
460 uint ptv; /* 0x24028 - Pause Time Value Register */
461 uint dmactrl; /* 0x2402c - DMA Control Register */
462 uint tbipa; /* 0x24030 - TBI PHY Address Register */
463 char res3[88];
464 uint fifo_tx_thr; /* 0x2408c - FIFO transmit threshold register */
465 char res4[8];
466 uint fifo_tx_starve; /* 0x24098 - FIFO transmit starve register */
467 uint fifo_tx_starve_shutoff; /* 0x2409c - FIFO transmit starve shutoff register */
468 char res5[96];
469 uint tctrl; /* 0x24100 - Transmit Control Register */
470 uint tstat; /* 0x24104 - Transmit Status Register */
471 char res6[4];
472 uint tbdlen; /* 0x2410c - Transmit Buffer Descriptor Data Length Register */
473 char res7[16];
474 uint ctbptrh; /* 0x24120 - Current Transmit Buffer Descriptor Pointer High Register */
475 uint ctbptr; /* 0x24124 - Current Transmit Buffer Descriptor Pointer Register */
476 char res8[88];
477 uint tbptrh; /* 0x24180 - Transmit Buffer Descriptor Pointer High Register */
478 uint tbptr; /* 0x24184 - Transmit Buffer Descriptor Pointer Low Register */
479 char res9[120];
480 uint tbaseh; /* 0x24200 - Transmit Descriptor Base Address High Register */
481 uint tbase; /* 0x24204 - Transmit Descriptor Base Address Register */
482 char res10[168];
483 uint ostbd; /* 0x242b0 - Out-of-Sequence Transmit Buffer Descriptor Register */
484 uint ostbdp; /* 0x242b4 - Out-of-Sequence Transmit Data Buffer Pointer Register */
485 uint os32tbdp; /* 0x242b8 - Out-of-Sequence 32 Bytes Transmit Data Buffer Pointer Low Register */
486 uint os32iptrh; /* 0x242bc - Out-of-Sequence 32 Bytes Transmit Insert Pointer High Register */
487 uint os32iptrl; /* 0x242c0 - Out-of-Sequence 32 Bytes Transmit Insert Pointer Low Register */
488 uint os32tbdr; /* 0x242c4 - Out-of-Sequence 32 Bytes Transmit Reserved Register */
489 uint os32iil; /* 0x242c8 - Out-of-Sequence 32 Bytes Transmit Insert Index/Length Register */
490 char res11[52];
491 uint rctrl; /* 0x24300 - Receive Control Register */
492 uint rstat; /* 0x24304 - Receive Status Register */
493 char res12[4];
494 uint rbdlen; /* 0x2430c - RxBD Data Length Register */
495 char res13[16];
496 uint crbptrh; /* 0x24320 - Current Receive Buffer Descriptor Pointer High */
497 uint crbptr; /* 0x24324 - Current Receive Buffer Descriptor Pointer */
498 char res14[24];
499 uint mrblr; /* 0x24340 - Maximum Receive Buffer Length Register */
500 uint mrblr2r3; /* 0x24344 - Maximum Receive Buffer Length R2R3 Register */
501 char res15[56];
502 uint rbptrh; /* 0x24380 - Receive Buffer Descriptor Pointer High 0 */
503 uint rbptr; /* 0x24384 - Receive Buffer Descriptor Pointer */
504 uint rbptrh1; /* 0x24388 - Receive Buffer Descriptor Pointer High 1 */
505 uint rbptrl1; /* 0x2438c - Receive Buffer Descriptor Pointer Low 1 */
506 uint rbptrh2; /* 0x24390 - Receive Buffer Descriptor Pointer High 2 */
507 uint rbptrl2; /* 0x24394 - Receive Buffer Descriptor Pointer Low 2 */
508 uint rbptrh3; /* 0x24398 - Receive Buffer Descriptor Pointer High 3 */
509 uint rbptrl3; /* 0x2439c - Receive Buffer Descriptor Pointer Low 3 */
510 char res16[96];
511 uint rbaseh; /* 0x24400 - Receive Descriptor Base Address High 0 */
512 uint rbase; /* 0x24404 - Receive Descriptor Base Address */
513 uint rbaseh1; /* 0x24408 - Receive Descriptor Base Address High 1 */
514 uint rbasel1; /* 0x2440c - Receive Descriptor Base Address Low 1 */
515 uint rbaseh2; /* 0x24410 - Receive Descriptor Base Address High 2 */
516 uint rbasel2; /* 0x24414 - Receive Descriptor Base Address Low 2 */
517 uint rbaseh3; /* 0x24418 - Receive Descriptor Base Address High 3 */
518 uint rbasel3; /* 0x2441c - Receive Descriptor Base Address Low 3 */
519 char res17[224];
520 uint maccfg1; /* 0x24500 - MAC Configuration 1 Register */
521 uint maccfg2; /* 0x24504 - MAC Configuration 2 Register */
522 uint ipgifg; /* 0x24508 - Inter Packet Gap/Inter Frame Gap Register */
523 uint hafdup; /* 0x2450c - Half Duplex Register */
524 uint maxfrm; /* 0x24510 - Maximum Frame Length Register */
525 char res18[12];
526 uint miimcfg; /* 0x24520 - MII Management Configuration Register */
527 uint miimcom; /* 0x24524 - MII Management Command Register */
528 uint miimadd; /* 0x24528 - MII Management Address Register */
529 uint miimcon; /* 0x2452c - MII Management Control Register */
530 uint miimstat; /* 0x24530 - MII Management Status Register */
531 uint miimind; /* 0x24534 - MII Management Indicator Register */
532 char res19[4];
533 uint ifstat; /* 0x2453c - Interface Status Register */
534 uint macstnaddr1; /* 0x24540 - Station Address Part 1 Register */
535 uint macstnaddr2; /* 0x24544 - Station Address Part 2 Register */
536 char res20[312];
537 uint tr64; /* 0x24680 - Transmit and Receive 64-byte Frame Counter */
538 uint tr127; /* 0x24684 - Transmit and Receive 65-127 byte Frame Counter */
539 uint tr255; /* 0x24688 - Transmit and Receive 128-255 byte Frame Counter */
540 uint tr511; /* 0x2468c - Transmit and Receive 256-511 byte Frame Counter */
541 uint tr1k; /* 0x24690 - Transmit and Receive 512-1023 byte Frame Counter */
542 uint trmax; /* 0x24694 - Transmit and Receive 1024-1518 byte Frame Counter */
543 uint trmgv; /* 0x24698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */
544 uint rbyt; /* 0x2469c - Receive Byte Counter */
545 uint rpkt; /* 0x246a0 - Receive Packet Counter */
546 uint rfcs; /* 0x246a4 - Receive FCS Error Counter */
547 uint rmca; /* 0x246a8 - Receive Multicast Packet Counter */
548 uint rbca; /* 0x246ac - Receive Broadcast Packet Counter */
549 uint rxcf; /* 0x246b0 - Receive Control Frame Packet Counter */
550 uint rxpf; /* 0x246b4 - Receive Pause Frame Packet Counter */
551 uint rxuo; /* 0x246b8 - Receive Unknown OP Code Counter */
552 uint raln; /* 0x246bc - Receive Alignment Error Counter */
553 uint rflr; /* 0x246c0 - Receive Frame Length Error Counter */
554 uint rcde; /* 0x246c4 - Receive Code Error Counter */
555 uint rcse; /* 0x246c8 - Receive Carrier Sense Error Counter */
556 uint rund; /* 0x246cc - Receive Undersize Packet Counter */
557 uint rovr; /* 0x246d0 - Receive Oversize Packet Counter */
558 uint rfrg; /* 0x246d4 - Receive Fragments Counter */
559 uint rjbr; /* 0x246d8 - Receive Jabber Counter */
560 uint rdrp; /* 0x246dc - Receive Drop Counter */
561 uint tbyt; /* 0x246e0 - Transmit Byte Counter Counter */
562 uint tpkt; /* 0x246e4 - Transmit Packet Counter */
563 uint tmca; /* 0x246e8 - Transmit Multicast Packet Counter */
564 uint tbca; /* 0x246ec - Transmit Broadcast Packet Counter */
565 uint txpf; /* 0x246f0 - Transmit Pause Control Frame Counter */
566 uint tdfr; /* 0x246f4 - Transmit Deferral Packet Counter */
567 uint tedf; /* 0x246f8 - Transmit Excessive Deferral Packet Counter */
568 uint tscl; /* 0x246fc - Transmit Single Collision Packet Counter */
569 uint tmcl; /* 0x24700 - Transmit Multiple Collision Packet Counter */
570 uint tlcl; /* 0x24704 - Transmit Late Collision Packet Counter */
571 uint txcl; /* 0x24708 - Transmit Excessive Collision Packet Counter */
572 uint tncl; /* 0x2470c - Transmit Total Collision Counter */
573 char res21[4];
574 uint tdrp; /* 0x24714 - Transmit Drop Frame Counter */
575 uint tjbr; /* 0x24718 - Transmit Jabber Frame Counter */
576 uint tfcs; /* 0x2471c - Transmit FCS Error Counter */
577 uint txcf; /* 0x24720 - Transmit Control Frame Counter */
578 uint tovr; /* 0x24724 - Transmit Oversize Frame Counter */
579 uint tund; /* 0x24728 - Transmit Undersize Frame Counter */
580 uint tfrg; /* 0x2472c - Transmit Fragments Frame Counter */
581 uint car1; /* 0x24730 - Carry Register One */
582 uint car2; /* 0x24734 - Carry Register Two */
583 uint cam1; /* 0x24738 - Carry Mask Register One */
584 uint cam2; /* 0x2473c - Carry Mask Register Two */
585 char res22[192];
586 uint iaddr0; /* 0x24800 - Indivdual address register 0 */
587 uint iaddr1; /* 0x24804 - Indivdual address register 1 */
588 uint iaddr2; /* 0x24808 - Indivdual address register 2 */
589 uint iaddr3; /* 0x2480c - Indivdual address register 3 */
590 uint iaddr4; /* 0x24810 - Indivdual address register 4 */
591 uint iaddr5; /* 0x24814 - Indivdual address register 5 */
592 uint iaddr6; /* 0x24818 - Indivdual address register 6 */
593 uint iaddr7; /* 0x2481c - Indivdual address register 7 */
594 char res23[96];
595 uint gaddr0; /* 0x24880 - Global address register 0 */
596 uint gaddr1; /* 0x24884 - Global address register 1 */
597 uint gaddr2; /* 0x24888 - Global address register 2 */
598 uint gaddr3; /* 0x2488c - Global address register 3 */
599 uint gaddr4; /* 0x24890 - Global address register 4 */
600 uint gaddr5; /* 0x24894 - Global address register 5 */
601 uint gaddr6; /* 0x24898 - Global address register 6 */
602 uint gaddr7; /* 0x2489c - Global address register 7 */
603 char res24[96];
604 uint pmd0; /* 0x24900 - Pattern Match Data Register */
605 char res25[4];
606 uint pmask0; /* 0x24908 - Pattern Mask Register */
607 char res26[4];
608 uint pcntrl0; /* 0x24910 - Pattern Match Control Register */
609 char res27[4];
610 uint pattrb0; /* 0x24918 - Pattern Match Attributes Register */
611 uint pattrbeli0; /* 0x2491c - Pattern Match Attributes Extract Length and Extract Index Register */
612 uint pmd1; /* 0x24920 - Pattern Match Data Register */
613 char res28[4];
614 uint pmask1; /* 0x24928 - Pattern Mask Register */
615 char res29[4];
616 uint pcntrl1; /* 0x24930 - Pattern Match Control Register */
617 char res30[4];
618 uint pattrb1; /* 0x24938 - Pattern Match Attributes Register */
619 uint pattrbeli1; /* 0x2493c - Pattern Match Attributes Extract Length and Extract Index Register */
620 uint pmd2; /* 0x24940 - Pattern Match Data Register */
621 char res31[4];
622 uint pmask2; /* 0x24948 - Pattern Mask Register */
623 char res32[4];
624 uint pcntrl2; /* 0x24950 - Pattern Match Control Register */
625 char res33[4];
626 uint pattrb2; /* 0x24958 - Pattern Match Attributes Register */
627 uint pattrbeli2; /* 0x2495c - Pattern Match Attributes Extract Length and Extract Index Register */
628 uint pmd3; /* 0x24960 - Pattern Match Data Register */
629 char res34[4];
630 uint pmask3; /* 0x24968 - Pattern Mask Register */
631 char res35[4];
632 uint pcntrl3; /* 0x24970 - Pattern Match Control Register */
633 char res36[4];
634 uint pattrb3; /* 0x24978 - Pattern Match Attributes Register */
635 uint pattrbeli3; /* 0x2497c - Pattern Match Attributes Extract Length and Extract Index Register */
636 uint pmd4; /* 0x24980 - Pattern Match Data Register */
637 char res37[4];
638 uint pmask4; /* 0x24988 - Pattern Mask Register */
639 char res38[4];
640 uint pcntrl4; /* 0x24990 - Pattern Match Control Register */
641 char res39[4];
642 uint pattrb4; /* 0x24998 - Pattern Match Attributes Register */
643 uint pattrbeli4; /* 0x2499c - Pattern Match Attributes Extract Length and Extract Index Register */
644 uint pmd5; /* 0x249a0 - Pattern Match Data Register */
645 char res40[4];
646 uint pmask5; /* 0x249a8 - Pattern Mask Register */
647 char res41[4];
648 uint pcntrl5; /* 0x249b0 - Pattern Match Control Register */
649 char res42[4];
650 uint pattrb5; /* 0x249b8 - Pattern Match Attributes Register */
651 uint pattrbeli5; /* 0x249bc - Pattern Match Attributes Extract Length and Extract Index Register */
652 uint pmd6; /* 0x249c0 - Pattern Match Data Register */
653 char res43[4];
654 uint pmask6; /* 0x249c8 - Pattern Mask Register */
655 char res44[4];
656 uint pcntrl6; /* 0x249d0 - Pattern Match Control Register */
657 char res45[4];
658 uint pattrb6; /* 0x249d8 - Pattern Match Attributes Register */
659 uint pattrbeli6; /* 0x249dc - Pattern Match Attributes Extract Length and Extract Index Register */
660 uint pmd7; /* 0x249e0 - Pattern Match Data Register */
661 char res46[4];
662 uint pmask7; /* 0x249e8 - Pattern Mask Register */
663 char res47[4];
664 uint pcntrl7; /* 0x249f0 - Pattern Match Control Register */
665 char res48[4];
666 uint pattrb7; /* 0x249f8 - Pattern Match Attributes Register */
667 uint pattrbeli7; /* 0x249fc - Pattern Match Attributes Extract Length and Extract Index Register */
668 uint pmd8; /* 0x24a00 - Pattern Match Data Register */
669 char res49[4];
670 uint pmask8; /* 0x24a08 - Pattern Mask Register */
671 char res50[4];
672 uint pcntrl8; /* 0x24a10 - Pattern Match Control Register */
673 char res51[4];
674 uint pattrb8; /* 0x24a18 - Pattern Match Attributes Register */
675 uint pattrbeli8; /* 0x24a1c - Pattern Match Attributes Extract Length and Extract Index Register */
676 uint pmd9; /* 0x24a20 - Pattern Match Data Register */
677 char res52[4];
678 uint pmask9; /* 0x24a28 - Pattern Mask Register */
679 char res53[4];
680 uint pcntrl9; /* 0x24a30 - Pattern Match Control Register */
681 char res54[4];
682 uint pattrb9; /* 0x24a38 - Pattern Match Attributes Register */
683 uint pattrbeli9; /* 0x24a3c - Pattern Match Attributes Extract Length and Extract Index Register */
684 uint pmd10; /* 0x24a40 - Pattern Match Data Register */
685 char res55[4];
686 uint pmask10; /* 0x24a48 - Pattern Mask Register */
687 char res56[4];
688 uint pcntrl10; /* 0x24a50 - Pattern Match Control Register */
689 char res57[4];
690 uint pattrb10; /* 0x24a58 - Pattern Match Attributes Register */
691 uint pattrbeli10; /* 0x24a5c - Pattern Match Attributes Extract Length and Extract Index Register */
692 uint pmd11; /* 0x24a60 - Pattern Match Data Register */
693 char res58[4];
694 uint pmask11; /* 0x24a68 - Pattern Mask Register */
695 char res59[4];
696 uint pcntrl11; /* 0x24a70 - Pattern Match Control Register */
697 char res60[4];
698 uint pattrb11; /* 0x24a78 - Pattern Match Attributes Register */
699 uint pattrbeli11; /* 0x24a7c - Pattern Match Attributes Extract Length and Extract Index Register */
700 uint pmd12; /* 0x24a80 - Pattern Match Data Register */
701 char res61[4];
702 uint pmask12; /* 0x24a88 - Pattern Mask Register */
703 char res62[4];
704 uint pcntrl12; /* 0x24a90 - Pattern Match Control Register */
705 char res63[4];
706 uint pattrb12; /* 0x24a98 - Pattern Match Attributes Register */
707 uint pattrbeli12; /* 0x24a9c - Pattern Match Attributes Extract Length and Extract Index Register */
708 uint pmd13; /* 0x24aa0 - Pattern Match Data Register */
709 char res64[4];
710 uint pmask13; /* 0x24aa8 - Pattern Mask Register */
711 char res65[4];
712 uint pcntrl13; /* 0x24ab0 - Pattern Match Control Register */
713 char res66[4];
714 uint pattrb13; /* 0x24ab8 - Pattern Match Attributes Register */
715 uint pattrbeli13; /* 0x24abc - Pattern Match Attributes Extract Length and Extract Index Register */
716 uint pmd14; /* 0x24ac0 - Pattern Match Data Register */
717 char res67[4];
718 uint pmask14; /* 0x24ac8 - Pattern Mask Register */
719 char res68[4];
720 uint pcntrl14; /* 0x24ad0 - Pattern Match Control Register */
721 char res69[4];
722 uint pattrb14; /* 0x24ad8 - Pattern Match Attributes Register */
723 uint pattrbeli14; /* 0x24adc - Pattern Match Attributes Extract Length and Extract Index Register */
724 uint pmd15; /* 0x24ae0 - Pattern Match Data Register */
725 char res70[4];
726 uint pmask15; /* 0x24ae8 - Pattern Mask Register */
727 char res71[4];
728 uint pcntrl15; /* 0x24af0 - Pattern Match Control Register */
729 char res72[4];
730 uint pattrb15; /* 0x24af8 - Pattern Match Attributes Register */
731 uint pattrbeli15; /* 0x24afc - Pattern Match Attributes Extract Length and Extract Index Register */
732 char res73[248];
733 uint attr; /* 0x24bf8 - Attributes Register */
734 uint attreli; /* 0x24bfc - Attributes Extract Length and Extract Index Register */
735 char res74[1024];
736} ccsr_tsec_t;
737
de1d0a69 738/*
04db4008 739 * PIC Registers(0x4_0000-0x8_0000)
de1d0a69 740 */
42d1f039 741typedef struct ccsr_pic {
04db4008 742 char res1[64]; /* 0x40000 */
42d1f039
WD		 743 uint ipidr0; /* 0x40040 - Interprocessor Interrupt Dispatch Register 0 */
744 char res2[12];
745 uint ipidr1; /* 0x40050 - Interprocessor Interrupt Dispatch Register 1 */
746 char res3[12];
747 uint ipidr2; /* 0x40060 - Interprocessor Interrupt Dispatch Register 2 */
748 char res4[12];
749 uint ipidr3; /* 0x40070 - Interprocessor Interrupt Dispatch Register 3 */
750 char res5[12];
751 uint ctpr; /* 0x40080 - Current Task Priority Register */
752 char res6[12];
753 uint whoami; /* 0x40090 - Who Am I Register */
754 char res7[12];
755 uint iack; /* 0x400a0 - Interrupt Acknowledge Register */
756 char res8[12];
757 uint eoi; /* 0x400b0 - End Of Interrupt Register */
758 char res9[3916];
759 uint frr; /* 0x41000 - Feature Reporting Register */
760 char res10[28];
761 uint gcr; /* 0x41020 - Global Configuration Register */
343117bf
WD		 762#define MPC85xx_PICGCR_RST 0x80000000
763#define MPC85xx_PICGCR_M 0x20000000
42d1f039
WD		 764 char res11[92];
765 uint vir; /* 0x41080 - Vendor Identification Register */
766 char res12[12];
767 uint pir; /* 0x41090 - Processor Initialization Register */
768 char res13[12];
769 uint ipivpr0; /* 0x410a0 - IPI Vector/Priority Register 0 */
770 char res14[12];
771 uint ipivpr1; /* 0x410b0 - IPI Vector/Priority Register 1 */
772 char res15[12];
773 uint ipivpr2; /* 0x410c0 - IPI Vector/Priority Register 2 */
774 char res16[12];
775 uint ipivpr3; /* 0x410d0 - IPI Vector/Priority Register 3 */
776 char res17[12];
777 uint svr; /* 0x410e0 - Spurious Vector Register */
778 char res18[12];
779 uint tfrr; /* 0x410f0 - Timer Frequency Reporting Register */
780 char res19[12];
781 uint gtccr0; /* 0x41100 - Global Timer Current Count Register 0 */
782 char res20[12];
783 uint gtbcr0; /* 0x41110 - Global Timer Base Count Register 0 */
784 char res21[12];
785 uint gtvpr0; /* 0x41120 - Global Timer Vector/Priority Register 0 */
786 char res22[12];
787 uint gtdr0; /* 0x41130 - Global Timer Destination Register 0 */
788 char res23[12];
789 uint gtccr1; /* 0x41140 - Global Timer Current Count Register 1 */
790 char res24[12];
791 uint gtbcr1; /* 0x41150 - Global Timer Base Count Register 1 */
792 char res25[12];
793 uint gtvpr1; /* 0x41160 - Global Timer Vector/Priority Register 1 */
794 char res26[12];
795 uint gtdr1; /* 0x41170 - Global Timer Destination Register 1 */
796 char res27[12];
797 uint gtccr2; /* 0x41180 - Global Timer Current Count Register 2 */
798 char res28[12];
799 uint gtbcr2; /* 0x41190 - Global Timer Base Count Register 2 */
800 char res29[12];
801 uint gtvpr2; /* 0x411a0 - Global Timer Vector/Priority Register 2 */
802 char res30[12];
803 uint gtdr2; /* 0x411b0 - Global Timer Destination Register 2 */
804 char res31[12];
805 uint gtccr3; /* 0x411c0 - Global Timer Current Count Register 3 */
806 char res32[12];
807 uint gtbcr3; /* 0x411d0 - Global Timer Base Count Register 3 */
808 char res33[12];
809 uint gtvpr3; /* 0x411e0 - Global Timer Vector/Priority Register 3 */
810 char res34[12];
811 uint gtdr3; /* 0x411f0 - Global Timer Destination Register 3 */
812 char res35[268];
813 uint tcr; /* 0x41300 - Timer Control Register */
814 char res36[12];
815 uint irqsr0; /* 0x41310 - IRQ_OUT Summary Register 0 */
816 char res37[12];
817 uint irqsr1; /* 0x41320 - IRQ_OUT Summary Register 1 */
818 char res38[12];
819 uint cisr0; /* 0x41330 - Critical Interrupt Summary Register 0 */
820 char res39[12];
821 uint cisr1; /* 0x41340 - Critical Interrupt Summary Register 1 */
822 char res40[188];
823 uint msgr0; /* 0x41400 - Message Register 0 */
824 char res41[12];
825 uint msgr1; /* 0x41410 - Message Register 1 */
826 char res42[12];
827 uint msgr2; /* 0x41420 - Message Register 2 */
828 char res43[12];
829 uint msgr3; /* 0x41430 - Message Register 3 */
830 char res44[204];
831 uint mer; /* 0x41500 - Message Enable Register */
832 char res45[12];
833 uint msr; /* 0x41510 - Message Status Register */
834 char res46[60140];
835 uint eivpr0; /* 0x50000 - External Interrupt Vector/Priority Register 0 */
836 char res47[12];
837 uint eidr0; /* 0x50010 - External Interrupt Destination Register 0 */
838 char res48[12];
839 uint eivpr1; /* 0x50020 - External Interrupt Vector/Priority Register 1 */
840 char res49[12];
841 uint eidr1; /* 0x50030 - External Interrupt Destination Register 1 */
842 char res50[12];
843 uint eivpr2; /* 0x50040 - External Interrupt Vector/Priority Register 2 */
844 char res51[12];
845 uint eidr2; /* 0x50050 - External Interrupt Destination Register 2 */
846 char res52[12];
847 uint eivpr3; /* 0x50060 - External Interrupt Vector/Priority Register 3 */
848 char res53[12];
849 uint eidr3; /* 0x50070 - External Interrupt Destination Register 3 */
850 char res54[12];
851 uint eivpr4; /* 0x50080 - External Interrupt Vector/Priority Register 4 */
852 char res55[12];
853 uint eidr4; /* 0x50090 - External Interrupt Destination Register 4 */
854 char res56[12];
855 uint eivpr5; /* 0x500a0 - External Interrupt Vector/Priority Register 5 */
856 char res57[12];
857 uint eidr5; /* 0x500b0 - External Interrupt Destination Register 5 */
858 char res58[12];
859 uint eivpr6; /* 0x500c0 - External Interrupt Vector/Priority Register 6 */
860 char res59[12];
861 uint eidr6; /* 0x500d0 - External Interrupt Destination Register 6 */
862 char res60[12];
863 uint eivpr7; /* 0x500e0 - External Interrupt Vector/Priority Register 7 */
864 char res61[12];
865 uint eidr7; /* 0x500f0 - External Interrupt Destination Register 7 */
866 char res62[12];
867 uint eivpr8; /* 0x50100 - External Interrupt Vector/Priority Register 8 */
868 char res63[12];
869 uint eidr8; /* 0x50110 - External Interrupt Destination Register 8 */
870 char res64[12];
871 uint eivpr9; /* 0x50120 - External Interrupt Vector/Priority Register 9 */
872 char res65[12];
873 uint eidr9; /* 0x50130 - External Interrupt Destination Register 9 */
874 char res66[12];
875 uint eivpr10; /* 0x50140 - External Interrupt Vector/Priority Register 10 */
876 char res67[12];
877 uint eidr10; /* 0x50150 - External Interrupt Destination Register 10 */
878 char res68[12];
879 uint eivpr11; /* 0x50160 - External Interrupt Vector/Priority Register 11 */
880 char res69[12];
881 uint eidr11; /* 0x50170 - External Interrupt Destination Register 11 */
882 char res70[140];
883 uint iivpr0; /* 0x50200 - Internal Interrupt Vector/Priority Register 0 */
884 char res71[12];
885 uint iidr0; /* 0x50210 - Internal Interrupt Destination Register 0 */
886 char res72[12];
887 uint iivpr1; /* 0x50220 - Internal Interrupt Vector/Priority Register 1 */
888 char res73[12];
889 uint iidr1; /* 0x50230 - Internal Interrupt Destination Register 1 */
890 char res74[12];
891 uint iivpr2; /* 0x50240 - Internal Interrupt Vector/Priority Register 2 */
892 char res75[12];
893 uint iidr2; /* 0x50250 - Internal Interrupt Destination Register 2 */
894 char res76[12];
895 uint iivpr3; /* 0x50260 - Internal Interrupt Vector/Priority Register 3 */
896 char res77[12];
897 uint iidr3; /* 0x50270 - Internal Interrupt Destination Register 3 */
898 char res78[12];
899 uint iivpr4; /* 0x50280 - Internal Interrupt Vector/Priority Register 4 */
900 char res79[12];
901 uint iidr4; /* 0x50290 - Internal Interrupt Destination Register 4 */
902 char res80[12];
903 uint iivpr5; /* 0x502a0 - Internal Interrupt Vector/Priority Register 5 */
904 char res81[12];
905 uint iidr5; /* 0x502b0 - Internal Interrupt Destination Register 5 */
906 char res82[12];
907 uint iivpr6; /* 0x502c0 - Internal Interrupt Vector/Priority Register 6 */
908 char res83[12];
909 uint iidr6; /* 0x502d0 - Internal Interrupt Destination Register 6 */
910 char res84[12];
911 uint iivpr7; /* 0x502e0 - Internal Interrupt Vector/Priority Register 7 */
912 char res85[12];
913 uint iidr7; /* 0x502f0 - Internal Interrupt Destination Register 7 */
914 char res86[12];
915 uint iivpr8; /* 0x50300 - Internal Interrupt Vector/Priority Register 8 */
916 char res87[12];
917 uint iidr8; /* 0x50310 - Internal Interrupt Destination Register 8 */
918 char res88[12];
919 uint iivpr9; /* 0x50320 - Internal Interrupt Vector/Priority Register 9 */
920 char res89[12];
921 uint iidr9; /* 0x50330 - Internal Interrupt Destination Register 9 */
922 char res90[12];
923 uint iivpr10; /* 0x50340 - Internal Interrupt Vector/Priority Register 10 */
924 char res91[12];
925 uint iidr10; /* 0x50350 - Internal Interrupt Destination Register 10 */
926 char res92[12];
927 uint iivpr11; /* 0x50360 - Internal Interrupt Vector/Priority Register 11 */
928 char res93[12];
929 uint iidr11; /* 0x50370 - Internal Interrupt Destination Register 11 */
930 char res94[12];
931 uint iivpr12; /* 0x50380 - Internal Interrupt Vector/Priority Register 12 */
932 char res95[12];
933 uint iidr12; /* 0x50390 - Internal Interrupt Destination Register 12 */
934 char res96[12];
935 uint iivpr13; /* 0x503a0 - Internal Interrupt Vector/Priority Register 13 */
936 char res97[12];
937 uint iidr13; /* 0x503b0 - Internal Interrupt Destination Register 13 */
938 char res98[12];
939 uint iivpr14; /* 0x503c0 - Internal Interrupt Vector/Priority Register 14 */
940 char res99[12];
941 uint iidr14; /* 0x503d0 - Internal Interrupt Destination Register 14 */
942 char res100[12];
943 uint iivpr15; /* 0x503e0 - Internal Interrupt Vector/Priority Register 15 */
944 char res101[12];
945 uint iidr15; /* 0x503f0 - Internal Interrupt Destination Register 15 */
946 char res102[12];
947 uint iivpr16; /* 0x50400 - Internal Interrupt Vector/Priority Register 16 */
948 char res103[12];
949 uint iidr16; /* 0x50410 - Internal Interrupt Destination Register 16 */
950 char res104[12];
951 uint iivpr17; /* 0x50420 - Internal Interrupt Vector/Priority Register 17 */
952 char res105[12];
953 uint iidr17; /* 0x50430 - Internal Interrupt Destination Register 17 */
954 char res106[12];
955 uint iivpr18; /* 0x50440 - Internal Interrupt Vector/Priority Register 18 */
956 char res107[12];
957 uint iidr18; /* 0x50450 - Internal Interrupt Destination Register 18 */
958 char res108[12];
959 uint iivpr19; /* 0x50460 - Internal Interrupt Vector/Priority Register 19 */
960 char res109[12];
961 uint iidr19; /* 0x50470 - Internal Interrupt Destination Register 19 */
962 char res110[12];
963 uint iivpr20; /* 0x50480 - Internal Interrupt Vector/Priority Register 20 */
964 char res111[12];
965 uint iidr20; /* 0x50490 - Internal Interrupt Destination Register 20 */
966 char res112[12];
967 uint iivpr21; /* 0x504a0 - Internal Interrupt Vector/Priority Register 21 */
968 char res113[12];
969 uint iidr21; /* 0x504b0 - Internal Interrupt Destination Register 21 */
970 char res114[12];
971 uint iivpr22; /* 0x504c0 - Internal Interrupt Vector/Priority Register 22 */
972 char res115[12];
973 uint iidr22; /* 0x504d0 - Internal Interrupt Destination Register 22 */
974 char res116[12];
975 uint iivpr23; /* 0x504e0 - Internal Interrupt Vector/Priority Register 23 */
976 char res117[12];
977 uint iidr23; /* 0x504f0 - Internal Interrupt Destination Register 23 */
978 char res118[12];
979 uint iivpr24; /* 0x50500 - Internal Interrupt Vector/Priority Register 24 */
980 char res119[12];
981 uint iidr24; /* 0x50510 - Internal Interrupt Destination Register 24 */
982 char res120[12];
983 uint iivpr25; /* 0x50520 - Internal Interrupt Vector/Priority Register 25 */
984 char res121[12];
985 uint iidr25; /* 0x50530 - Internal Interrupt Destination Register 25 */
986 char res122[12];
987 uint iivpr26; /* 0x50540 - Internal Interrupt Vector/Priority Register 26 */
988 char res123[12];
989 uint iidr26; /* 0x50550 - Internal Interrupt Destination Register 26 */
990 char res124[12];
991 uint iivpr27; /* 0x50560 - Internal Interrupt Vector/Priority Register 27 */
992 char res125[12];
993 uint iidr27; /* 0x50570 - Internal Interrupt Destination Register 27 */
994 char res126[12];
995 uint iivpr28; /* 0x50580 - Internal Interrupt Vector/Priority Register 28 */
996 char res127[12];
997 uint iidr28; /* 0x50590 - Internal Interrupt Destination Register 28 */
998 char res128[12];
999 uint iivpr29; /* 0x505a0 - Internal Interrupt Vector/Priority Register 29 */
1000 char res129[12];
1001 uint iidr29; /* 0x505b0 - Internal Interrupt Destination Register 29 */
1002 char res130[12];
1003 uint iivpr30; /* 0x505c0 - Internal Interrupt Vector/Priority Register 30 */
1004 char res131[12];
1005 uint iidr30; /* 0x505d0 - Internal Interrupt Destination Register 30 */
1006 char res132[12];
1007 uint iivpr31; /* 0x505e0 - Internal Interrupt Vector/Priority Register 31 */
1008 char res133[12];
1009 uint iidr31; /* 0x505f0 - Internal Interrupt Destination Register 31 */
1010 char res134[4108];
1011 uint mivpr0; /* 0x51600 - Messaging Interrupt Vector/Priority Register 0 */
1012 char res135[12];
1013 uint midr0; /* 0x51610 - Messaging Interrupt Destination Register 0 */
1014 char res136[12];
1015 uint mivpr1; /* 0x51620 - Messaging Interrupt Vector/Priority Register 1 */
1016 char res137[12];
1017 uint midr1; /* 0x51630 - Messaging Interrupt Destination Register 1 */
1018 char res138[12];
1019 uint mivpr2; /* 0x51640 - Messaging Interrupt Vector/Priority Register 2 */
1020 char res139[12];
1021 uint midr2; /* 0x51650 - Messaging Interrupt Destination Register 2 */
1022 char res140[12];
1023 uint mivpr3; /* 0x51660 - Messaging Interrupt Vector/Priority Register 3 */
1024 char res141[12];
1025 uint midr3; /* 0x51670 - Messaging Interrupt Destination Register 3 */
1026 char res142[59852];
1027 uint ipi0dr0; /* 0x60040 - Processor 0 Interprocessor Interrupt Dispatch Register 0 */
1028 char res143[12];
1029 uint ipi0dr1; /* 0x60050 - Processor 0 Interprocessor Interrupt Dispatch Register 1 */
1030 char res144[12];
1031 uint ipi0dr2; /* 0x60060 - Processor 0 Interprocessor Interrupt Dispatch Register 2 */
1032 char res145[12];
1033 uint ipi0dr3; /* 0x60070 - Processor 0 Interprocessor Interrupt Dispatch Register 3 */
1034 char res146[12];
1035 uint ctpr0; /* 0x60080 - Current Task Priority Register for Processor 0 */
1036 char res147[12];
1037 uint whoami0; /* 0x60090 - Who Am I Register for Processor 0 */
1038 char res148[12];
1039 uint iack0; /* 0x600a0 - Interrupt Acknowledge Register for Processor 0 */
1040 char res149[12];
1041 uint eoi0; /* 0x600b0 - End Of Interrupt Register for Processor 0 */
1042 char res150[130892];
1043} ccsr_pic_t;
1044
de1d0a69
JL		 1045/*
1046 * CPM Block(0x8_0000-0xc_0000)
1047 */
9c4c5ae3 1048#ifndef CONFIG_CPM2
42d1f039
WD		 1049typedef struct ccsr_cpm {
1050 char res[262144];
1051} ccsr_cpm_t;
1052#else
de1d0a69
JL		 1053/*
1054 * 0x8000-0x8ffff:DPARM
1055 * 0x9000-0x90bff: General SIU
1056 */
42d1f039 1057typedef struct ccsr_cpm_siu {
53677ef1 1058 char res1[80];
42d1f039
WD		 1059 uint smaer;
1060 uint smser;
1061 uint smevr;
1062 char res2[4];
1063 uint lmaer;
1064 uint lmser;
1065 uint lmevr;
1066 char res3[2964];
1067} ccsr_cpm_siu_t;
1068
1069/* 0x90c00-0x90cff: Interrupt Controller */
1070typedef struct ccsr_cpm_intctl {
1071 ushort sicr;
1072 char res1[2];
1073 uint sivec;
1074 uint sipnrh;
1075 uint sipnrl;
1076 uint siprr;
1077 uint scprrh;
1078 uint scprrl;
1079 uint simrh;
1080 uint simrl;
1081 uint siexr;
1082 char res2[88];
1083 uint sccr;
1084 char res3[124];
1085} ccsr_cpm_intctl_t;
1086
1087/* 0x90d00-0x90d7f: input/output port */
1088typedef struct ccsr_cpm_iop {
1089 uint pdira;
1090 uint ppara;
1091 uint psora;
1092 uint podra;
1093 uint pdata;
1094 char res1[12];
1095 uint pdirb;
1096 uint pparb;
1097 uint psorb;
1098 uint podrb;
1099 uint pdatb;
1100 char res2[12];
1101 uint pdirc;
1102 uint pparc;
1103 uint psorc;
1104 uint podrc;
1105 uint pdatc;
1106 char res3[12];
1107 uint pdird;
1108 uint ppard;
1109 uint psord;
1110 uint podrd;
1111 uint pdatd;
1112 char res4[12];
1113} ccsr_cpm_iop_t;
1114
1115/* 0x90d80-0x91017: CPM timers */
1116typedef struct ccsr_cpm_timer {
1117 u_char tgcr1;
1118 char res1[3];
1119 u_char tgcr2;
1120 char res2[11];
1121 ushort tmr1;
1122 ushort tmr2;
1123 ushort trr1;
1124 ushort trr2;
1125 ushort tcr1;
1126 ushort tcr2;
1127 ushort tcn1;
1128 ushort tcn2;
1129 ushort tmr3;
1130 ushort tmr4;
1131 ushort trr3;
1132 ushort trr4;
1133 ushort tcr3;
1134 ushort tcr4;
1135 ushort tcn3;
1136 ushort tcn4;
1137 ushort ter1;
1138 ushort ter2;
1139 ushort ter3;
1140 ushort ter4;
1141 char res3[608];
1142} ccsr_cpm_timer_t;
1143
1144/* 0x91018-0x912ff: SDMA */
1145typedef struct ccsr_cpm_sdma {
1146 uchar sdsr;
53677ef1
WD		 1147 char res1[3];
1148 uchar sdmr;
1149 char res2[739];
42d1f039
WD		 1150} ccsr_cpm_sdma_t;
1151
1152/* 0x91300-0x9131f: FCC1 */
1153typedef struct ccsr_cpm_fcc1 {
1154 uint gfmr;
1155 uint fpsmr;
1156 ushort ftodr;
1157 char res1[2];
1158 ushort fdsr;
1159 char res2[2];
1160 ushort fcce;
1161 char res3[2];
1162 ushort fccm;
1163 char res4[2];
1164 u_char fccs;
1165 char res5[3];
1166 u_char ftirr_phy[4];
1167} ccsr_cpm_fcc1_t;
1168
1169/* 0x91320-0x9133f: FCC2 */
1170typedef struct ccsr_cpm_fcc2 {
1171 uint gfmr;
1172 uint fpsmr;
1173 ushort ftodr;
1174 char res1[2];
1175 ushort fdsr;
1176 char res2[2];
1177 ushort fcce;
1178 char res3[2];
1179 ushort fccm;
1180 char res4[2];
1181 u_char fccs;
1182 char res5[3];
1183 u_char ftirr_phy[4];
1184} ccsr_cpm_fcc2_t;
1185
1186/* 0x91340-0x9137f: FCC3 */
1187typedef struct ccsr_cpm_fcc3 {
1188 uint gfmr;
1189 uint fpsmr;
1190 ushort ftodr;
1191 char res1[2];
1192 ushort fdsr;
1193 char res2[2];
1194 ushort fcce;
1195 char res3[2];
1196 ushort fccm;
1197 char res4[2];
1198 u_char fccs;
1199 char res5[3];
1200 char res[36];
1201} ccsr_cpm_fcc3_t;
1202
1203/* 0x91380-0x9139f: FCC1 extended */
1204typedef struct ccsr_cpm_fcc1_ext {
1205 uint firper;
1206 uint firer;
1207 uint firsr_h;
1208 uint firsr_l;
1209 u_char gfemr;
1210 char res[15];
1211
1212} ccsr_cpm_fcc1_ext_t;
1213
1214/* 0x913a0-0x913cf: FCC2 extended */
1215typedef struct ccsr_cpm_fcc2_ext {
1216 uint firper;
1217 uint firer;
1218 uint firsr_h;
1219 uint firsr_l;
1220 u_char gfemr;
1221 char res[31];
1222} ccsr_cpm_fcc2_ext_t;
1223
1224/* 0x913d0-0x913ff: FCC3 extended */
1225typedef struct ccsr_cpm_fcc3_ext {
1226 u_char gfemr;
1227 char res[47];
1228} ccsr_cpm_fcc3_ext_t;
1229
1230/* 0x91400-0x915ef: TC layers */
1231typedef struct ccsr_cpm_tmp1 {
53677ef1 1232 char res[496];
42d1f039
WD		 1233} ccsr_cpm_tmp1_t;
1234
1235/* 0x915f0-0x9185f: BRGs:5,6,7,8 */
1236typedef struct ccsr_cpm_brg2 {
1237 uint brgc5;
1238 uint brgc6;
1239 uint brgc7;
1240 uint brgc8;
1241 char res[608];
1242} ccsr_cpm_brg2_t;
1243
1244/* 0x91860-0x919bf: I2C */
1245typedef struct ccsr_cpm_i2c {
1246 u_char i2mod;
1247 char res1[3];
1248 u_char i2add;
1249 char res2[3];
1250 u_char i2brg;
1251 char res3[3];
1252 u_char i2com;
1253 char res4[3];
1254 u_char i2cer;
1255 char res5[3];
1256 u_char i2cmr;
1257 char res6[331];
1258} ccsr_cpm_i2c_t;
1259
1260/* 0x919c0-0x919ef: CPM core */
1261typedef struct ccsr_cpm_cp {
1262 uint cpcr;
1263 uint rccr;
1264 char res1[14];
1265 ushort rter;
1266 char res2[2];
1267 ushort rtmr;
1268 ushort rtscr;
1269 char res3[2];
1270 uint rtsr;
1271 char res4[12];
1272} ccsr_cpm_cp_t;
1273
1274/* 0x919f0-0x919ff: BRGs:1,2,3,4 */
1275typedef struct ccsr_cpm_brg1 {
1276 uint brgc1;
1277 uint brgc2;
1278 uint brgc3;
1279 uint brgc4;
1280} ccsr_cpm_brg1_t;
1281
1282/* 0x91a00-0x91a9f: SCC1-SCC4 */
1283typedef struct ccsr_cpm_scc {
1284 uint gsmrl;
1285 uint gsmrh;
1286 ushort psmr;
1287 char res1[2];
1288 ushort todr;
1289 ushort dsr;
1290 ushort scce;
1291 char res2[2];
1292 ushort sccm;
1293 char res3;
1294 u_char sccs;
1295 char res4[8];
1296} ccsr_cpm_scc_t;
1297
1298/* 0x91a80-0x91a9f */
1299typedef struct ccsr_cpm_tmp2 {
53677ef1 1300 char res[32];
42d1f039
WD		 1301} ccsr_cpm_tmp2_t;
1302
1303/* 0x91aa0-0x91aff: SPI */
1304typedef struct ccsr_cpm_spi {
1305 ushort spmode;
1306 char res1[4];
1307 u_char spie;
1308 char res2[3];
1309 u_char spim;
1310 char res3[2];
1311 u_char spcom;
1312 char res4[82];
1313} ccsr_cpm_spi_t;
1314
1315/* 0x91b00-0x91b1f: CPM MUX */
1316typedef struct ccsr_cpm_mux {
1317 u_char cmxsi1cr;
1318 char res1;
1319 u_char cmxsi2cr;
1320 char res2;
1321 uint cmxfcr;
1322 uint cmxscr;
1323 char res3[2];
1324 ushort cmxuar;
1325 char res4[16];
1326} ccsr_cpm_mux_t;
1327
1328/* 0x91b20-0xbffff: SI,MCC,etc */
1329typedef struct ccsr_cpm_tmp3 {
1330 char res[58592];
1331} ccsr_cpm_tmp3_t;
1332
1333typedef struct ccsr_cpm_iram {
1334 unsigned long iram[8192];
1335 char res[98304];
1336} ccsr_cpm_iram_t;
1337
1338typedef struct ccsr_cpm {
1339 /* Some references are into the unique and known dpram spaces,
1340 * others are from the generic base.
1341 */
53677ef1
WD		 1342#define im_dprambase im_dpram1
1343 u_char im_dpram1[16*1024];
1344 char res1[16*1024];
1345 u_char im_dpram2[16*1024];
1346 char res2[16*1024];
1347 ccsr_cpm_siu_t im_cpm_siu; /* SIU Configuration */
1348 ccsr_cpm_intctl_t im_cpm_intctl; /* Interrupt Controller */
1349 ccsr_cpm_iop_t im_cpm_iop; /* IO Port control/status */
1350 ccsr_cpm_timer_t im_cpm_timer; /* CPM timers */
1351 ccsr_cpm_sdma_t im_cpm_sdma; /* SDMA control/status */
42d1f039
WD		 1352 ccsr_cpm_fcc1_t im_cpm_fcc1;
1353 ccsr_cpm_fcc2_t im_cpm_fcc2;
1354 ccsr_cpm_fcc3_t im_cpm_fcc3;
1355 ccsr_cpm_fcc1_ext_t im_cpm_fcc1_ext;
1356 ccsr_cpm_fcc2_ext_t im_cpm_fcc2_ext;
1357 ccsr_cpm_fcc3_ext_t im_cpm_fcc3_ext;
1358 ccsr_cpm_tmp1_t im_cpm_tmp1;
1359 ccsr_cpm_brg2_t im_cpm_brg2;
1360 ccsr_cpm_i2c_t im_cpm_i2c;
1361 ccsr_cpm_cp_t im_cpm_cp;
1362 ccsr_cpm_brg1_t im_cpm_brg1;
1363 ccsr_cpm_scc_t im_cpm_scc[4];
1364 ccsr_cpm_tmp2_t im_cpm_tmp2;
1365 ccsr_cpm_spi_t im_cpm_spi;
1366 ccsr_cpm_mux_t im_cpm_mux;
1367 ccsr_cpm_tmp3_t im_cpm_tmp3;
1368 ccsr_cpm_iram_t im_cpm_iram;
1369} ccsr_cpm_t;
1370#endif
42d1f039 1371
de1d0a69
JL		 1372/*
1373 * RapidIO Registers(0xc_0000-0xe_0000)
1374 */
42d1f039
WD		 1375typedef struct ccsr_rio {
1376 uint didcar; /* 0xc0000 - Device Identity Capability Register */
1377 uint dicar; /* 0xc0004 - Device Information Capability Register */
1378 uint aidcar; /* 0xc0008 - Assembly Identity Capability Register */
1379 uint aicar; /* 0xc000c - Assembly Information Capability Register */
1380 uint pefcar; /* 0xc0010 - Processing Element Features Capability Register */
1381 uint spicar; /* 0xc0014 - Switch Port Information Capability Register */
1382 uint socar; /* 0xc0018 - Source Operations Capability Register */
1383 uint docar; /* 0xc001c - Destination Operations Capability Register */
1384 char res1[32];
1385 uint msr; /* 0xc0040 - Mailbox Command And Status Register */
1386 uint pwdcsr; /* 0xc0044 - Port-Write and Doorbell Command And Status Register */
1387 char res2[4];
1388 uint pellccsr; /* 0xc004c - Processing Element Logic Layer Control Command and Status Register */
1389 char res3[12];
1390 uint lcsbacsr; /* 0xc005c - Local Configuration Space Base Address Command and Status Register */
1391 uint bdidcsr; /* 0xc0060 - Base Device ID Command and Status Register */
1392 char res4[4];
1393 uint hbdidlcsr; /* 0xc0068 - Host Base Device ID Lock Command and Status Register */
1394 uint ctcsr; /* 0xc006c - Component Tag Command and Status Register */
1395 char res5[144];
1396 uint pmbh0csr; /* 0xc0100 - 8/16 LP-LVDS Port Maintenance Block Header 0 Command and Status Register */
1397 char res6[28];
1398 uint pltoccsr; /* 0xc0120 - Port Link Time-out Control Command and Status Register */
1399 uint prtoccsr; /* 0xc0124 - Port Response Time-out Control Command and Status Register */
1400 char res7[20];
1401 uint pgccsr; /* 0xc013c - Port General Command and Status Register */
1402 uint plmreqcsr; /* 0xc0140 - Port Link Maintenance Request Command and Status Register */
1403 uint plmrespcsr; /* 0xc0144 - Port Link Maintenance Response Command and Status Register */
1404 uint plascsr; /* 0xc0148 - Port Local Ackid Status Command and Status Register */
1405 char res8[12];
1406 uint pescsr; /* 0xc0158 - Port Error and Status Command and Status Register */
1407 uint pccsr; /* 0xc015c - Port Control Command and Status Register */
1408 char res9[65184];
1409 uint cr; /* 0xd0000 - Port Control Command and Status Register */
1410 char res10[12];
1411 uint pcr; /* 0xd0010 - Port Configuration Register */
1412 uint peir; /* 0xd0014 - Port Error Injection Register */
1413 char res11[3048];
1414 uint rowtar0; /* 0xd0c00 - RapidIO Outbound Window Translation Address Register 0 */
1415 char res12[12];
1416 uint rowar0; /* 0xd0c10 - RapidIO Outbound Attributes Register 0 */
1417 char res13[12];
1418 uint rowtar1; /* 0xd0c20 - RapidIO Outbound Window Translation Address Register 1 */
1419 char res14[4];
1420 uint rowbar1; /* 0xd0c28 - RapidIO Outbound Window Base Address Register 1 */
1421 char res15[4];
1422 uint rowar1; /* 0xd0c30 - RapidIO Outbound Attributes Register 1 */
1423 char res16[12];
1424 uint rowtar2; /* 0xd0c40 - RapidIO Outbound Window Translation Address Register 2 */
1425 char res17[4];
1426 uint rowbar2; /* 0xd0c48 - RapidIO Outbound Window Base Address Register 2 */
1427 char res18[4];
1428 uint rowar2; /* 0xd0c50 - RapidIO Outbound Attributes Register 2 */
1429 char res19[12];
1430 uint rowtar3; /* 0xd0c60 - RapidIO Outbound Window Translation Address Register 3 */
1431 char res20[4];
1432 uint rowbar3; /* 0xd0c68 - RapidIO Outbound Window Base Address Register 3 */
1433 char res21[4];
1434 uint rowar3; /* 0xd0c70 - RapidIO Outbound Attributes Register 3 */
1435 char res22[12];
1436 uint rowtar4; /* 0xd0c80 - RapidIO Outbound Window Translation Address Register 4 */
1437 char res23[4];
1438 uint rowbar4; /* 0xd0c88 - RapidIO Outbound Window Base Address Register 4 */
1439 char res24[4];
1440 uint rowar4; /* 0xd0c90 - RapidIO Outbound Attributes Register 4 */
1441 char res25[12];
1442 uint rowtar5; /* 0xd0ca0 - RapidIO Outbound Window Translation Address Register 5 */
1443 char res26[4];
1444 uint rowbar5; /* 0xd0ca8 - RapidIO Outbound Window Base Address Register 5 */
1445 char res27[4];
1446 uint rowar5; /* 0xd0cb0 - RapidIO Outbound Attributes Register 5 */
1447 char res28[12];
1448 uint rowtar6; /* 0xd0cc0 - RapidIO Outbound Window Translation Address Register 6 */
1449 char res29[4];
1450 uint rowbar6; /* 0xd0cc8 - RapidIO Outbound Window Base Address Register 6 */
1451 char res30[4];
1452 uint rowar6; /* 0xd0cd0 - RapidIO Outbound Attributes Register 6 */
1453 char res31[12];
1454 uint rowtar7; /* 0xd0ce0 - RapidIO Outbound Window Translation Address Register 7 */
1455 char res32[4];
1456 uint rowbar7; /* 0xd0ce8 - RapidIO Outbound Window Base Address Register 7 */
1457 char res33[4];
1458 uint rowar7; /* 0xd0cf0 - RapidIO Outbound Attributes Register 7 */
1459 char res34[12];
1460 uint rowtar8; /* 0xd0d00 - RapidIO Outbound Window Translation Address Register 8 */
1461 char res35[4];
1462 uint rowbar8; /* 0xd0d08 - RapidIO Outbound Window Base Address Register 8 */
1463 char res36[4];
1464 uint rowar8; /* 0xd0d10 - RapidIO Outbound Attributes Register 8 */
1465 char res37[76];
1466 uint riwtar4; /* 0xd0d60 - RapidIO Inbound Window Translation Address Register 4 */
1467 char res38[4];
1468 uint riwbar4; /* 0xd0d68 - RapidIO Inbound Window Base Address Register 4 */
1469 char res39[4];
1470 uint riwar4; /* 0xd0d70 - RapidIO Inbound Attributes Register 4 */
1471 char res40[12];
1472 uint riwtar3; /* 0xd0d80 - RapidIO Inbound Window Translation Address Register 3 */
1473 char res41[4];
1474 uint riwbar3; /* 0xd0d88 - RapidIO Inbound Window Base Address Register 3 */
1475 char res42[4];
1476 uint riwar3; /* 0xd0d90 - RapidIO Inbound Attributes Register 3 */
1477 char res43[12];
1478 uint riwtar2; /* 0xd0da0 - RapidIO Inbound Window Translation Address Register 2 */
1479 char res44[4];
1480 uint riwbar2; /* 0xd0da8 - RapidIO Inbound Window Base Address Register 2 */
1481 char res45[4];
1482 uint riwar2; /* 0xd0db0 - RapidIO Inbound Attributes Register 2 */
1483 char res46[12];
1484 uint riwtar1; /* 0xd0dc0 - RapidIO Inbound Window Translation Address Register 1 */
1485 char res47[4];
1486 uint riwbar1; /* 0xd0dc8 - RapidIO Inbound Window Base Address Register 1 */
1487 char res48[4];
1488 uint riwar1; /* 0xd0dd0 - RapidIO Inbound Attributes Register 1 */
1489 char res49[12];
1490 uint riwtar0; /* 0xd0de0 - RapidIO Inbound Window Translation Address Register 0 */
1491 char res50[12];
1492 uint riwar0; /* 0xd0df0 - RapidIO Inbound Attributes Register 0 */
1493 char res51[12];
1494 uint pnfedr; /* 0xd0e00 - Port Notification/Fatal Error Detect Register */
1495 uint pnfedir; /* 0xd0e04 - Port Notification/Fatal Error Detect Register */
1496 uint pnfeier; /* 0xd0e08 - Port Notification/Fatal Error Interrupt Enable Register */
1497 uint pecr; /* 0xd0e0c - Port Error Control Register */
1498 uint pepcsr0; /* 0xd0e10 - Port Error Packet/Control Symbol Register 0 */
1499 uint pepr1; /* 0xd0e14 - Port Error Packet Register 1 */
1500 uint pepr2; /* 0xd0e18 - Port Error Packet Register 2 */
1501 char res52[4];
1502 uint predr; /* 0xd0e20 - Port Recoverable Error Detect Register */
1503 char res53[4];
1504 uint pertr; /* 0xd0e28 - Port Error Recovery Threshold Register */
1505 uint prtr; /* 0xd0e2c - Port Retry Threshold Register */
1506 char res54[464];
1507 uint omr; /* 0xd1000 - Outbound Mode Register */
1508 uint osr; /* 0xd1004 - Outbound Status Register */
1509 uint eodqtpar; /* 0xd1008 - Extended Outbound Descriptor Queue Tail Pointer Address Register */
1510 uint odqtpar; /* 0xd100c - Outbound Descriptor Queue Tail Pointer Address Register */
1511 uint eosar; /* 0xd1010 - Extended Outbound Unit Source Address Register */
1512 uint osar; /* 0xd1014 - Outbound Unit Source Address Register */
1513 uint odpr; /* 0xd1018 - Outbound Destination Port Register */
1514 uint odatr; /* 0xd101c - Outbound Destination Attributes Register */
1515 uint odcr; /* 0xd1020 - Outbound Doubleword Count Register */
1516 uint eodqhpar; /* 0xd1024 - Extended Outbound Descriptor Queue Head Pointer Address Register */
1517 uint odqhpar; /* 0xd1028 - Outbound Descriptor Queue Head Pointer Address Register */
1518 char res55[52];
1519 uint imr; /* 0xd1060 - Outbound Mode Register */
1520 uint isr; /* 0xd1064 - Inbound Status Register */
1521 uint eidqtpar; /* 0xd1068 - Extended Inbound Descriptor Queue Tail Pointer Address Register */
1522 uint idqtpar; /* 0xd106c - Inbound Descriptor Queue Tail Pointer Address Register */
1523 uint eifqhpar; /* 0xd1070 - Extended Inbound Frame Queue Head Pointer Address Register */
1524 uint ifqhpar; /* 0xd1074 - Inbound Frame Queue Head Pointer Address Register */
1525 char res56[1000];
1526 uint dmr; /* 0xd1460 - Doorbell Mode Register */
1527 uint dsr; /* 0xd1464 - Doorbell Status Register */
1528 uint edqtpar; /* 0xd1468 - Extended Doorbell Queue Tail Pointer Address Register */
1529 uint dqtpar; /* 0xd146c - Doorbell Queue Tail Pointer Address Register */
1530 uint edqhpar; /* 0xd1470 - Extended Doorbell Queue Head Pointer Address Register */
1531 uint dqhpar; /* 0xd1474 - Doorbell Queue Head Pointer Address Register */
1532 char res57[104];
1533 uint pwmr; /* 0xd14e0 - Port-Write Mode Register */
1534 uint pwsr; /* 0xd14e4 - Port-Write Status Register */
1535 uint epwqbar; /* 0xd14e8 - Extended Port-Write Queue Base Address Register */
1536 uint pwqbar; /* 0xd14ec - Port-Write Queue Base Address Register */
1537 char res58[60176];
1538} ccsr_rio_t;
1539
c59e4091
HW		 1540/* Quick Engine Block Pin Muxing Registers (0xe_0100 - 0xe_01bf) */
1541typedef struct par_io {
1542 uint cpodr; /* 0x100 */
1543 uint cpdat; /* 0x104 */
1544 uint cpdir1; /* 0x108 */
1545 uint cpdir2; /* 0x10c */
1546 uint cppar1; /* 0x110 */
1547 uint cppar2; /* 0x114 */
1548 char res[8];
1549}par_io_t;
1550
de1d0a69
JL		 1551/*
1552 * Global Utilities Register Block(0xe_0000-0xf_ffff)
1553 */
42d1f039
WD		 1554typedef struct ccsr_gur {
1555 uint porpllsr; /* 0xe0000 - POR PLL ratio status register */
c0391111
JJ		 1556#ifdef CONFIG_MPC8536
1557#define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000
1558#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25
1559#else
1560#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00
1561#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 9
1562#endif
42d1f039 1563 uint porbmsr; /* 0xe0004 - POR boot mode status register */
53677ef1 1564#define MPC85xx_PORBMSR_HA 0x00070000
42d1f039
WD		 1565 uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */
1566 uint pordevsr; /* 0xe000c - POR I/O device status regsiter */
837f1ba0
ES		 1567#define MPC85xx_PORDEVSR_SGMII1_DIS 0x20000000
1568#define MPC85xx_PORDEVSR_SGMII2_DIS 0x10000000
1569#define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000
1570#define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000
ef50d6c0 1571#define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000
4442f45b 1572#define MPC85xx_PORDEVSR_IO_SEL 0x00780000
53677ef1
WD		 1573#define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000
1574#define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000
1575#define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000
1576#define MPC85xx_PORDEVSR_PCI1_SPD 0x00008000
1577#define MPC85xx_PORDEVSR_PCI2_SPD 0x00004000
837f1ba0 1578#define MPC85xx_PORDEVSR_DRAM_RTYPE 0x00000060
53677ef1 1579#define MPC85xx_PORDEVSR_RIO_CTLS 0x00000008
837f1ba0 1580#define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007
42d1f039 1581 uint pordbgmsr; /* 0xe0010 - POR debug mode status register */
88353a98 1582 uint pordevsr2; /* 0xe0014 - POR I/O device status regsiter 2 */
681c02d0 1583/* The 8544 RM says this is bit 26, but it's really bit 24 */
f7d190b1 1584#define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080
88353a98 1585 char res1[8];
42d1f039
WD		 1586 uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */
1587 char res2[12];
1588 uint gpiocr; /* 0xe0030 - GPIO control register */
1589 char res3[12];
1590 uint gpoutdr; /* 0xe0040 - General-purpose output data register */
1591 char res4[12];
1592 uint gpindr; /* 0xe0050 - General-purpose input data register */
1593 char res5[12];
1594 uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */
1595 char res6[12];
1596 uint devdisr; /* 0xe0070 - Device disable control */
837f1ba0
ES		 1597#define MPC85xx_DEVDISR_PCI1 0x80000000
1598#define MPC85xx_DEVDISR_PCI2 0x40000000
1599#define MPC85xx_DEVDISR_PCIE 0x20000000
1600#define MPC85xx_DEVDISR_LBC 0x08000000
1601#define MPC85xx_DEVDISR_PCIE2 0x04000000
1602#define MPC85xx_DEVDISR_PCIE3 0x02000000
1603#define MPC85xx_DEVDISR_SEC 0x01000000
1604#define MPC85xx_DEVDISR_SRIO 0x00080000
1605#define MPC85xx_DEVDISR_RMSG 0x00040000
53677ef1
WD		 1606#define MPC85xx_DEVDISR_DDR 0x00010000
1607#define MPC85xx_DEVDISR_CPU 0x00008000
1608#define MPC85xx_DEVDISR_CPU0 MPC85xx_DEVDISR_CPU
1609#define MPC85xx_DEVDISR_TB 0x00004000
1610#define MPC85xx_DEVDISR_TB0 MPC85xx_DEVDISR_TB
1611#define MPC85xx_DEVDISR_CPU1 0x00002000
1612#define MPC85xx_DEVDISR_TB1 0x00001000
837f1ba0
ES		 1613#define MPC85xx_DEVDISR_DMA 0x00000400
1614#define MPC85xx_DEVDISR_TSEC1 0x00000080
1615#define MPC85xx_DEVDISR_TSEC2 0x00000040
1616#define MPC85xx_DEVDISR_TSEC3 0x00000020
1617#define MPC85xx_DEVDISR_TSEC4 0x00000010
1618#define MPC85xx_DEVDISR_I2C 0x00000004
1619#define MPC85xx_DEVDISR_DUART 0x00000002
42d1f039
WD		 1620 char res7[12];
1621 uint powmgtcsr; /* 0xe0080 - Power management status and control register */
1622 char res8[12];
1623 uint mcpsumr; /* 0xe0090 - Machine check summary register */
1624 char res9[12];
1625 uint pvr; /* 0xe00a0 - Processor version register */
1626 uint svr; /* 0xe00a4 - System version register */
982efcf2
AF		 1627 char res10a[8];
1628 uint rstcr; /* 0xe00b0 - Reset control register */
b96c83d4 1629#ifdef CONFIG_MPC8568
c59e4091
HW		 1630 char res10b[76];
1631 par_io_t qe_par_io[7]; /* 0xe0100 - 0xe01bf */
1632 char res10c[3136];
1633#else
982efcf2 1634 char res10b[3404];
c59e4091 1635#endif
42d1f039
WD		 1636 uint clkocr; /* 0xe0e00 - Clock out select register */
1637 char res11[12];
1638 uint ddrdllcr; /* 0xe0e10 - DDR DLL control register */
1639 char res12[12];
1640 uint lbcdllcr; /* 0xe0e20 - LBC DLL control register */
d9b94f28
JL		 1641 char res13[248];
1642 uint lbiuiplldcr0; /* 0xe0f1c -- LBIU PLL Debug Reg 0 */
1643 uint lbiuiplldcr1; /* 0xe0f20 -- LBIU PLL Debug Reg 1 */
1644 uint ddrioovcr; /* 0xe0f24 - DDR IO Override Control */
1645 uint res14; /* 0xe0f28 */
1646 uint tsec34ioovcr; /* 0xe0f2c - eTSEC 3/4 IO override control */
837f1ba0 1647 char res15[61648]; /* 0xe0f30 to 0xefffff */
42d1f039
WD		 1648} ccsr_gur_t;
1649
97074ed9
MM		 1650#define PORDEVSR_PCI (0x00800000) /* PCI Mode */
1651
6d0f6bcf
JCPV		 1652#define CONFIG_SYS_MPC85xx_GUTS_OFFSET (0xE0000)
1653#define CONFIG_SYS_MPC85xx_GUTS_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET)
1654#define CONFIG_SYS_MPC85xx_ECM_OFFSET (0x0000)
1655#define CONFIG_SYS_MPC85xx_ECM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET)
1656#define CONFIG_SYS_MPC85xx_DDR_OFFSET (0x2000)
1657#define CONFIG_SYS_MPC85xx_DDR_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR_OFFSET)
1658#define CONFIG_SYS_MPC85xx_DDR2_OFFSET (0x6000)
1659#define CONFIG_SYS_MPC85xx_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR2_OFFSET)
1660#define CONFIG_SYS_MPC85xx_LBC_OFFSET (0x5000)
1661#define CONFIG_SYS_MPC85xx_LBC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET)
1662#define CONFIG_SYS_MPC85xx_PCIX_OFFSET (0x8000)
1663#define CONFIG_SYS_MPC85xx_PCIX_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET)
1664#define CONFIG_SYS_MPC85xx_PCIX2_OFFSET (0x9000)
1665#define CONFIG_SYS_MPC85xx_PCIX2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET)
1666#define CONFIG_SYS_MPC85xx_SATA1_OFFSET (0x18000)
1667#define CONFIG_SYS_MPC85xx_SATA1_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET)
1668#define CONFIG_SYS_MPC85xx_SATA2_OFFSET (0x19000)
1669#define CONFIG_SYS_MPC85xx_SATA2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA2_OFFSET)
1670#define CONFIG_SYS_MPC85xx_L2_OFFSET (0x20000)
1671#define CONFIG_SYS_MPC85xx_L2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_L2_OFFSET)
1672#define CONFIG_SYS_MPC85xx_DMA_OFFSET (0x21000)
1673#define CONFIG_SYS_MPC85xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET)
1674#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET (0x2e000)
1675#define CONFIG_SYS_MPC85xx_ESDHC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET)
1676#define CONFIG_SYS_MPC85xx_PIC_OFFSET (0x40000)
1677#define CONFIG_SYS_MPC85xx_PIC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET)
1678#define CONFIG_SYS_MPC85xx_CPM_OFFSET (0x80000)
1679#define CONFIG_SYS_MPC85xx_CPM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET)
1680#define CONFIG_SYS_MPC85xx_SERDES1_OFFSET (0xE3000)
1681#define CONFIG_SYS_MPC85xx_SERDES1_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
1682#define CONFIG_SYS_MPC85xx_SERDES2_OFFSET (0xE3100)
1683#define CONFIG_SYS_MPC85xx_SERDES2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
aafeefbd 1684
42d1f039 1685#endif /*__IMMAP_85xx__*/
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