[people/ms/u-boot.git] / include / asm-ppc / mmu.h

/*
 * PowerPC memory management structures
 */

#ifndef _PPC_MMU_H_
#define _PPC_MMU_H_

#include <linux/config.h>

#ifndef __ASSEMBLY__
/* Hardware Page Table Entry */
typedef struct _PTE {
#ifdef CONFIG_PPC64BRIDGE
	unsigned long long vsid:52;
	unsigned long api:5;
	unsigned long :5;
	unsigned long h:1;
	unsigned long v:1;
	unsigned long long rpn:52;
#else /* CONFIG_PPC64BRIDGE */
	unsigned long v:1;	/* Entry is valid */
	unsigned long vsid:24;	/* Virtual segment identifier */
	unsigned long h:1;	/* Hash algorithm indicator */
	unsigned long api:6;	/* Abbreviated page index */
	unsigned long rpn:20;	/* Real (physical) page number */
#endif /* CONFIG_PPC64BRIDGE */
	unsigned long    :3;	/* Unused */
	unsigned long r:1;	/* Referenced */
	unsigned long c:1;	/* Changed */
	unsigned long w:1;	/* Write-thru cache mode */
	unsigned long i:1;	/* Cache inhibited */
	unsigned long m:1;	/* Memory coherence */
	unsigned long g:1;	/* Guarded */
	unsigned long  :1;	/* Unused */
	unsigned long pp:2;	/* Page protection */
} PTE;

/* Values for PP (assumes Ks=0, Kp=1) */
#define PP_RWXX	0	/* Supervisor read/write, User none */
#define PP_RWRX 1	/* Supervisor read/write, User read */
#define PP_RWRW 2	/* Supervisor read/write, User read/write */
#define PP_RXRX 3	/* Supervisor read,       User read */

/* Segment Register */
typedef struct _SEGREG {
	unsigned long t:1;	/* Normal or I/O  type */
	unsigned long ks:1;	/* Supervisor 'key' (normally 0) */
	unsigned long kp:1;	/* User 'key' (normally 1) */
	unsigned long n:1;	/* No-execute */
	unsigned long :4;	/* Unused */
	unsigned long vsid:24;	/* Virtual Segment Identifier */
} SEGREG;

/* Block Address Translation (BAT) Registers */
typedef struct _P601_BATU {	/* Upper part of BAT for 601 processor */
	unsigned long bepi:15;	/* Effective page index (virtual address) */
	unsigned long :8;	/* unused */
	unsigned long w:1;
	unsigned long i:1;	/* Cache inhibit */
	unsigned long m:1;	/* Memory coherence */
	unsigned long ks:1;	/* Supervisor key (normally 0) */
	unsigned long kp:1;	/* User key (normally 1) */
	unsigned long pp:2;	/* Page access protections */
} P601_BATU;

typedef struct _BATU {		/* Upper part of BAT (all except 601) */
#ifdef CONFIG_PPC64BRIDGE
	unsigned long long bepi:47;
#else /* CONFIG_PPC64BRIDGE */
	unsigned long bepi:15;	/* Effective page index (virtual address) */
#endif /* CONFIG_PPC64BRIDGE */
	unsigned long :4;	/* Unused */
	unsigned long bl:11;	/* Block size mask */
	unsigned long vs:1;	/* Supervisor valid */
	unsigned long vp:1;	/* User valid */
} BATU;

typedef struct _P601_BATL {	/* Lower part of BAT for 601 processor */
	unsigned long brpn:15;	/* Real page index (physical address) */
	unsigned long :10;	/* Unused */
	unsigned long v:1;	/* Valid bit */
	unsigned long bl:6;	/* Block size mask */
} P601_BATL;

typedef struct _BATL {		/* Lower part of BAT (all except 601) */
#ifdef CONFIG_PPC64BRIDGE
	unsigned long long brpn:47;
#else /* CONFIG_PPC64BRIDGE */
	unsigned long brpn:15;	/* Real page index (physical address) */
#endif /* CONFIG_PPC64BRIDGE */
	unsigned long :10;	/* Unused */
	unsigned long w:1;	/* Write-thru cache */
	unsigned long i:1;	/* Cache inhibit */
	unsigned long m:1;	/* Memory coherence */
	unsigned long g:1;	/* Guarded (MBZ in IBAT) */
	unsigned long :1;	/* Unused */
	unsigned long pp:2;	/* Page access protections */
} BATL;

typedef struct _BAT {
	BATU batu;		/* Upper register */
	BATL batl;		/* Lower register */
} BAT;

typedef struct _P601_BAT {
	P601_BATU batu;		/* Upper register */
	P601_BATL batl;		/* Lower register */
} P601_BAT;

/*
 * Simulated two-level MMU.  This structure is used by the kernel
 * to keep track of MMU mappings and is used to update/maintain
 * the hardware HASH table which is really a cache of mappings.
 *
 * The simulated structures mimic the hardware available on other
 * platforms, notably the 80x86 and 680x0.
 */

typedef struct _pte {
   	unsigned long page_num:20;
   	unsigned long flags:12;		/* Page flags (some unused bits) */
} pte;

#define PD_SHIFT (10+12)		/* Page directory */
#define PD_MASK  0x02FF
#define PT_SHIFT (12)			/* Page Table */
#define PT_MASK  0x02FF
#define PG_SHIFT (12)			/* Page Entry */


/* MMU context */

typedef struct _MMU_context {
	SEGREG	segs[16];	/* Segment registers */
	pte	**pmap;		/* Two-level page-map structure */
} MMU_context;

extern void _tlbie(unsigned long va);	/* invalidate a TLB entry */
extern void _tlbia(void);		/* invalidate all TLB entries */

typedef enum {
	IBAT0 = 0, IBAT1, IBAT2, IBAT3,
	DBAT0, DBAT1, DBAT2, DBAT3
} ppc_bat_t;

extern int read_bat(ppc_bat_t bat, unsigned long *upper, unsigned long *lower);
extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);

#endif /* __ASSEMBLY__ */

/* Block size masks */
#define BL_128K	0x000
#define BL_256K 0x001
#define BL_512K 0x003
#define BL_1M   0x007
#define BL_2M   0x00F
#define BL_4M   0x01F
#define BL_8M   0x03F
#define BL_16M  0x07F
#define BL_32M  0x0FF
#define BL_64M  0x1FF
#define BL_128M 0x3FF
#define BL_256M 0x7FF

/* BAT Access Protection */
#define BPP_XX	0x00		/* No access */
#define BPP_RX	0x01		/* Read only */
#define BPP_RW	0x02		/* Read/write */

/* Used to set up SDR1 register */
#define HASH_TABLE_SIZE_64K	0x00010000
#define HASH_TABLE_SIZE_128K	0x00020000
#define HASH_TABLE_SIZE_256K	0x00040000
#define HASH_TABLE_SIZE_512K	0x00080000
#define HASH_TABLE_SIZE_1M	0x00100000
#define HASH_TABLE_SIZE_2M	0x00200000
#define HASH_TABLE_SIZE_4M	0x00400000
#define HASH_TABLE_MASK_64K	0x000
#define HASH_TABLE_MASK_128K	0x001
#define HASH_TABLE_MASK_256K	0x003
#define HASH_TABLE_MASK_512K	0x007
#define HASH_TABLE_MASK_1M	0x00F
#define HASH_TABLE_MASK_2M	0x01F
#define HASH_TABLE_MASK_4M	0x03F

/* Control/status registers for the MPC8xx.
 * A write operation to these registers causes serialized access.
 * During software tablewalk, the registers used perform mask/shift-add
 * operations when written/read.  A TLB entry is created when the Mx_RPN
 * is written, and the contents of several registers are used to
 * create the entry.
 */
#define MI_CTR		784	/* Instruction TLB control register */
#define MI_GPM		0x80000000	/* Set domain manager mode */
#define MI_PPM		0x40000000	/* Set subpage protection */
#define MI_CIDEF	0x20000000	/* Set cache inhibit when MMU dis */
#define MI_RSV4I	0x08000000	/* Reserve 4 TLB entries */
#define MI_PPCS		0x02000000	/* Use MI_RPN prob/priv state */
#define MI_IDXMASK	0x00001f00	/* TLB index to be loaded */
#define MI_RESETVAL	0x00000000	/* Value of register at reset */

/* These are the Ks and Kp from the PowerPC books.  For proper operation,
 * Ks = 0, Kp = 1.
 */
#define MI_AP		786
#define MI_Ks		0x80000000	/* Should not be set */
#define MI_Kp		0x40000000	/* Should always be set */

/* The effective page number register.  When read, contains the information
 * about the last instruction TLB miss.  When MI_RPN is written, bits in
 * this register are used to create the TLB entry.
 */
#define MI_EPN		787
#define MI_EPNMASK	0xfffff000	/* Effective page number for entry */
#define MI_EVALID	0x00000200	/* Entry is valid */
#define MI_ASIDMASK	0x0000000f	/* ASID match value */
					/* Reset value is undefined */

/* A "level 1" or "segment" or whatever you want to call it register.
 * For the instruction TLB, it contains bits that get loaded into the
 * TLB entry when the MI_RPN is written.
 */
#define MI_TWC		789
#define MI_APG		0x000001e0	/* Access protection group (0) */
#define MI_GUARDED	0x00000010	/* Guarded storage */
#define MI_PSMASK	0x0000000c	/* Mask of page size bits */
#define MI_PS8MEG	0x0000000c	/* 8M page size */
#define MI_PS512K	0x00000004	/* 512K page size */
#define MI_PS4K_16K	0x00000000	/* 4K or 16K page size */
#define MI_SVALID	0x00000001	/* Segment entry is valid */
					/* Reset value is undefined */

/* Real page number.  Defined by the pte.  Writing this register
 * causes a TLB entry to be created for the instruction TLB, using
 * additional information from the MI_EPN, and MI_TWC registers.
 */
#define MI_RPN		790

/* Define an RPN value for mapping kernel memory to large virtual
 * pages for boot initialization.  This has real page number of 0,
 * large page size, shared page, cache enabled, and valid.
 * Also mark all subpages valid and write access.
 */
#define MI_BOOTINIT	0x000001fd

#define MD_CTR		792	/* Data TLB control register */
#define MD_GPM		0x80000000	/* Set domain manager mode */
#define MD_PPM		0x40000000	/* Set subpage protection */
#define MD_CIDEF	0x20000000	/* Set cache inhibit when MMU dis */
#define MD_WTDEF	0x10000000	/* Set writethrough when MMU dis */
#define MD_RSV4I	0x08000000	/* Reserve 4 TLB entries */
#define MD_TWAM		0x04000000	/* Use 4K page hardware assist */
#define MD_PPCS		0x02000000	/* Use MI_RPN prob/priv state */
#define MD_IDXMASK	0x00001f00	/* TLB index to be loaded */
#define MD_RESETVAL	0x04000000	/* Value of register at reset */

#define M_CASID		793	/* Address space ID (context) to match */
#define MC_ASIDMASK	0x0000000f	/* Bits used for ASID value */


/* These are the Ks and Kp from the PowerPC books.  For proper operation,
 * Ks = 0, Kp = 1.
 */
#define MD_AP		794
#define MD_Ks		0x80000000	/* Should not be set */
#define MD_Kp		0x40000000	/* Should always be set */

/* The effective page number register.  When read, contains the information
 * about the last instruction TLB miss.  When MD_RPN is written, bits in
 * this register are used to create the TLB entry.
 */
#define MD_EPN		795
#define MD_EPNMASK	0xfffff000	/* Effective page number for entry */
#define MD_EVALID	0x00000200	/* Entry is valid */
#define MD_ASIDMASK	0x0000000f	/* ASID match value */
					/* Reset value is undefined */

/* The pointer to the base address of the first level page table.
 * During a software tablewalk, reading this register provides the address
 * of the entry associated with MD_EPN.
 */
#define M_TWB		796
#define	M_L1TB		0xfffff000	/* Level 1 table base address */
#define M_L1INDX	0x00000ffc	/* Level 1 index, when read */
					/* Reset value is undefined */

/* A "level 1" or "segment" or whatever you want to call it register.
 * For the data TLB, it contains bits that get loaded into the TLB entry
 * when the MD_RPN is written.  It is also provides the hardware assist
 * for finding the PTE address during software tablewalk.
 */
#define MD_TWC		797
#define MD_L2TB		0xfffff000	/* Level 2 table base address */
#define MD_L2INDX	0xfffffe00	/* Level 2 index (*pte), when read */
#define MD_APG		0x000001e0	/* Access protection group (0) */
#define MD_GUARDED	0x00000010	/* Guarded storage */
#define MD_PSMASK	0x0000000c	/* Mask of page size bits */
#define MD_PS8MEG	0x0000000c	/* 8M page size */
#define MD_PS512K	0x00000004	/* 512K page size */
#define MD_PS4K_16K	0x00000000	/* 4K or 16K page size */
#define MD_WT		0x00000002	/* Use writethrough page attribute */
#define MD_SVALID	0x00000001	/* Segment entry is valid */
					/* Reset value is undefined */


/* Real page number.  Defined by the pte.  Writing this register
 * causes a TLB entry to be created for the data TLB, using
 * additional information from the MD_EPN, and MD_TWC registers.
 */
#define MD_RPN		798

/* This is a temporary storage register that could be used to save
 * a processor working register during a tablewalk.
 */
#define M_TW		799

/*
 * At present, all PowerPC 400-class processors share a similar TLB
 * architecture. The instruction and data sides share a unified,
 * 64-entry, fully-associative TLB which is maintained totally under
 * software control. In addition, the instruction side has a
 * hardware-managed, 4-entry, fully- associative TLB which serves as a
 * first level to the shared TLB. These two TLBs are known as the UTLB
 * and ITLB, respectively.
 */

#define        PPC4XX_TLB_SIZE 64

/*
 * TLB entries are defined by a "high" tag portion and a "low" data
 * portion.  On all architectures, the data portion is 32-bits.
 *
 * TLB entries are managed entirely under software control by reading,
 * writing, and searchoing using the 4xx-specific tlbre, tlbwr, and tlbsx
 * instructions.
 */

#define	TLB_LO          1
#define	TLB_HI          0

#define	TLB_DATA        TLB_LO
#define	TLB_TAG         TLB_HI

/* Tag portion */

#define TLB_EPN_MASK    0xFFFFFC00      /* Effective Page Number */
#define TLB_PAGESZ_MASK 0x00000380
#define TLB_PAGESZ(x)   (((x) & 0x7) << 7)
#define   PAGESZ_1K		0
#define   PAGESZ_4K             1
#define   PAGESZ_16K            2
#define   PAGESZ_64K            3
#define   PAGESZ_256K           4
#define   PAGESZ_1M             5
#define   PAGESZ_4M             6
#define   PAGESZ_16M            7
#define TLB_VALID       0x00000040      /* Entry is valid */

/* Data portion */

#define TLB_RPN_MASK    0xFFFFFC00      /* Real Page Number */
#define TLB_PERM_MASK   0x00000300
#define TLB_EX          0x00000200      /* Instruction execution allowed */
#define TLB_WR          0x00000100      /* Writes permitted */
#define TLB_ZSEL_MASK   0x000000F0
#define TLB_ZSEL(x)     (((x) & 0xF) << 4)
#define TLB_ATTR_MASK   0x0000000F
#define TLB_W           0x00000008      /* Caching is write-through */
#define TLB_I           0x00000004      /* Caching is inhibited */
#define TLB_M           0x00000002      /* Memory is coherent */
#define TLB_G           0x00000001      /* Memory is guarded from prefetch */

/*
 * e500 support
 */

#define MAS0_TLBSEL     0x10000000
#define MAS0_ESEL       0x000F0000
#define MAS0_NV         0x00000001

#define MAS1_VALID      0x80000000
#define MAS1_IPROT      0x40000000
#define MAS1_TID        0x00FF0000
#define MAS1_TS         0x00001000
#define MAS1_TSIZE   	0x00000F00

#define MAS2_EPN        0xFFFFF000
#define MAS2_SHAREN     0x00000200
#define MAS2_X0         0x00000040
#define MAS2_X1         0x00000020
#define MAS2_W          0x00000010
#define MAS2_I          0x00000008
#define MAS2_M          0x00000004
#define MAS2_G          0x00000002
#define MAS2_E          0x00000001

#define MAS3_RPN        0xFFFFF000
#define MAS3_U0         0x00000200
#define MAS3_U1         0x00000100
#define MAS3_U2         0x00000080
#define MAS3_U3         0x00000040
#define MAS3_UX         0x00000020
#define MAS3_SX         0x00000010
#define MAS3_UW         0x00000008
#define MAS3_SW         0x00000004
#define MAS3_UR         0x00000002
#define MAS3_SR         0x00000001

#define MAS4_TLBSELD    0x10000000
#define MAS4_TIDDSEL    0x00030000
#define MAS4_DSHAREN    0x00001000
#define MAS4_TSIZED(x)  (x << 8)
#define MAS4_X0D        0x00000040
#define MAS4_X1D        0x00000020
#define MAS4_WD         0x00000010
#define MAS4_ID         0x00000008
#define MAS4_MD         0x00000004
#define MAS4_GD         0x00000002
#define MAS4_ED         0x00000001

#define MAS6_SPID       0x00FF0000
#define MAS6_SAS        0x00000001

#define BOOKE_PAGESZ_1K         0
#define BOOKE_PAGESZ_4K         1
#define BOOKE_PAGESZ_16K        2
#define BOOKE_PAGESZ_64K        3
#define BOOKE_PAGESZ_256K       4
#define BOOKE_PAGESZ_1M         5
#define BOOKE_PAGESZ_4M         6
#define BOOKE_PAGESZ_16M        7
#define BOOKE_PAGESZ_64M        8
#define BOOKE_PAGESZ_256M       9
#define BOOKE_PAGESZ_1GB        10
#define BOOKE_PAGESZ_4GB        11

#if defined(CONFIG_MPC86xx)
#define LAWBAR_BASE_ADDR	0x00FFFFFF
#define LAWAR_TRGT_IF		0x01F00000
#else
#define LAWBAR_BASE_ADDR	0x000FFFFF
#define LAWAR_TRGT_IF		0x00F00000
#endif
#define LAWAR_EN		0x80000000
#define LAWAR_SIZE		0x0000003F

#define LAWAR_TRGT_IF_PCI	0x00000000
#define LAWAR_TRGT_IF_PCI1	0x00000000
#define LAWAR_TRGT_IF_PCIX	0x00000000
#define LAWAR_TRGT_IF_PCI2	0x00100000
#define LAWAR_TRGT_IF_HT	0x00200000
#define LAWAR_TRGT_IF_LBC	0x00400000
#define LAWAR_TRGT_IF_CCSR	0x00800000
#define LAWAR_TRGT_IF_DDR_INTERLEAVED 0x00B00000
#define LAWAR_TRGT_IF_RIO	0x00c00000
#define LAWAR_TRGT_IF_DDR	0x00f00000
#define LAWAR_TRGT_IF_DDR1	0x00f00000
#define LAWAR_TRGT_IF_DDR2	0x01600000

#define LAWAR_SIZE_BASE		0xa
#define LAWAR_SIZE_4K		(LAWAR_SIZE_BASE+1)
#define LAWAR_SIZE_8K		(LAWAR_SIZE_BASE+2)
#define LAWAR_SIZE_16K		(LAWAR_SIZE_BASE+3)
#define LAWAR_SIZE_32K		(LAWAR_SIZE_BASE+4)
#define LAWAR_SIZE_64K		(LAWAR_SIZE_BASE+5)
#define LAWAR_SIZE_128K		(LAWAR_SIZE_BASE+6)
#define LAWAR_SIZE_256K		(LAWAR_SIZE_BASE+7)
#define LAWAR_SIZE_512K		(LAWAR_SIZE_BASE+8)
#define LAWAR_SIZE_1M		(LAWAR_SIZE_BASE+9)
#define LAWAR_SIZE_2M		(LAWAR_SIZE_BASE+10)
#define LAWAR_SIZE_4M		(LAWAR_SIZE_BASE+11)
#define LAWAR_SIZE_8M		(LAWAR_SIZE_BASE+12)
#define LAWAR_SIZE_16M		(LAWAR_SIZE_BASE+13)
#define LAWAR_SIZE_32M		(LAWAR_SIZE_BASE+14)
#define LAWAR_SIZE_64M		(LAWAR_SIZE_BASE+15)
#define LAWAR_SIZE_128M		(LAWAR_SIZE_BASE+16)
#define LAWAR_SIZE_256M		(LAWAR_SIZE_BASE+17)
#define LAWAR_SIZE_512M		(LAWAR_SIZE_BASE+18)
#define LAWAR_SIZE_1G		(LAWAR_SIZE_BASE+19)
#define LAWAR_SIZE_2G		(LAWAR_SIZE_BASE+20)
#define LAWAR_SIZE_4G		(LAWAR_SIZE_BASE+21)
#define LAWAR_SIZE_8G		(LAWAR_SIZE_BASE+22)
#define LAWAR_SIZE_16G		(LAWAR_SIZE_BASE+23)
#define LAWAR_SIZE_32G		(LAWAR_SIZE_BASE+24)

#ifdef CONFIG_440SPE
/*----------------------------------------------------------------------------+
| Following instructions are not available in Book E mode of the GNU assembler.
+----------------------------------------------------------------------------*/
#define DCCCI(ra,rb)			.long 0x7c000000|\
					(ra<<16)|(rb<<11)|(454<<1)

#define ICCCI(ra,rb)			.long 0x7c000000|\
					(ra<<16)|(rb<<11)|(966<<1)

#define DCREAD(rt,ra,rb)		.long 0x7c000000|\
					(rt<<21)|(ra<<16)|(rb<<11)|(486<<1)

#define ICREAD(ra,rb)			.long 0x7c000000|\
					(ra<<16)|(rb<<11)|(998<<1)

#define TLBSX(rt,ra,rb)			.long 0x7c000000|\
					(rt<<21)|(ra<<16)|(rb<<11)|(914<<1)

#define TLBWE(rs,ra,ws)			.long 0x7c000000|\
					(rs<<21)|(ra<<16)|(ws<<11)|(978<<1)

#define TLBRE(rt,ra,ws)			.long 0x7c000000|\
					(rt<<21)|(ra<<16)|(ws<<11)|(946<<1)

#define TLBSXDOT(rt,ra,rb)		.long 0x7c000001|\
					(rt<<21)|(ra<<16)|(rb<<11)|(914<<1)

#define MSYNC				.long 0x7c000000|\
					(598<<1)

#define MBAR_INST 				.long 0x7c000000|\
					(854<<1)

/*----------------------------------------------------------------------------+
| Following instruction is not available in PPC405 mode of the GNU assembler.
+----------------------------------------------------------------------------*/
#define TLBRE(rt,ra,ws)			.long 0x7c000000|\
					(rt<<21)|(ra<<16)|(ws<<11)|(946<<1)

#endif
#endif /* _PPC_MMU_H_ */
Commit	Line	Data
3b759bd6 WD	1	/*
	2	* PowerPC memory management structures
	3	*/
	4
	5	#ifndef _PPC_MMU_H_
	6	#define _PPC_MMU_H_
	7
	8	#include <linux/config.h>
	9
	10	#ifndef __ASSEMBLY__
	11	/* Hardware Page Table Entry */
	12	typedef struct _PTE {
	13	#ifdef CONFIG_PPC64BRIDGE
	14	unsigned long long vsid:52;
	15	unsigned long api:5;
	16	unsigned long :5;
	17	unsigned long h:1;
	18	unsigned long v:1;
	19	unsigned long long rpn:52;
	20	#else /* CONFIG_PPC64BRIDGE */
	21	unsigned long v:1; /* Entry is valid */
	22	unsigned long vsid:24; /* Virtual segment identifier */
	23	unsigned long h:1; /* Hash algorithm indicator */
	24	unsigned long api:6; /* Abbreviated page index */
	25	unsigned long rpn:20; /* Real (physical) page number */
	26	#endif /* CONFIG_PPC64BRIDGE */
	27	unsigned long :3; /* Unused */
	28	unsigned long r:1; /* Referenced */
	29	unsigned long c:1; /* Changed */
	30	unsigned long w:1; /* Write-thru cache mode */
	31	unsigned long i:1; /* Cache inhibited */
	32	unsigned long m:1; /* Memory coherence */
	33	unsigned long g:1; /* Guarded */
	34	unsigned long :1; /* Unused */
	35	unsigned long pp:2; /* Page protection */
	36	} PTE;
	37
	38	/* Values for PP (assumes Ks=0, Kp=1) */
	39	#define PP_RWXX 0 /* Supervisor read/write, User none */
	40	#define PP_RWRX 1 /* Supervisor read/write, User read */
	41	#define PP_RWRW 2 /* Supervisor read/write, User read/write */
	42	#define PP_RXRX 3 /* Supervisor read, User read */
	43
	44	/* Segment Register */
	45	typedef struct _SEGREG {
	46	unsigned long t:1; /* Normal or I/O type */
	47	unsigned long ks:1; /* Supervisor 'key' (normally 0) */
	48	unsigned long kp:1; /* User 'key' (normally 1) */
	49	unsigned long n:1; /* No-execute */
	50	unsigned long :4; /* Unused */
	51	unsigned long vsid:24; /* Virtual Segment Identifier */
	52	} SEGREG;
	53
	54	/* Block Address Translation (BAT) Registers */
	55	typedef struct _P601_BATU { /* Upper part of BAT for 601 processor */
	56	unsigned long bepi:15; /* Effective page index (virtual address) */
	57	unsigned long :8; /* unused */
	58	unsigned long w:1;
	59	unsigned long i:1; /* Cache inhibit */
	60	unsigned long m:1; /* Memory coherence */
	61	unsigned long ks:1; /* Supervisor key (normally 0) */
	62	unsigned long kp:1; /* User key (normally 1) */
	63	unsigned long pp:2; /* Page access protections */
	64	} P601_BATU;
65
66	typedef struct _BATU { /* Upper part of BAT (all except 601) */
67	#ifdef CONFIG_PPC64BRIDGE
68	unsigned long long bepi:47;
69	#else /* CONFIG_PPC64BRIDGE */
70	unsigned long bepi:15; /* Effective page index (virtual address) */
71	#endif /* CONFIG_PPC64BRIDGE */
72	unsigned long :4; /* Unused */
73	unsigned long bl:11; /* Block size mask */
74	unsigned long vs:1; /* Supervisor valid */
75	unsigned long vp:1; /* User valid */
76	} BATU;
77
78	typedef struct _P601_BATL { /* Lower part of BAT for 601 processor */
79	unsigned long brpn:15; /* Real page index (physical address) */
80	unsigned long :10; /* Unused */
81	unsigned long v:1; /* Valid bit */
82	unsigned long bl:6; /* Block size mask */
83	} P601_BATL;
84
85	typedef struct _BATL { /* Lower part of BAT (all except 601) */
86	#ifdef CONFIG_PPC64BRIDGE
87	unsigned long long brpn:47;
88	#else /* CONFIG_PPC64BRIDGE */
89	unsigned long brpn:15; /* Real page index (physical address) */
90	#endif /* CONFIG_PPC64BRIDGE */
91	unsigned long :10; /* Unused */
92	unsigned long w:1; /* Write-thru cache */
93	unsigned long i:1; /* Cache inhibit */
94	unsigned long m:1; /* Memory coherence */
95	unsigned long g:1; /* Guarded (MBZ in IBAT) */
96	unsigned long :1; /* Unused */
97	unsigned long pp:2; /* Page access protections */
98	} BATL;
99
100	typedef struct _BAT {
101	BATU batu; /* Upper register */
102	BATL batl; /* Lower register */
103	} BAT;
104
105	typedef struct _P601_BAT {
106	P601_BATU batu; /* Upper register */
107	P601_BATL batl; /* Lower register */
108	} P601_BAT;
109
110	/*
111	* Simulated two-level MMU. This structure is used by the kernel
112	* to keep track of MMU mappings and is used to update/maintain
113	* the hardware HASH table which is really a cache of mappings.
114	*
115	* The simulated structures mimic the hardware available on other
116	* platforms, notably the 80x86 and 680x0.
117	*/
118
119	typedef struct _pte {
120	unsigned long page_num:20;
121	unsigned long flags:12; /* Page flags (some unused bits) */
122	} pte;
123
124	#define PD_SHIFT (10+12) /* Page directory */
125	#define PD_MASK 0x02FF
126	#define PT_SHIFT (12) /* Page Table */
127	#define PT_MASK 0x02FF
128	#define PG_SHIFT (12) /* Page Entry */
129
130
131	/* MMU context */
132
133	typedef struct _MMU_context {
134	SEGREG segs[16]; /* Segment registers */
135	pte *pmap; / Two-level page-map structure */
136	} MMU_context;
137
138	extern void _tlbie(unsigned long va); /* invalidate a TLB entry */
139	extern void _tlbia(void); /* invalidate all TLB entries */
140
141	typedef enum {
142	IBAT0 = 0, IBAT1, IBAT2, IBAT3,
143	DBAT0, DBAT1, DBAT2, DBAT3
144	} ppc_bat_t;
145
146	extern int read_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);
147	extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);
148
149	#endif /* __ASSEMBLY__ */
150
151	/* Block size masks */
152	#define BL_128K 0x000
153	#define BL_256K 0x001
154	#define BL_512K 0x003
155	#define BL_1M 0x007
156	#define BL_2M 0x00F
157	#define BL_4M 0x01F
158	#define BL_8M 0x03F
159	#define BL_16M 0x07F
160	#define BL_32M 0x0FF
161	#define BL_64M 0x1FF
162	#define BL_128M 0x3FF
163	#define BL_256M 0x7FF
164
165	/* BAT Access Protection */
166	#define BPP_XX 0x00 /* No access */
167	#define BPP_RX 0x01 /* Read only */
168	#define BPP_RW 0x02 /* Read/write */
169
170	/* Used to set up SDR1 register */
171	#define HASH_TABLE_SIZE_64K 0x00010000
172	#define HASH_TABLE_SIZE_128K 0x00020000
173	#define HASH_TABLE_SIZE_256K 0x00040000
174	#define HASH_TABLE_SIZE_512K 0x00080000
175	#define HASH_TABLE_SIZE_1M 0x00100000
176	#define HASH_TABLE_SIZE_2M 0x00200000
177	#define HASH_TABLE_SIZE_4M 0x00400000
178	#define HASH_TABLE_MASK_64K 0x000
179	#define HASH_TABLE_MASK_128K 0x001
180	#define HASH_TABLE_MASK_256K 0x003
181	#define HASH_TABLE_MASK_512K 0x007
182	#define HASH_TABLE_MASK_1M 0x00F
183	#define HASH_TABLE_MASK_2M 0x01F
184	#define HASH_TABLE_MASK_4M 0x03F
185
186	/* Control/status registers for the MPC8xx.
187	* A write operation to these registers causes serialized access.
188	* During software tablewalk, the registers used perform mask/shift-add
189	* operations when written/read. A TLB entry is created when the Mx_RPN
190	* is written, and the contents of several registers are used to
191	* create the entry.
192	*/
193	#define MI_CTR 784 /* Instruction TLB control register */
194	#define MI_GPM 0x80000000 /* Set domain manager mode */
195	#define MI_PPM 0x40000000 /* Set subpage protection */
196	#define MI_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */
197	#define MI_RSV4I 0x08000000 /* Reserve 4 TLB entries */
198	#define MI_PPCS 0x02000000 /* Use MI_RPN prob/priv state */
199	#define MI_IDXMASK 0x00001f00 /* TLB index to be loaded */
200	#define MI_RESETVAL 0x00000000 /* Value of register at reset */
201
202	/* These are the Ks and Kp from the PowerPC books. For proper operation,
203	* Ks = 0, Kp = 1.
204	*/
205	#define MI_AP 786
206	#define MI_Ks 0x80000000 /* Should not be set */
207	#define MI_Kp 0x40000000 /* Should always be set */
208
209	/* The effective page number register. When read, contains the information
210	* about the last instruction TLB miss. When MI_RPN is written, bits in
211	* this register are used to create the TLB entry.
212	*/
213	#define MI_EPN 787
214	#define MI_EPNMASK 0xfffff000 /* Effective page number for entry */
215	#define MI_EVALID 0x00000200 /* Entry is valid */
216	#define MI_ASIDMASK 0x0000000f /* ASID match value */
217	/* Reset value is undefined */
218
219	/* A "level 1" or "segment" or whatever you want to call it register.
220	* For the instruction TLB, it contains bits that get loaded into the
221	* TLB entry when the MI_RPN is written.
222	*/
223	#define MI_TWC 789
224	#define MI_APG 0x000001e0 /* Access protection group (0) */
225	#define MI_GUARDED 0x00000010 /* Guarded storage */
226	#define MI_PSMASK 0x0000000c /* Mask of page size bits */
227	#define MI_PS8MEG 0x0000000c /* 8M page size */
228	#define MI_PS512K 0x00000004 /* 512K page size */
229	#define MI_PS4K_16K 0x00000000 /* 4K or 16K page size */
230	#define MI_SVALID 0x00000001 /* Segment entry is valid */
231	/* Reset value is undefined */
232
233	/* Real page number. Defined by the pte. Writing this register
234	* causes a TLB entry to be created for the instruction TLB, using
235	* additional information from the MI_EPN, and MI_TWC registers.
236	*/
237	#define MI_RPN 790
238
239	/* Define an RPN value for mapping kernel memory to large virtual
240	* pages for boot initialization. This has real page number of 0,
241	* large page size, shared page, cache enabled, and valid.
242	* Also mark all subpages valid and write access.
243	*/
244	#define MI_BOOTINIT 0x000001fd
245
246	#define MD_CTR 792 /* Data TLB control register */
247	#define MD_GPM 0x80000000 /* Set domain manager mode */
248	#define MD_PPM 0x40000000 /* Set subpage protection */
249	#define MD_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */
250	#define MD_WTDEF 0x10000000 /* Set writethrough when MMU dis */
251	#define MD_RSV4I 0x08000000 /* Reserve 4 TLB entries */
252	#define MD_TWAM 0x04000000 /* Use 4K page hardware assist */
253	#define MD_PPCS 0x02000000 /* Use MI_RPN prob/priv state */
254	#define MD_IDXMASK 0x00001f00 /* TLB index to be loaded */
255	#define MD_RESETVAL 0x04000000 /* Value of register at reset */
256
257	#define M_CASID 793 /* Address space ID (context) to match */
258	#define MC_ASIDMASK 0x0000000f /* Bits used for ASID value */
259
260
261	/* These are the Ks and Kp from the PowerPC books. For proper operation,
262	* Ks = 0, Kp = 1.
263	*/
264	#define MD_AP 794
265	#define MD_Ks 0x80000000 /* Should not be set */
266	#define MD_Kp 0x40000000 /* Should always be set */
267
268	/* The effective page number register. When read, contains the information
269	* about the last instruction TLB miss. When MD_RPN is written, bits in
270	* this register are used to create the TLB entry.
271	*/
272	#define MD_EPN 795
273	#define MD_EPNMASK 0xfffff000 /* Effective page number for entry */
274	#define MD_EVALID 0x00000200 /* Entry is valid */
275	#define MD_ASIDMASK 0x0000000f /* ASID match value */
276	/* Reset value is undefined */
277
278	/* The pointer to the base address of the first level page table.
279	* During a software tablewalk, reading this register provides the address
280	* of the entry associated with MD_EPN.
281	*/
282	#define M_TWB 796
283	#define M_L1TB 0xfffff000 /* Level 1 table base address */
284	#define M_L1INDX 0x00000ffc /* Level 1 index, when read */
285	/* Reset value is undefined */
286
287	/* A "level 1" or "segment" or whatever you want to call it register.
288	* For the data TLB, it contains bits that get loaded into the TLB entry
289	* when the MD_RPN is written. It is also provides the hardware assist
290	* for finding the PTE address during software tablewalk.
291	*/
292	#define MD_TWC 797
293	#define MD_L2TB 0xfffff000 /* Level 2 table base address */
294	#define MD_L2INDX 0xfffffe00 /* Level 2 index (pte), when read /
295	#define MD_APG 0x000001e0 /* Access protection group (0) */
296	#define MD_GUARDED 0x00000010 /* Guarded storage */
297	#define MD_PSMASK 0x0000000c /* Mask of page size bits */
298	#define MD_PS8MEG 0x0000000c /* 8M page size */
299	#define MD_PS512K 0x00000004 /* 512K page size */
300	#define MD_PS4K_16K 0x00000000 /* 4K or 16K page size */
301	#define MD_WT 0x00000002 /* Use writethrough page attribute */
302	#define MD_SVALID 0x00000001 /* Segment entry is valid */
303	/* Reset value is undefined */
304
305
306	/* Real page number. Defined by the pte. Writing this register
307	* causes a TLB entry to be created for the data TLB, using
308	* additional information from the MD_EPN, and MD_TWC registers.
309	*/
310	#define MD_RPN 798
311
312	/* This is a temporary storage register that could be used to save
313	* a processor working register during a tablewalk.
314	*/
315	#define M_TW 799
316
317	/*
318	* At present, all PowerPC 400-class processors share a similar TLB
319	* architecture. The instruction and data sides share a unified,
320	* 64-entry, fully-associative TLB which is maintained totally under
321	* software control. In addition, the instruction side has a
322	* hardware-managed, 4-entry, fully- associative TLB which serves as a
323	* first level to the shared TLB. These two TLBs are known as the UTLB
324	* and ITLB, respectively.
325	*/
326
327	#define PPC4XX_TLB_SIZE 64
328
329	/*
330	* TLB entries are defined by a "high" tag portion and a "low" data
331	* portion. On all architectures, the data portion is 32-bits.
332	*
333	* TLB entries are managed entirely under software control by reading,
334	* writing, and searchoing using the 4xx-specific tlbre, tlbwr, and tlbsx
335	* instructions.
336	*/
337
338	#define TLB_LO 1
339	#define TLB_HI 0
340
341	#define TLB_DATA TLB_LO
342	#define TLB_TAG TLB_HI
343
344	/* Tag portion */
345
346	#define TLB_EPN_MASK 0xFFFFFC00 /* Effective Page Number */
347	#define TLB_PAGESZ_MASK 0x00000380
348	#define TLB_PAGESZ(x) (((x) & 0x7) << 7)
349	#define PAGESZ_1K 0
350	#define PAGESZ_4K 1
351	#define PAGESZ_16K 2
352	#define PAGESZ_64K 3
353	#define PAGESZ_256K 4
354	#define PAGESZ_1M 5
355	#define PAGESZ_4M 6
356	#define PAGESZ_16M 7
357	#define TLB_VALID 0x00000040 /* Entry is valid */
358
359	/* Data portion */
360
361	#define TLB_RPN_MASK 0xFFFFFC00 /* Real Page Number */
362	#define TLB_PERM_MASK 0x00000300
363	#define TLB_EX 0x00000200 /* Instruction execution allowed */
364	#define TLB_WR 0x00000100 /* Writes permitted */
365	#define TLB_ZSEL_MASK 0x000000F0
366	#define TLB_ZSEL(x) (((x) & 0xF) << 4)
367	#define TLB_ATTR_MASK 0x0000000F
368	#define TLB_W 0x00000008 /* Caching is write-through */
369	#define TLB_I 0x00000004 /* Caching is inhibited */
370	#define TLB_M 0x00000002 /* Memory is coherent */
371	#define TLB_G 0x00000001 /* Memory is guarded from prefetch */
372
42d1f039 WD	373	/*
	374	* e500 support
	375	*/
	376
	377	#define MAS0_TLBSEL 0x10000000
	378	#define MAS0_ESEL 0x000F0000
	379	#define MAS0_NV 0x00000001
	380
	381	#define MAS1_VALID 0x80000000
	382	#define MAS1_IPROT 0x40000000
	383	#define MAS1_TID 0x00FF0000
	384	#define MAS1_TS 0x00001000
	385	#define MAS1_TSIZE 0x00000F00
	386
	387	#define MAS2_EPN 0xFFFFF000
	388	#define MAS2_SHAREN 0x00000200
	389	#define MAS2_X0 0x00000040
	390	#define MAS2_X1 0x00000020
	391	#define MAS2_W 0x00000010
	392	#define MAS2_I 0x00000008
	393	#define MAS2_M 0x00000004
	394	#define MAS2_G 0x00000002
	395	#define MAS2_E 0x00000001
	396
	397	#define MAS3_RPN 0xFFFFF000
	398	#define MAS3_U0 0x00000200
	399	#define MAS3_U1 0x00000100
	400	#define MAS3_U2 0x00000080
	401	#define MAS3_U3 0x00000040
	402	#define MAS3_UX 0x00000020
	403	#define MAS3_SX 0x00000010
	404	#define MAS3_UW 0x00000008
	405	#define MAS3_SW 0x00000004
	406	#define MAS3_UR 0x00000002
	407	#define MAS3_SR 0x00000001
	408
	409	#define MAS4_TLBSELD 0x10000000
	410	#define MAS4_TIDDSEL 0x00030000
	411	#define MAS4_DSHAREN 0x00001000
	412	#define MAS4_TSIZED(x) (x << 8)
	413	#define MAS4_X0D 0x00000040
	414	#define MAS4_X1D 0x00000020
	415	#define MAS4_WD 0x00000010
	416	#define MAS4_ID 0x00000008
	417	#define MAS4_MD 0x00000004
	418	#define MAS4_GD 0x00000002
	419	#define MAS4_ED 0x00000001
	420
	421	#define MAS6_SPID 0x00FF0000
	422	#define MAS6_SAS 0x00000001
	423
	424	#define BOOKE_PAGESZ_1K 0
	425	#define BOOKE_PAGESZ_4K 1
	426	#define BOOKE_PAGESZ_16K 2
	427	#define BOOKE_PAGESZ_64K 3
	428	#define BOOKE_PAGESZ_256K 4
	429	#define BOOKE_PAGESZ_1M 5
	430	#define BOOKE_PAGESZ_4M 6
	431	#define BOOKE_PAGESZ_16M 7
	432	#define BOOKE_PAGESZ_64M 8
	433	#define BOOKE_PAGESZ_256M 9
	434	#define BOOKE_PAGESZ_1GB 10
	435	#define BOOKE_PAGESZ_4GB 11
	436
debb7354	437	#if defined(CONFIG_MPC86xx)
2c33e8a1 JL	438	#define LAWBAR_BASE_ADDR 0x00FFFFFF
2c33e8a1 JL	439	#define LAWAR_TRGT_IF 0x01F00000
debb7354	440	#else
42d1f039	441	#define LAWBAR_BASE_ADDR 0x000FFFFF
42d1f039	442	#define LAWAR_TRGT_IF 0x00F00000
debb7354 JL	443	#endif
debb7354 JL	444	#define LAWAR_EN 0x80000000
42d1f039 WD	445	#define LAWAR_SIZE 0x0000003F
	446
	447	#define LAWAR_TRGT_IF_PCI 0x00000000
0ac6f8b7	448	#define LAWAR_TRGT_IF_PCI1 0x00000000
42d1f039	449	#define LAWAR_TRGT_IF_PCIX 0x00000000
0ac6f8b7	450	#define LAWAR_TRGT_IF_PCI2 0x00100000
2c33e8a1	451	#define LAWAR_TRGT_IF_HT 0x00200000
42d1f039 WD	452	#define LAWAR_TRGT_IF_LBC 0x00400000
42d1f039 WD	453	#define LAWAR_TRGT_IF_CCSR 0x00800000
debb7354	454	#define LAWAR_TRGT_IF_DDR_INTERLEAVED 0x00B00000
42d1f039 WD	455	#define LAWAR_TRGT_IF_RIO 0x00c00000
42d1f039 WD	456	#define LAWAR_TRGT_IF_DDR 0x00f00000
2c33e8a1 JL	457	#define LAWAR_TRGT_IF_DDR1 0x00f00000
2c33e8a1 JL	458	#define LAWAR_TRGT_IF_DDR2 0x01600000
42d1f039 WD	459
	460	#define LAWAR_SIZE_BASE 0xa
	461	#define LAWAR_SIZE_4K (LAWAR_SIZE_BASE+1)
	462	#define LAWAR_SIZE_8K (LAWAR_SIZE_BASE+2)
	463	#define LAWAR_SIZE_16K (LAWAR_SIZE_BASE+3)
	464	#define LAWAR_SIZE_32K (LAWAR_SIZE_BASE+4)
	465	#define LAWAR_SIZE_64K (LAWAR_SIZE_BASE+5)
	466	#define LAWAR_SIZE_128K (LAWAR_SIZE_BASE+6)
	467	#define LAWAR_SIZE_256K (LAWAR_SIZE_BASE+7)
	468	#define LAWAR_SIZE_512K (LAWAR_SIZE_BASE+8)
	469	#define LAWAR_SIZE_1M (LAWAR_SIZE_BASE+9)
	470	#define LAWAR_SIZE_2M (LAWAR_SIZE_BASE+10)
	471	#define LAWAR_SIZE_4M (LAWAR_SIZE_BASE+11)
	472	#define LAWAR_SIZE_8M (LAWAR_SIZE_BASE+12)
	473	#define LAWAR_SIZE_16M (LAWAR_SIZE_BASE+13)
	474	#define LAWAR_SIZE_32M (LAWAR_SIZE_BASE+14)
	475	#define LAWAR_SIZE_64M (LAWAR_SIZE_BASE+15)
	476	#define LAWAR_SIZE_128M (LAWAR_SIZE_BASE+16)
	477	#define LAWAR_SIZE_256M (LAWAR_SIZE_BASE+17)
	478	#define LAWAR_SIZE_512M (LAWAR_SIZE_BASE+18)
	479	#define LAWAR_SIZE_1G (LAWAR_SIZE_BASE+19)
	480	#define LAWAR_SIZE_2G (LAWAR_SIZE_BASE+20)
2c33e8a1 JL	481	#define LAWAR_SIZE_4G (LAWAR_SIZE_BASE+21)
	482	#define LAWAR_SIZE_8G (LAWAR_SIZE_BASE+22)
	483	#define LAWAR_SIZE_16G (LAWAR_SIZE_BASE+23)
	484	#define LAWAR_SIZE_32G (LAWAR_SIZE_BASE+24)
42d1f039	485
6c5879f3 MB	486	#ifdef CONFIG_440SPE
	487	/*----------------------------------------------------------------------------+
	488	\| Following instructions are not available in Book E mode of the GNU assembler.
	489	+----------------------------------------------------------------------------*/
	490	#define DCCCI(ra,rb) .long 0x7c000000\|\
	491	(ra<<16)\|(rb<<11)\|(454<<1)
	492
	493	#define ICCCI(ra,rb) .long 0x7c000000\|\
	494	(ra<<16)\|(rb<<11)\|(966<<1)
	495
	496	#define DCREAD(rt,ra,rb) .long 0x7c000000\|\
	497	(rt<<21)\|(ra<<16)\|(rb<<11)\|(486<<1)
	498
	499	#define ICREAD(ra,rb) .long 0x7c000000\|\
	500	(ra<<16)\|(rb<<11)\|(998<<1)
	501
	502	#define TLBSX(rt,ra,rb) .long 0x7c000000\|\
	503	(rt<<21)\|(ra<<16)\|(rb<<11)\|(914<<1)
	504
	505	#define TLBWE(rs,ra,ws) .long 0x7c000000\|\
	506	(rs<<21)\|(ra<<16)\|(ws<<11)\|(978<<1)
	507
	508	#define TLBRE(rt,ra,ws) .long 0x7c000000\|\
	509	(rt<<21)\|(ra<<16)\|(ws<<11)\|(946<<1)
	510
	511	#define TLBSXDOT(rt,ra,rb) .long 0x7c000001\|\
	512	(rt<<21)\|(ra<<16)\|(rb<<11)\|(914<<1)
	513
	514	#define MSYNC .long 0x7c000000\|\
	515	(598<<1)
	516
	517	#define MBAR_INST .long 0x7c000000\|\
	518	(854<<1)
	519
	520	/*----------------------------------------------------------------------------+
	521	\| Following instruction is not available in PPC405 mode of the GNU assembler.
	522	+----------------------------------------------------------------------------*/
	523	#define TLBRE(rt,ra,ws) .long 0x7c000000\|\
	524	(rt<<21)\|(ra<<16)\|(ws<<11)\|(946<<1)
	525
	526	#endif
3b759bd6	527	#endif /* _PPC_MMU_H_ */