[people/ms/u-boot.git] / include / asm-ppc / ppc4xx-uic.h

/*
 *  Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
 *
 * (C) Copyright 2008
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef _PPC4xx_UIC_H_
#define _PPC4xx_UIC_H_

/*
 * Define the number of UIC's
 */
#if defined(CONFIG_440SPE) || \
    defined(CONFIG_460EX) || defined(CONFIG_460GT)
#define UIC_MAX		4
#elif defined(CONFIG_440GX) || \
    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
    defined(CONFIG_405EX)
#define UIC_MAX		3
#elif defined(CONFIG_440GP) || defined(CONFIG_440SP) || \
    defined(CONFIG_440EP) || defined(CONFIG_440GR)
#define UIC_MAX		2
#else
#define UIC_MAX		1
#endif

/*
 * UIC register
 */
#define UIC_SR	0x0			/* UIC status			*/
#define UIC_ER	0x2			/* UIC enable			*/
#define UIC_CR	0x3			/* UIC critical			*/
#define UIC_PR	0x4			/* UIC polarity			*/
#define UIC_TR	0x5			/* UIC triggering		*/
#define UIC_MSR 0x6			/* UIC masked status		*/
#define UIC_VR	0x7			/* UIC vector			*/
#define UIC_VCR 0x8			/* UIC vector configuration	*/

#define UIC0_DCR_BASE 0xc0
#define uic0sr	(UIC0_DCR_BASE+0x0)	/* UIC0 status			*/
#define uic0er	(UIC0_DCR_BASE+0x2)	/* UIC0 enable			*/
#define uic0cr	(UIC0_DCR_BASE+0x3)	/* UIC0 critical		*/
#define uic0pr	(UIC0_DCR_BASE+0x4)	/* UIC0 polarity		*/
#define uic0tr	(UIC0_DCR_BASE+0x5)	/* UIC0 triggering		*/
#define uic0msr (UIC0_DCR_BASE+0x6)	/* UIC0 masked status		*/
#define uic0vr	(UIC0_DCR_BASE+0x7)	/* UIC0 vector			*/
#define uic0vcr (UIC0_DCR_BASE+0x8)	/* UIC0 vector configuration	*/

#define UIC1_DCR_BASE 0xd0
#define uic1sr	(UIC1_DCR_BASE+0x0)	/* UIC1 status			*/
#define uic1er	(UIC1_DCR_BASE+0x2)	/* UIC1 enable			*/
#define uic1cr	(UIC1_DCR_BASE+0x3)	/* UIC1 critical		*/
#define uic1pr	(UIC1_DCR_BASE+0x4)	/* UIC1 polarity		*/
#define uic1tr	(UIC1_DCR_BASE+0x5)	/* UIC1 triggering		*/
#define uic1msr (UIC1_DCR_BASE+0x6)	/* UIC1 masked status		*/
#define uic1vr	(UIC1_DCR_BASE+0x7)	/* UIC1 vector			*/
#define uic1vcr (UIC1_DCR_BASE+0x8)	/* UIC1 vector configuration	*/

#if defined(CONFIG_440GX)
#define UIC2_DCR_BASE 0x210
#else
#define UIC2_DCR_BASE 0xe0
#endif
#define uic2sr	(UIC2_DCR_BASE+0x0)	/* UIC2 status-Read Clear	*/
#define uic2srs	(UIC2_DCR_BASE+0x1)	/* UIC2 status-Read Set		*/
#define uic2er	(UIC2_DCR_BASE+0x2)	/* UIC2 enable			*/
#define uic2cr	(UIC2_DCR_BASE+0x3)	/* UIC2 critical		*/
#define uic2pr	(UIC2_DCR_BASE+0x4)	/* UIC2 polarity		*/
#define uic2tr	(UIC2_DCR_BASE+0x5)	/* UIC2 triggering		*/
#define uic2msr (UIC2_DCR_BASE+0x6)	/* UIC2 masked status		*/
#define uic2vr	(UIC2_DCR_BASE+0x7)	/* UIC2 vector			*/
#define uic2vcr (UIC2_DCR_BASE+0x8)	/* UIC2 vector configuration	*/

#define UIC3_DCR_BASE 0xf0
#define uic3sr	(UIC3_DCR_BASE+0x0)	/* UIC3 status-Read Clear	*/
#define uic3srs	(UIC3_DCR_BASE+0x1)	/* UIC3 status-Read Set		*/
#define uic3er	(UIC3_DCR_BASE+0x2)	/* UIC3 enable			*/
#define uic3cr	(UIC3_DCR_BASE+0x3)	/* UIC3 critical		*/
#define uic3pr	(UIC3_DCR_BASE+0x4)	/* UIC3 polarity		*/
#define uic3tr	(UIC3_DCR_BASE+0x5)	/* UIC3 triggering		*/
#define uic3msr (UIC3_DCR_BASE+0x6)	/* UIC3 masked status		*/
#define uic3vr	(UIC3_DCR_BASE+0x7)	/* UIC3 vector			*/
#define uic3vcr (UIC3_DCR_BASE+0x8)	/* UIC3 vector configuration	*/

#if defined(CONFIG_440GX)
#define UIC_DCR_BASE 0x200
#define uicb0sr	 (UIC_DCR_BASE+0x0)	/* UIC Base Status Register	*/
#define uicb0er	 (UIC_DCR_BASE+0x2)	/* UIC Base enable		*/
#define uicb0cr	 (UIC_DCR_BASE+0x3)	/* UIC Base critical		*/
#define uicb0pr	 (UIC_DCR_BASE+0x4)	/* UIC Base polarity		*/
#define uicb0tr	 (UIC_DCR_BASE+0x5)	/* UIC Base triggering		*/
#define uicb0msr (UIC_DCR_BASE+0x6)	/* UIC Base masked status	*/
#define uicb0vr	 (UIC_DCR_BASE+0x7)	/* UIC Base vector		*/
#define uicb0vcr (UIC_DCR_BASE+0x8)	/* UIC Base vector configuration*/
#endif /* CONFIG_440GX */

/* The following is for compatibility with 405 code */
#define uicsr  uic0sr
#define uicer  uic0er
#define uiccr  uic0cr
#define uicpr  uic0pr
#define uictr  uic0tr
#define uicmsr uic0msr
#define uicvr  uic0vr
#define uicvcr uic0vcr

/*
 * Now the interrupt vector definitions. They are different for most of
 * the 4xx variants, so we need some more #ifdef's here. No mask
 * definitions anymore here. For this please use the UIC_MASK macro below.
 *
 * Note: Please only define the interrupts really used in U-Boot here.
 * Those are the cascading and EMAC/MAL related interrupt.
 */

#if defined(CONFIG_405EP) || defined(CONFIG_405GP)
#define VECNUM_MAL_SERR		10
#define VECNUM_MAL_TXEOB	11
#define VECNUM_MAL_RXEOB	12
#define VECNUM_MAL_TXDE		13
#define VECNUM_MAL_RXDE		14
#define VECNUM_ETH0		15
#define VECNUM_ETH1_OFFS	2
#define VECNUM_EIRQ6		29
#endif /* defined(CONFIG_405EP) */

#if defined(CONFIG_405EZ)
#define VECNUM_USBDEV		15
#define VECNUM_ETH0		16
#define VECNUM_MAL_SERR		18
#define VECNUM_MAL_TXDE		18
#define VECNUM_MAL_RXDE		18
#define VECNUM_MAL_TXEOB	19
#define VECNUM_MAL_RXEOB	21
#endif /* CONFIG_405EX */

#if defined(CONFIG_405EX)
/* UIC 0 */
#define VECNUM_MAL_TXEOB	10
#define VECNUM_MAL_RXEOB	11
#define VECNUM_ETH0		24
#define VECNUM_ETH1_OFFS	1
#define VECNUM_UIC2NCI		28
#define VECNUM_UIC2CI		29
#define VECNUM_UIC1NCI		30
#define VECNUM_UIC1CI		31

/* UIC 1 */
#define VECNUM_MAL_SERR		(32 + 0)
#define VECNUM_MAL_TXDE		(32 + 1)
#define VECNUM_MAL_RXDE		(32 + 2)
#endif /* CONFIG_405EX */

#if defined(CONFIG_440GP) || \
    defined(CONFIG_440EP) || defined(CONFIG_440GR)
/* UIC 0 */
#define VECNUM_MAL_TXEOB	10
#define VECNUM_MAL_RXEOB	11
#define VECNUM_UIC1NCI		30
#define VECNUM_UIC1CI		31

/* UIC 1 */
#define VECNUM_MAL_SERR		(32 + 0)
#define VECNUM_MAL_TXDE		(32 + 1)
#define VECNUM_MAL_RXDE		(32 + 2)
#define VECNUM_USBDEV		(32 + 23)
#define VECNUM_ETH0		(32 + 28)
#define VECNUM_ETH1_OFFS	2
#endif /* CONFIG_440GP */

#if defined(CONFIG_440GX)
/* UIC 0 */
#define VECNUM_MAL_TXEOB	10
#define VECNUM_MAL_RXEOB	11

/* UIC 1 */
#define VECNUM_MAL_SERR		(32 + 0)
#define VECNUM_MAL_TXDE		(32 + 1)
#define VECNUM_MAL_RXDE		(32 + 2)
#define VECNUM_ETH0		(32 + 28)
#define VECNUM_ETH1_OFFS	2

/* UICB 0 (440GX only) */
#define VECNUM_UIC0CI		0
#define VECNUM_UIC0NCI		1
#define VECNUM_UIC1CI		2
#define VECNUM_UIC1NCI		3
#define VECNUM_UIC2CI		4
#define VECNUM_UIC2NCI		5
#endif /* CONFIG_440GX */

#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
/* UIC 0 */
#define VECNUM_MAL_TXEOB	10
#define VECNUM_MAL_RXEOB	11
#define VECNUM_USBDEV		20
#define VECNUM_ETH0		24
#define VECNUM_ETH1_OFFS	1
#define VECNUM_UIC2NCI		28
#define VECNUM_UIC2CI		29
#define VECNUM_UIC1NCI		30
#define VECNUM_UIC1CI		31

/* UIC 1 */
#define VECNUM_MAL_SERR		(32 + 0)
#define VECNUM_MAL_TXDE		(32 + 1)
#define VECNUM_MAL_RXDE		(32 + 2)

/* UIC 2 */
#define VECNUM_EIRQ2		(64 + 3)
#endif /* CONFIG_440EPX */

#if defined(CONFIG_440SP)
/* UIC 0 */
#define VECNUM_UIC1NCI		30
#define VECNUM_UIC1CI		31

/* UIC 1 */
#define VECNUM_MAL_SERR		(32 + 1)
#define VECNUM_MAL_TXDE		(32 + 2)
#define VECNUM_MAL_RXDE		(32 + 3)
#define VECNUM_MAL_TXEOB	(32 + 6)
#define VECNUM_MAL_RXEOB	(32 + 7)
#define VECNUM_ETH0		(32 + 28)
#endif /* CONFIG_440SP */

#if defined(CONFIG_440SPE)
/* UIC 0 */
#define VECNUM_UIC2NCI		10
#define VECNUM_UIC2CI		11
#define VECNUM_UIC3NCI		16
#define VECNUM_UIC3CI		17
#define VECNUM_UIC1NCI		30
#define VECNUM_UIC1CI		31

/* UIC 1 */
#define VECNUM_MAL_SERR		(32 + 1)
#define VECNUM_MAL_TXDE		(32 + 2)
#define VECNUM_MAL_RXDE		(32 + 3)
#define VECNUM_MAL_TXEOB	(32 + 6)
#define VECNUM_MAL_RXEOB	(32 + 7)
#define VECNUM_ETH0		(32 + 28)
#endif /* CONFIG_440SPE */

#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
/* UIC 0 */
#define VECNUM_UIC2NCI		10
#define VECNUM_UIC2CI		11
#define VECNUM_UIC3NCI		16
#define VECNUM_UIC3CI		17
#define VECNUM_UIC1NCI		30
#define VECNUM_UIC1CI		31

/* UIC 2 */
#define VECNUM_MAL_SERR		(64 + 3)
#define	VECNUM_MAL_TXDE		(64 + 4)
#define	VECNUM_MAL_RXDE		(64 + 5)
#define VECNUM_MAL_TXEOB	(64 + 6)
#define	VECNUM_MAL_RXEOB	(64 + 7)
#define	VECNUM_ETH0		(64 + 16)
#define VECNUM_ETH1_OFFS	1
#endif /* CONFIG_460EX */

#if !defined(VECNUM_ETH1_OFFS)
#define VECNUM_ETH1_OFFS	1
#endif

/*
 * Mask definitions (used for example in 4xx_enet.c)
 */
#define UIC_MASK(vec)		(0x80000000 >> ((vec) & 0x1f))
#define UIC_NR(vec)		((vec) >> 5)

#endif /* _PPC4xx_UIC_H_ */
Commit	Line	Data
c609719b	1	/*
4fb25a3d SR	2	* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
	3	*
	4	* (C) Copyright 2008
	5	* Stefan Roese, DENX Software Engineering, sr@denx.de.
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
c609719b	14	*
4fb25a3d SR	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
c609719b	19	*
4fb25a3d SR	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
c609719b WD	24	*/
c609719b WD	25
4fb25a3d SR	26	#ifndef _PPC4xx_UIC_H_
4fb25a3d SR	27	#define _PPC4xx_UIC_H_
c609719b	28
d1631fe1 SR	29	/*
	30	* Define the number of UIC's
	31	*/
	32	#if defined(CONFIG_440SPE) \|\| \
	33	defined(CONFIG_460EX) \|\| defined(CONFIG_460GT)
	34	#define UIC_MAX 4
	35	#elif defined(CONFIG_440GX) \|\| \
	36	defined(CONFIG_440EPX) \|\| defined(CONFIG_440GRX) \|\| \
	37	defined(CONFIG_405EX)
	38	#define UIC_MAX 3
	39	#elif defined(CONFIG_440GP) \|\| defined(CONFIG_440SP) \|\| \
	40	defined(CONFIG_440EP) \|\| defined(CONFIG_440GR)
	41	#define UIC_MAX 2
	42	#else
	43	#define UIC_MAX 1
	44	#endif
887e2ec9	45
d1631fe1 SR	46	/*
	47	* UIC register
	48	*/
	49	#define UIC_SR 0x0 /* UIC status */
	50	#define UIC_ER 0x2 /* UIC enable */
	51	#define UIC_CR 0x3 /* UIC critical */
	52	#define UIC_PR 0x4 /* UIC polarity */
	53	#define UIC_TR 0x5 /* UIC triggering */
	54	#define UIC_MSR 0x6 /* UIC masked status */
	55	#define UIC_VR 0x7 /* UIC vector */
	56	#define UIC_VCR 0x8 /* UIC vector configuration */
	57
	58	#define UIC0_DCR_BASE 0xc0
	59	#define uic0sr (UIC0_DCR_BASE+0x0) /* UIC0 status */
	60	#define uic0er (UIC0_DCR_BASE+0x2) /* UIC0 enable */
	61	#define uic0cr (UIC0_DCR_BASE+0x3) /* UIC0 critical */
	62	#define uic0pr (UIC0_DCR_BASE+0x4) /* UIC0 polarity */
	63	#define uic0tr (UIC0_DCR_BASE+0x5) /* UIC0 triggering */
	64	#define uic0msr (UIC0_DCR_BASE+0x6) /* UIC0 masked status */
	65	#define uic0vr (UIC0_DCR_BASE+0x7) /* UIC0 vector */
	66	#define uic0vcr (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration */
	67
	68	#define UIC1_DCR_BASE 0xd0
	69	#define uic1sr (UIC1_DCR_BASE+0x0) /* UIC1 status */
	70	#define uic1er (UIC1_DCR_BASE+0x2) /* UIC1 enable */
	71	#define uic1cr (UIC1_DCR_BASE+0x3) /* UIC1 critical */
	72	#define uic1pr (UIC1_DCR_BASE+0x4) /* UIC1 polarity */
	73	#define uic1tr (UIC1_DCR_BASE+0x5) /* UIC1 triggering */
	74	#define uic1msr (UIC1_DCR_BASE+0x6) /* UIC1 masked status */
	75	#define uic1vr (UIC1_DCR_BASE+0x7) /* UIC1 vector */
	76	#define uic1vcr (UIC1_DCR_BASE+0x8) /* UIC1 vector configuration */
	77
	78	#if defined(CONFIG_440GX)
	79	#define UIC2_DCR_BASE 0x210
	80	#else
	81	#define UIC2_DCR_BASE 0xe0
	82	#endif
	83	#define uic2sr (UIC2_DCR_BASE+0x0) /* UIC2 status-Read Clear */
	84	#define uic2srs (UIC2_DCR_BASE+0x1) /* UIC2 status-Read Set */
	85	#define uic2er (UIC2_DCR_BASE+0x2) /* UIC2 enable */
	86	#define uic2cr (UIC2_DCR_BASE+0x3) /* UIC2 critical */
	87	#define uic2pr (UIC2_DCR_BASE+0x4) /* UIC2 polarity */
	88	#define uic2tr (UIC2_DCR_BASE+0x5) /* UIC2 triggering */
	89	#define uic2msr (UIC2_DCR_BASE+0x6) /* UIC2 masked status */
	90	#define uic2vr (UIC2_DCR_BASE+0x7) /* UIC2 vector */
	91	#define uic2vcr (UIC2_DCR_BASE+0x8) /* UIC2 vector configuration */
	92
	93	#define UIC3_DCR_BASE 0xf0
	94	#define uic3sr (UIC3_DCR_BASE+0x0) /* UIC3 status-Read Clear */
	95	#define uic3srs (UIC3_DCR_BASE+0x1) /* UIC3 status-Read Set */
	96	#define uic3er (UIC3_DCR_BASE+0x2) /* UIC3 enable */
	97	#define uic3cr (UIC3_DCR_BASE+0x3) /* UIC3 critical */
	98	#define uic3pr (UIC3_DCR_BASE+0x4) /* UIC3 polarity */
	99	#define uic3tr (UIC3_DCR_BASE+0x5) /* UIC3 triggering */
	100	#define uic3msr (UIC3_DCR_BASE+0x6) /* UIC3 masked status */
	101	#define uic3vr (UIC3_DCR_BASE+0x7) /* UIC3 vector */
	102	#define uic3vcr (UIC3_DCR_BASE+0x8) /* UIC3 vector configuration */
	103
	104	#if defined(CONFIG_440GX)
	105	#define UIC_DCR_BASE 0x200
	106	#define uicb0sr (UIC_DCR_BASE+0x0) /* UIC Base Status Register */
	107	#define uicb0er (UIC_DCR_BASE+0x2) /* UIC Base enable */
	108	#define uicb0cr (UIC_DCR_BASE+0x3) /* UIC Base critical */
	109	#define uicb0pr (UIC_DCR_BASE+0x4) /* UIC Base polarity */
110	#define uicb0tr (UIC_DCR_BASE+0x5) /* UIC Base triggering */
111	#define uicb0msr (UIC_DCR_BASE+0x6) /* UIC Base masked status */
112	#define uicb0vr (UIC_DCR_BASE+0x7) /* UIC Base vector */
113	#define uicb0vcr (UIC_DCR_BASE+0x8) /* UIC Base vector configuration*/
114	#endif /* CONFIG_440GX */
115
116	/* The following is for compatibility with 405 code */
117	#define uicsr uic0sr
118	#define uicer uic0er
119	#define uiccr uic0cr
120	#define uicpr uic0pr
121	#define uictr uic0tr
122	#define uicmsr uic0msr
123	#define uicvr uic0vr
124	#define uicvcr uic0vcr
887e2ec9	125
d1631fe1 SR	126	/*
	127	* Now the interrupt vector definitions. They are different for most of
	128	* the 4xx variants, so we need some more #ifdef's here. No mask
	129	* definitions anymore here. For this please use the UIC_MASK macro below.
	130	*
	131	* Note: Please only define the interrupts really used in U-Boot here.
	132	* Those are the cascading and EMAC/MAL related interrupt.
	133	*/
887e2ec9	134
d1631fe1 SR	135	#if defined(CONFIG_405EP) \|\| defined(CONFIG_405GP)
	136	#define VECNUM_MAL_SERR 10
	137	#define VECNUM_MAL_TXEOB 11
	138	#define VECNUM_MAL_RXEOB 12
	139	#define VECNUM_MAL_TXDE 13
	140	#define VECNUM_MAL_RXDE 14
	141	#define VECNUM_ETH0 15
	142	#define VECNUM_ETH1_OFFS 2
	143	#define VECNUM_EIRQ6 29
	144	#endif /* defined(CONFIG_405EP) */
999ecd5a	145
d1631fe1 SR	146	#if defined(CONFIG_405EZ)
	147	#define VECNUM_USBDEV 15
	148	#define VECNUM_ETH0 16
	149	#define VECNUM_MAL_SERR 18
	150	#define VECNUM_MAL_TXDE 18
	151	#define VECNUM_MAL_RXDE 18
	152	#define VECNUM_MAL_TXEOB 19
	153	#define VECNUM_MAL_RXEOB 21
	154	#endif /* CONFIG_405EX */
	155
	156	#if defined(CONFIG_405EX)
999ecd5a	157	/* UIC 0 */
d1631fe1 SR	158	#define VECNUM_MAL_TXEOB 10
	159	#define VECNUM_MAL_RXEOB 11
	160	#define VECNUM_ETH0 24
	161	#define VECNUM_ETH1_OFFS 1
	162	#define VECNUM_UIC2NCI 28
	163	#define VECNUM_UIC2CI 29
	164	#define VECNUM_UIC1NCI 30
	165	#define VECNUM_UIC1CI 31
999ecd5a SR	166
999ecd5a SR	167	/* UIC 1 */
d1631fe1 SR	168	#define VECNUM_MAL_SERR (32 + 0)
	169	#define VECNUM_MAL_TXDE (32 + 1)
	170	#define VECNUM_MAL_RXDE (32 + 2)
	171	#endif /* CONFIG_405EX */
887e2ec9	172
d1631fe1 SR	173	#if defined(CONFIG_440GP) \|\| \
d1631fe1 SR	174	defined(CONFIG_440EP) \|\| defined(CONFIG_440GR)
6c5879f3	175	/* UIC 0 */
d1631fe1 SR	176	#define VECNUM_MAL_TXEOB 10
	177	#define VECNUM_MAL_RXEOB 11
	178	#define VECNUM_UIC1NCI 30
	179	#define VECNUM_UIC1CI 31
6c5879f3 MB	180
6c5879f3 MB	181	/* UIC 1 */
d1631fe1 SR	182	#define VECNUM_MAL_SERR (32 + 0)
	183	#define VECNUM_MAL_TXDE (32 + 1)
	184	#define VECNUM_MAL_RXDE (32 + 2)
	185	#define VECNUM_USBDEV (32 + 23)
	186	#define VECNUM_ETH0 (32 + 28)
	187	#define VECNUM_ETH1_OFFS 2
	188	#endif /* CONFIG_440GP */
	189
	190	#if defined(CONFIG_440GX)
6e7fb6ea	191	/* UIC 0 */
d1631fe1 SR	192	#define VECNUM_MAL_TXEOB 10
d1631fe1 SR	193	#define VECNUM_MAL_RXEOB 11
6e7fb6ea SR	194
6e7fb6ea SR	195	/* UIC 1 */
d1631fe1 SR	196	#define VECNUM_MAL_SERR (32 + 0)
	197	#define VECNUM_MAL_TXDE (32 + 1)
	198	#define VECNUM_MAL_RXDE (32 + 2)
	199	#define VECNUM_ETH0 (32 + 28)
	200	#define VECNUM_ETH1_OFFS 2
	201
	202	/* UICB 0 (440GX only) */
	203	#define VECNUM_UIC0CI 0
	204	#define VECNUM_UIC0NCI 1
	205	#define VECNUM_UIC1CI 2
	206	#define VECNUM_UIC1NCI 3
	207	#define VECNUM_UIC2CI 4
	208	#define VECNUM_UIC2NCI 5
	209	#endif /* CONFIG_440GX */
c609719b	210
d1631fe1	211	#if defined(CONFIG_440EPX) \|\| defined(CONFIG_440GRX)
c609719b	212	/* UIC 0 */
d1631fe1 SR	213	#define VECNUM_MAL_TXEOB 10
	214	#define VECNUM_MAL_RXEOB 11
	215	#define VECNUM_USBDEV 20
	216	#define VECNUM_ETH0 24
	217	#define VECNUM_ETH1_OFFS 1
	218	#define VECNUM_UIC2NCI 28
	219	#define VECNUM_UIC2CI 29
	220	#define VECNUM_UIC1NCI 30
	221	#define VECNUM_UIC1CI 31
c609719b WD	222
c609719b WD	223	/* UIC 1 */
d1631fe1 SR	224	#define VECNUM_MAL_SERR (32 + 0)
	225	#define VECNUM_MAL_TXDE (32 + 1)
	226	#define VECNUM_MAL_RXDE (32 + 2)
e01bd218	227
d1631fe1 SR	228	/* UIC 2 */
	229	#define VECNUM_EIRQ2 (64 + 3)
	230	#endif /* CONFIG_440EPX */
e01bd218	231
d1631fe1 SR	232	#if defined(CONFIG_440SP)
	233	/* UIC 0 */
	234	#define VECNUM_UIC1NCI 30
	235	#define VECNUM_UIC1CI 31
dbbd1257	236
d1631fe1 SR	237	/* UIC 1 */
	238	#define VECNUM_MAL_SERR (32 + 1)
	239	#define VECNUM_MAL_TXDE (32 + 2)
	240	#define VECNUM_MAL_RXDE (32 + 3)
	241	#define VECNUM_MAL_TXEOB (32 + 6)
	242	#define VECNUM_MAL_RXEOB (32 + 7)
	243	#define VECNUM_ETH0 (32 + 28)
	244	#endif /* CONFIG_440SP */
	245
	246	#if defined(CONFIG_440SPE)
dbbd1257	247	/* UIC 0 */
d1631fe1 SR	248	#define VECNUM_UIC2NCI 10
	249	#define VECNUM_UIC2CI 11
	250	#define VECNUM_UIC3NCI 16
	251	#define VECNUM_UIC3CI 17
	252	#define VECNUM_UIC1NCI 30
	253	#define VECNUM_UIC1CI 31
dbbd1257 SR	254
dbbd1257 SR	255	/* UIC 1 */
d1631fe1 SR	256	#define VECNUM_MAL_SERR (32 + 1)
	257	#define VECNUM_MAL_TXDE (32 + 2)
	258	#define VECNUM_MAL_RXDE (32 + 3)
	259	#define VECNUM_MAL_TXEOB (32 + 6)
	260	#define VECNUM_MAL_RXEOB (32 + 7)
	261	#define VECNUM_ETH0 (32 + 28)
	262	#endif /* CONFIG_440SPE */
	263
	264	#if defined(CONFIG_460EX) \|\| defined(CONFIG_460GT)
	265	/* UIC 0 */
	266	#define VECNUM_UIC2NCI 10
	267	#define VECNUM_UIC2CI 11
	268	#define VECNUM_UIC3NCI 16
	269	#define VECNUM_UIC3CI 17
	270	#define VECNUM_UIC1NCI 30
	271	#define VECNUM_UIC1CI 31
dbbd1257 SR	272
dbbd1257 SR	273	/* UIC 2 */
d1631fe1 SR	274	#define VECNUM_MAL_SERR (64 + 3)
	275	#define VECNUM_MAL_TXDE (64 + 4)
	276	#define VECNUM_MAL_RXDE (64 + 5)
	277	#define VECNUM_MAL_TXEOB (64 + 6)
	278	#define VECNUM_MAL_RXEOB (64 + 7)
	279	#define VECNUM_ETH0 (64 + 16)
	280	#define VECNUM_ETH1_OFFS 1
	281	#endif /* CONFIG_460EX */
	282
	283	#if !defined(VECNUM_ETH1_OFFS)
	284	#define VECNUM_ETH1_OFFS 1
	285	#endif
dbbd1257	286
d1631fe1 SR	287	/*
	288	* Mask definitions (used for example in 4xx_enet.c)
	289	*/
	290	#define UIC_MASK(vec) (0x80000000 >> ((vec) & 0x1f))
	291	#define UIC_NR(vec) ((vec) >> 5)
c609719b	292
4fb25a3d	293	#endif /* _PPC4xx_UIC_H_ */