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935ecca1 WD |
1 | #ifndef __ASM_PPC_PROCESSOR_H |
2 | #define __ASM_PPC_PROCESSOR_H | |
3 | ||
4 | /* | |
5 | * Default implementation of macro that returns current | |
6 | * instruction pointer ("program counter"). | |
7 | */ | |
8 | #define current_text_addr() ({ __label__ _l; _l: &&_l;}) | |
9 | ||
10 | #include <linux/config.h> | |
11 | ||
12 | #include <asm/ptrace.h> | |
13 | #include <asm/types.h> | |
14 | ||
15 | /* Machine State Register (MSR) Fields */ | |
16 | ||
17 | #ifdef CONFIG_PPC64BRIDGE | |
18 | #define MSR_SF (1<<63) | |
19 | #define MSR_ISF (1<<61) | |
20 | #endif /* CONFIG_PPC64BRIDGE */ | |
42d1f039 WD |
21 | #define MSR_UCLE (1<<26) /* User-mode cache lock enable (e500) */ |
22 | #define MSR_VEC (1<<25) /* Enable AltiVec(74xx) */ | |
23 | #define MSR_SPE (1<<25) /* Enable SPE(e500) */ | |
935ecca1 WD |
24 | #define MSR_POW (1<<18) /* Enable Power Management */ |
25 | #define MSR_WE (1<<18) /* Wait State Enable */ | |
26 | #define MSR_TGPR (1<<17) /* TLB Update registers in use */ | |
27 | #define MSR_CE (1<<17) /* Critical Interrupt Enable */ | |
28 | #define MSR_ILE (1<<16) /* Interrupt Little Endian */ | |
29 | #define MSR_EE (1<<15) /* External Interrupt Enable */ | |
30 | #define MSR_PR (1<<14) /* Problem State / Privilege Level */ | |
31 | #define MSR_FP (1<<13) /* Floating Point enable */ | |
32 | #define MSR_ME (1<<12) /* Machine Check Enable */ | |
33 | #define MSR_FE0 (1<<11) /* Floating Exception mode 0 */ | |
34 | #define MSR_SE (1<<10) /* Single Step */ | |
42d1f039 WD |
35 | #define MSR_DWE (1<<10) /* Debug Wait Enable (4xx) */ |
36 | #define MSR_UBLE (1<<10) /* BTB lock enable (e500) */ | |
935ecca1 WD |
37 | #define MSR_BE (1<<9) /* Branch Trace */ |
38 | #define MSR_DE (1<<9) /* Debug Exception Enable */ | |
39 | #define MSR_FE1 (1<<8) /* Floating Exception mode 1 */ | |
40 | #define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */ | |
41 | #define MSR_IR (1<<5) /* Instruction Relocate */ | |
42d1f039 | 42 | #define MSR_IS (1<<5) /* Book E Instruction space */ |
935ecca1 | 43 | #define MSR_DR (1<<4) /* Data Relocate */ |
42d1f039 | 44 | #define MSR_DS (1<<4) /* Book E Data space */ |
935ecca1 WD |
45 | #define MSR_PE (1<<3) /* Protection Enable */ |
46 | #define MSR_PX (1<<2) /* Protection Exclusive Mode */ | |
42d1f039 | 47 | #define MSR_PMM (1<<2) /* Performance monitor mark bit (e500) */ |
935ecca1 WD |
48 | #define MSR_RI (1<<1) /* Recoverable Exception */ |
49 | #define MSR_LE (1<<0) /* Little Endian */ | |
50 | ||
51 | #ifdef CONFIG_APUS_FAST_EXCEPT | |
52 | #define MSR_ MSR_ME|MSR_IP|MSR_RI | |
53 | #else | |
54 | #define MSR_ MSR_ME|MSR_RI | |
55 | #endif | |
42d1f039 | 56 | #ifndef CONFIG_E500 |
935ecca1 | 57 | #define MSR_KERNEL MSR_|MSR_IR|MSR_DR |
42d1f039 WD |
58 | #else |
59 | #define MSR_KERNEL MSR_ME | |
60 | #endif | |
935ecca1 WD |
61 | #define MSR_USER MSR_KERNEL|MSR_PR|MSR_EE |
62 | ||
63 | /* Floating Point Status and Control Register (FPSCR) Fields */ | |
64 | ||
65 | #define FPSCR_FX 0x80000000 /* FPU exception summary */ | |
66 | #define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */ | |
67 | #define FPSCR_VX 0x20000000 /* Invalid operation summary */ | |
68 | #define FPSCR_OX 0x10000000 /* Overflow exception summary */ | |
69 | #define FPSCR_UX 0x08000000 /* Underflow exception summary */ | |
70 | #define FPSCR_ZX 0x04000000 /* Zero-devide exception summary */ | |
71 | #define FPSCR_XX 0x02000000 /* Inexact exception summary */ | |
72 | #define FPSCR_VXSNAN 0x01000000 /* Invalid op for SNaN */ | |
73 | #define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */ | |
74 | #define FPSCR_VXIDI 0x00400000 /* Invalid op for Inv / Inv */ | |
75 | #define FPSCR_VXZDZ 0x00200000 /* Invalid op for Zero / Zero */ | |
76 | #define FPSCR_VXIMZ 0x00100000 /* Invalid op for Inv * Zero */ | |
77 | #define FPSCR_VXVC 0x00080000 /* Invalid op for Compare */ | |
78 | #define FPSCR_FR 0x00040000 /* Fraction rounded */ | |
79 | #define FPSCR_FI 0x00020000 /* Fraction inexact */ | |
80 | #define FPSCR_FPRF 0x0001f000 /* FPU Result Flags */ | |
81 | #define FPSCR_FPCC 0x0000f000 /* FPU Condition Codes */ | |
82 | #define FPSCR_VXSOFT 0x00000400 /* Invalid op for software request */ | |
83 | #define FPSCR_VXSQRT 0x00000200 /* Invalid op for square root */ | |
84 | #define FPSCR_VXCVI 0x00000100 /* Invalid op for integer convert */ | |
85 | #define FPSCR_VE 0x00000080 /* Invalid op exception enable */ | |
86 | #define FPSCR_OE 0x00000040 /* IEEE overflow exception enable */ | |
87 | #define FPSCR_UE 0x00000020 /* IEEE underflow exception enable */ | |
88 | #define FPSCR_ZE 0x00000010 /* IEEE zero divide exception enable */ | |
89 | #define FPSCR_XE 0x00000008 /* FP inexact exception enable */ | |
90 | #define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */ | |
91 | #define FPSCR_RN 0x00000003 /* FPU rounding control */ | |
92 | ||
93 | /* Special Purpose Registers (SPRNs)*/ | |
94 | ||
95 | #define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */ | |
96 | #define SPRN_CTR 0x009 /* Count Register */ | |
97 | #define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */ | |
42d1f039 | 98 | #ifndef CONFIG_BOOKE |
935ecca1 WD |
99 | #define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */ |
100 | #define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */ | |
42d1f039 WD |
101 | #else |
102 | #define SPRN_DAC1 0x13C /* Book E Data Address Compare 1 */ | |
103 | #define SPRN_DAC2 0x13D /* Book E Data Address Compare 2 */ | |
104 | #endif /* CONFIG_BOOKE */ | |
935ecca1 WD |
105 | #define SPRN_DAR 0x013 /* Data Address Register */ |
106 | #define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */ | |
107 | #define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */ | |
108 | #define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */ | |
109 | #define SPRN_DBAT1U 0x21A /* Data BAT 1 Upper Register */ | |
110 | #define SPRN_DBAT2L 0x21D /* Data BAT 2 Lower Register */ | |
111 | #define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */ | |
112 | #define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */ | |
113 | #define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */ | |
35656de7 WD |
114 | #define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */ |
115 | #define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */ | |
116 | #define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */ | |
117 | #define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */ | |
118 | #define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */ | |
119 | #define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */ | |
120 | #define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */ | |
121 | #define SPRN_DBAT7U 0x23E /* Data BAT 7 Lower Register */ | |
935ecca1 WD |
122 | #define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */ |
123 | #define DBCR_EDM 0x80000000 | |
124 | #define DBCR_IDM 0x40000000 | |
125 | #define DBCR_RST(x) (((x) & 0x3) << 28) | |
126 | #define DBCR_RST_NONE 0 | |
127 | #define DBCR_RST_CORE 1 | |
128 | #define DBCR_RST_CHIP 2 | |
129 | #define DBCR_RST_SYSTEM 3 | |
130 | #define DBCR_IC 0x08000000 /* Instruction Completion Debug Evnt */ | |
131 | #define DBCR_BT 0x04000000 /* Branch Taken Debug Event */ | |
132 | #define DBCR_EDE 0x02000000 /* Exception Debug Event */ | |
133 | #define DBCR_TDE 0x01000000 /* TRAP Debug Event */ | |
134 | #define DBCR_FER 0x00F80000 /* First Events Remaining Mask */ | |
135 | #define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */ | |
136 | #define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */ | |
137 | #define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */ | |
138 | #define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */ | |
139 | #define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */ | |
140 | #define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */ | |
141 | #define DAC_BYTE 0 | |
142 | #define DAC_HALF 1 | |
143 | #define DAC_WORD 2 | |
144 | #define DAC_QUAD 3 | |
145 | #define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */ | |
146 | #define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */ | |
147 | #define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */ | |
148 | #define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */ | |
149 | #define DBCR_SED 0x00000020 /* Second Exception Debug Event */ | |
150 | #define DBCR_STD 0x00000010 /* Second Trap Debug Event */ | |
151 | #define DBCR_SIA 0x00000008 /* Second IAC Enable */ | |
152 | #define DBCR_SDA 0x00000004 /* Second DAC Enable */ | |
153 | #define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */ | |
154 | #define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */ | |
42d1f039 WD |
155 | #ifndef CONFIG_BOOKE |
156 | #define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */ | |
157 | #else | |
158 | #define SPRN_DBCR0 0x134 /* Book E Debug Control Register 0 */ | |
159 | #endif /* CONFIG_BOOKE */ | |
160 | #ifndef CONFIG_BOOKE | |
935ecca1 WD |
161 | #define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */ |
162 | #define SPRN_DBSR 0x3F0 /* Debug Status Register */ | |
42d1f039 WD |
163 | #else |
164 | #define SPRN_DBCR1 0x135 /* Book E Debug Control Register 1 */ | |
165 | #define SPRN_DBSR 0x130 /* Book E Debug Status Register */ | |
166 | #define DBSR_IC 0x08000000 /* Book E Instruction Completion */ | |
167 | #define DBSR_TIE 0x01000000 /* Book E Trap Instruction Event */ | |
168 | #endif /* CONFIG_BOOKE */ | |
935ecca1 WD |
169 | #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ |
170 | #define DCCR_NOCACHE 0 /* Noncacheable */ | |
171 | #define DCCR_CACHE 1 /* Cacheable */ | |
172 | #define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */ | |
173 | #define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */ | |
174 | #define DCWR_COPY 0 /* Copy-back */ | |
175 | #define DCWR_WRITE 1 /* Write-through */ | |
42d1f039 | 176 | #ifndef CONFIG_BOOKE |
935ecca1 | 177 | #define SPRN_DEAR 0x3D5 /* Data Error Address Register */ |
42d1f039 WD |
178 | #else |
179 | #define SPRN_DEAR 0x03D /* Book E Data Error Address Register */ | |
180 | #endif /* CONFIG_BOOKE */ | |
935ecca1 WD |
181 | #define SPRN_DEC 0x016 /* Decrement Register */ |
182 | #define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */ | |
183 | #define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */ | |
184 | #define SPRN_EAR 0x11A /* External Address Register */ | |
42d1f039 | 185 | #ifndef CONFIG_BOOKE |
935ecca1 | 186 | #define SPRN_ESR 0x3D4 /* Exception Syndrome Register */ |
42d1f039 WD |
187 | #else |
188 | #define SPRN_ESR 0x03E /* Book E Exception Syndrome Register */ | |
189 | #endif /* CONFIG_BOOKE */ | |
935ecca1 WD |
190 | #define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */ |
191 | #define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */ | |
192 | #define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */ | |
193 | #define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */ | |
194 | #define ESR_PIL 0x08000000 /* Program Exception - Illegal */ | |
195 | #define ESR_PPR 0x04000000 /* Program Exception - Priveleged */ | |
196 | #define ESR_PTR 0x02000000 /* Program Exception - Trap */ | |
197 | #define ESR_DST 0x00800000 /* Storage Exception - Data miss */ | |
198 | #define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */ | |
199 | #define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */ | |
200 | #define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */ | |
201 | #define SPRN_HASH2 0x3D3 /* Secondary Hash Address Resgister */ | |
202 | #define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */ | |
203 | #define HID0_EMCP (1<<31) /* Enable Machine Check pin */ | |
204 | #define HID0_EBA (1<<29) /* Enable Bus Address Parity */ | |
205 | #define HID0_EBD (1<<28) /* Enable Bus Data Parity */ | |
206 | #define HID0_SBCLK (1<<27) | |
207 | #define HID0_EICE (1<<26) | |
208 | #define HID0_ECLK (1<<25) | |
209 | #define HID0_PAR (1<<24) | |
210 | #define HID0_DOZE (1<<23) | |
211 | #define HID0_NAP (1<<22) | |
212 | #define HID0_SLEEP (1<<21) | |
213 | #define HID0_DPM (1<<20) | |
214 | #define HID0_ICE (1<<15) /* Instruction Cache Enable */ | |
215 | #define HID0_DCE (1<<14) /* Data Cache Enable */ | |
216 | #define HID0_ILOCK (1<<13) /* Instruction Cache Lock */ | |
217 | #define HID0_DLOCK (1<<12) /* Data Cache Lock */ | |
218 | #define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */ | |
219 | #define HID0_DCFI (1<<10) /* Data Cache Flash Invalidate */ | |
220 | #define HID0_DCI HID0_DCFI | |
221 | #define HID0_SPD (1<<9) /* Speculative disable */ | |
222 | #define HID0_SGE (1<<7) /* Store Gathering Enable */ | |
223 | #define HID0_SIED HID_SGE /* Serial Instr. Execution [Disable] */ | |
224 | #define HID0_DCFA (1<<6) /* Data Cache Flush Assist */ | |
225 | #define HID0_BTIC (1<<5) /* Branch Target Instruction Cache Enable */ | |
226 | #define HID0_ABE (1<<3) /* Address Broadcast Enable */ | |
227 | #define HID0_BHTE (1<<2) /* Branch History Table Enable */ | |
228 | #define HID0_BTCD (1<<1) /* Branch target cache disable */ | |
229 | #define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */ | |
230 | #define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */ | |
42d1f039 | 231 | #ifndef CONFIG_BOOKE |
935ecca1 WD |
232 | #define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */ |
233 | #define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */ | |
42d1f039 WD |
234 | #else |
235 | #define SPRN_IAC1 0x138 /* Book E Instruction Address Compare 1 */ | |
236 | #define SPRN_IAC2 0x139 /* Book E Instruction Address Compare 2 */ | |
237 | #endif /* CONFIG_BOOKE */ | |
935ecca1 WD |
238 | #define SPRN_IBAT0L 0x211 /* Instruction BAT 0 Lower Register */ |
239 | #define SPRN_IBAT0U 0x210 /* Instruction BAT 0 Upper Register */ | |
240 | #define SPRN_IBAT1L 0x213 /* Instruction BAT 1 Lower Register */ | |
241 | #define SPRN_IBAT1U 0x212 /* Instruction BAT 1 Upper Register */ | |
242 | #define SPRN_IBAT2L 0x215 /* Instruction BAT 2 Lower Register */ | |
243 | #define SPRN_IBAT2U 0x214 /* Instruction BAT 2 Upper Register */ | |
244 | #define SPRN_IBAT3L 0x217 /* Instruction BAT 3 Lower Register */ | |
245 | #define SPRN_IBAT3U 0x216 /* Instruction BAT 3 Upper Register */ | |
35656de7 WD |
246 | #define SPRN_IBAT4L 0x231 /* Instruction BAT 4 Lower Register */ |
247 | #define SPRN_IBAT4U 0x230 /* Instruction BAT 4 Upper Register */ | |
248 | #define SPRN_IBAT5L 0x233 /* Instruction BAT 5 Lower Register */ | |
249 | #define SPRN_IBAT5U 0x232 /* Instruction BAT 5 Upper Register */ | |
250 | #define SPRN_IBAT6L 0x235 /* Instruction BAT 6 Lower Register */ | |
251 | #define SPRN_IBAT6U 0x234 /* Instruction BAT 6 Upper Register */ | |
252 | #define SPRN_IBAT7L 0x237 /* Instruction BAT 7 Lower Register */ | |
253 | #define SPRN_IBAT7U 0x236 /* Instruction BAT 7 Upper Register */ | |
935ecca1 WD |
254 | #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ |
255 | #define ICCR_NOCACHE 0 /* Noncacheable */ | |
256 | #define ICCR_CACHE 1 /* Cacheable */ | |
257 | #define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */ | |
258 | #define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */ | |
259 | #define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */ | |
260 | #define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */ | |
261 | #define SPRN_IMMR 0x27E /* Internal Memory Map Register */ | |
262 | #define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */ | |
263 | #define SPRN_LR 0x008 /* Link Register */ | |
264 | #define SPRN_MMCR0 0x3B8 /* Monitor Mode Control Register 0 */ | |
265 | #define SPRN_MMCR1 0x3BC /* Monitor Mode Control Register 1 */ | |
266 | #define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */ | |
267 | #define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */ | |
268 | #define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */ | |
269 | #define SPRN_PBU2 0x3FF /* Protection Bound Upper 2 */ | |
42d1f039 | 270 | #ifndef CONFIG_BOOKE |
935ecca1 WD |
271 | #define SPRN_PID 0x3B1 /* Process ID */ |
272 | #define SPRN_PIR 0x3FF /* Processor Identification Register */ | |
42d1f039 WD |
273 | #else |
274 | #define SPRN_PID 0x030 /* Book E Process ID */ | |
275 | #define SPRN_PIR 0x11E /* Book E Processor Identification Register */ | |
276 | #endif /* CONFIG_BOOKE */ | |
935ecca1 WD |
277 | #define SPRN_PIT 0x3DB /* Programmable Interval Timer */ |
278 | #define SPRN_PMC1 0x3B9 /* Performance Counter Register 1 */ | |
279 | #define SPRN_PMC2 0x3BA /* Performance Counter Register 2 */ | |
280 | #define SPRN_PMC3 0x3BD /* Performance Counter Register 3 */ | |
281 | #define SPRN_PMC4 0x3BE /* Performance Counter Register 4 */ | |
282 | #define SPRN_PVR 0x11F /* Processor Version Register */ | |
283 | #define SPRN_RPA 0x3D6 /* Required Physical Address Register */ | |
284 | #define SPRN_SDA 0x3BF /* Sampled Data Address Register */ | |
285 | #define SPRN_SDR1 0x019 /* MMU Hash Base Register */ | |
286 | #define SPRN_SGR 0x3B9 /* Storage Guarded Register */ | |
287 | #define SGR_NORMAL 0 | |
288 | #define SGR_GUARDED 1 | |
289 | #define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */ | |
290 | #define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */ | |
291 | #define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */ | |
292 | #define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */ | |
293 | #define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */ | |
294 | #define SPRN_SRR0 0x01A /* Save/Restore Register 0 */ | |
295 | #define SPRN_SRR1 0x01B /* Save/Restore Register 1 */ | |
296 | #define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */ | |
297 | #define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */ | |
298 | #define SPRN_TBHI 0x3DC /* Time Base High */ | |
299 | #define SPRN_TBHU 0x3CC /* Time Base High User-mode */ | |
300 | #define SPRN_TBLO 0x3DD /* Time Base Low */ | |
301 | #define SPRN_TBLU 0x3CD /* Time Base Low User-mode */ | |
302 | #define SPRN_TBRL 0x10D /* Time Base Read Lower Register */ | |
303 | #define SPRN_TBRU 0x10C /* Time Base Read Upper Register */ | |
304 | #define SPRN_TBWL 0x11D /* Time Base Write Lower Register */ | |
305 | #define SPRN_TBWU 0x11C /* Time Base Write Upper Register */ | |
42d1f039 | 306 | #ifndef CONFIG_BOOKE |
935ecca1 | 307 | #define SPRN_TCR 0x3DA /* Timer Control Register */ |
42d1f039 WD |
308 | #else |
309 | #define SPRN_TCR 0x154 /* Book E Timer Control Register */ | |
310 | #endif /* CONFIG_BOOKE */ | |
935ecca1 WD |
311 | #define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */ |
312 | #define WP_2_17 0 /* 2^17 clocks */ | |
313 | #define WP_2_21 1 /* 2^21 clocks */ | |
314 | #define WP_2_25 2 /* 2^25 clocks */ | |
315 | #define WP_2_29 3 /* 2^29 clocks */ | |
316 | #define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */ | |
317 | #define WRC_NONE 0 /* No reset will occur */ | |
318 | #define WRC_CORE 1 /* Core reset will occur */ | |
319 | #define WRC_CHIP 2 /* Chip reset will occur */ | |
320 | #define WRC_SYSTEM 3 /* System reset will occur */ | |
321 | #define TCR_WIE 0x08000000 /* WDT Interrupt Enable */ | |
322 | #define TCR_PIE 0x04000000 /* PIT Interrupt Enable */ | |
323 | #define TCR_FP(x) (((x)&0x3)<<24) /* FIT Period */ | |
324 | #define FP_2_9 0 /* 2^9 clocks */ | |
325 | #define FP_2_13 1 /* 2^13 clocks */ | |
326 | #define FP_2_17 2 /* 2^17 clocks */ | |
327 | #define FP_2_21 3 /* 2^21 clocks */ | |
328 | #define TCR_FIE 0x00800000 /* FIT Interrupt Enable */ | |
329 | #define TCR_ARE 0x00400000 /* Auto Reload Enable */ | |
330 | #define SPRN_THRM1 0x3FC /* Thermal Management Register 1 */ | |
331 | #define THRM1_TIN (1<<0) | |
332 | #define THRM1_TIV (1<<1) | |
333 | #define THRM1_THRES (0x7f<<2) | |
334 | #define THRM1_TID (1<<29) | |
335 | #define THRM1_TIE (1<<30) | |
336 | #define THRM1_V (1<<31) | |
337 | #define SPRN_THRM2 0x3FD /* Thermal Management Register 2 */ | |
338 | #define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */ | |
339 | #define THRM3_E (1<<31) | |
42d1f039 WD |
340 | #define SPRN_TLBMISS 0x3D4 /* 980 7450 TLB Miss Register */ |
341 | #ifndef CONFIG_BOOKE | |
935ecca1 | 342 | #define SPRN_TSR 0x3D8 /* Timer Status Register */ |
42d1f039 WD |
343 | #else |
344 | #define SPRN_TSR 0x150 /* Book E Timer Status Register */ | |
345 | #endif /* CONFIG_BOOKE */ | |
935ecca1 WD |
346 | #define TSR_ENW 0x80000000 /* Enable Next Watchdog */ |
347 | #define TSR_WIS 0x40000000 /* WDT Interrupt Status */ | |
348 | #define TSR_WRS(x) (((x)&0x3)<<28) /* WDT Reset Status */ | |
349 | #define WRS_NONE 0 /* No WDT reset occurred */ | |
350 | #define WRS_CORE 1 /* WDT forced core reset */ | |
351 | #define WRS_CHIP 2 /* WDT forced chip reset */ | |
352 | #define WRS_SYSTEM 3 /* WDT forced system reset */ | |
353 | #define TSR_PIS 0x08000000 /* PIT Interrupt Status */ | |
354 | #define TSR_FIS 0x04000000 /* FIT Interrupt Status */ | |
355 | #define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 */ | |
356 | #define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 */ | |
357 | #define SPRN_UPMC1 0x3A9 /* User Performance Counter Register 1 */ | |
358 | #define SPRN_UPMC2 0x3AA /* User Performance Counter Register 2 */ | |
359 | #define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 */ | |
360 | #define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 */ | |
361 | #define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */ | |
362 | #define SPRN_XER 0x001 /* Fixed Point Exception Register */ | |
363 | #define SPRN_ZPR 0x3B0 /* Zone Protection Register */ | |
364 | ||
42d1f039 WD |
365 | /* Book E definitions */ |
366 | #define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */ | |
367 | #define SPRN_CSRR0 0x03A /* Critical SRR0 */ | |
368 | #define SPRN_CSRR1 0x03B /* Critical SRR0 */ | |
369 | #define SPRN_IVPR 0x03F /* Interrupt Vector Prefix Register */ | |
370 | #define SPRN_USPRG0 0x100 /* User Special Purpose Register General 0 */ | |
371 | #define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */ | |
372 | #define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */ | |
373 | #define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */ | |
374 | #define SPRN_SPRG7R 0x107 /* Special Purpose Register General 7 Read */ | |
375 | #define SPRN_SPRG4W 0x114 /* Special Purpose Register General 4 Write */ | |
376 | #define SPRN_SPRG5W 0x115 /* Special Purpose Register General 5 Write */ | |
377 | #define SPRN_SPRG6W 0x116 /* Special Purpose Register General 6 Write */ | |
378 | #define SPRN_SPRG7W 0x117 /* Special Purpose Register General 7 Write */ | |
379 | #define SPRN_DBCR2 0x136 /* Debug Control Register 2 */ | |
380 | #define SPRN_IAC3 0x13A /* Instruction Address Compare 3 */ | |
381 | #define SPRN_IAC4 0x13B /* Instruction Address Compare 4 */ | |
382 | #define SPRN_DVC1 0x13E /* Data Value Compare Register 1 */ | |
383 | #define SPRN_DVC2 0x13F /* Data Value Compare Register 2 */ | |
384 | #define SPRN_IVOR0 0x190 /* Interrupt Vector Offset Register 0 */ | |
385 | #define SPRN_IVOR1 0x191 /* Interrupt Vector Offset Register 1 */ | |
386 | #define SPRN_IVOR2 0x192 /* Interrupt Vector Offset Register 2 */ | |
387 | #define SPRN_IVOR3 0x193 /* Interrupt Vector Offset Register 3 */ | |
388 | #define SPRN_IVOR4 0x194 /* Interrupt Vector Offset Register 4 */ | |
389 | #define SPRN_IVOR5 0x195 /* Interrupt Vector Offset Register 5 */ | |
390 | #define SPRN_IVOR6 0x196 /* Interrupt Vector Offset Register 6 */ | |
391 | #define SPRN_IVOR7 0x197 /* Interrupt Vector Offset Register 7 */ | |
392 | #define SPRN_IVOR8 0x198 /* Interrupt Vector Offset Register 8 */ | |
393 | #define SPRN_IVOR9 0x199 /* Interrupt Vector Offset Register 9 */ | |
394 | #define SPRN_IVOR10 0x19a /* Interrupt Vector Offset Register 10 */ | |
395 | #define SPRN_IVOR11 0x19b /* Interrupt Vector Offset Register 11 */ | |
396 | #define SPRN_IVOR12 0x19c /* Interrupt Vector Offset Register 12 */ | |
397 | #define SPRN_IVOR13 0x19d /* Interrupt Vector Offset Register 13 */ | |
398 | #define SPRN_IVOR14 0x19e /* Interrupt Vector Offset Register 14 */ | |
399 | #define SPRN_IVOR15 0x19f /* Interrupt Vector Offset Register 15 */ | |
400 | ||
401 | /* e500 definitions */ | |
402 | #define SPRN_L1CSR0 0x3f2 /* L1 Cache Control and Status Register 0 */ | |
403 | #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */ | |
404 | #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */ | |
405 | #define SPRN_L1CSR1 0x3f3 /* L1 Cache Control and Status Register 1 */ | |
406 | #define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */ | |
407 | #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */ | |
408 | ||
409 | #define SPRN_MMUCSR0 0x3f4 /* MMU control and status register 0 */ | |
410 | #define SPRN_MAS0 0x270 /* MMU Assist Register 0 */ | |
411 | #define SPRN_MAS1 0x271 /* MMU Assist Register 1 */ | |
412 | #define SPRN_MAS2 0x272 /* MMU Assist Register 2 */ | |
413 | #define SPRN_MAS3 0x273 /* MMU Assist Register 3 */ | |
414 | #define SPRN_MAS4 0x274 /* MMU Assist Register 4 */ | |
415 | #define SPRN_MAS5 0x275 /* MMU Assist Register 5 */ | |
416 | #define SPRN_MAS6 0x276 /* MMU Assist Register 6 */ | |
417 | ||
418 | #define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */ | |
419 | #define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */ | |
420 | #define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */ | |
421 | #define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */ | |
422 | #define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */ | |
423 | ||
424 | #define SPRN_MCSRR0 0x23a /* Machine Check Save and Restore Register 0 */ | |
425 | #define SPRN_MCSRR1 0x23b /* Machine Check Save and Restore Register 1 */ | |
426 | #define SPRN_BUCSR 0x3f5 /* Branch Control and Status Register */ | |
427 | #define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */ | |
428 | #define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */ | |
429 | #define SPRN_PID1 0x279 /* Process ID Register 1 */ | |
430 | #define SPRN_PID2 0x27a /* Process ID Register 2 */ | |
431 | #define SPRN_MCSR 0x23c /* Machine Check Syndrome register */ | |
432 | #define ESR_ST 0x00800000 /* Store Operation */ | |
433 | ||
935ecca1 WD |
434 | /* Short-hand versions for a number of the above SPRNs */ |
435 | ||
436 | #define CTR SPRN_CTR /* Counter Register */ | |
437 | #define DAR SPRN_DAR /* Data Address Register */ | |
438 | #define DABR SPRN_DABR /* Data Address Breakpoint Register */ | |
42d1f039 WD |
439 | #define DAC1 SPRN_DAC1 /* Data Address Register 1 */ |
440 | #define DAC2 SPRN_DAC2 /* Data Address Register 2 */ | |
935ecca1 WD |
441 | #define DBAT0L SPRN_DBAT0L /* Data BAT 0 Lower Register */ |
442 | #define DBAT0U SPRN_DBAT0U /* Data BAT 0 Upper Register */ | |
443 | #define DBAT1L SPRN_DBAT1L /* Data BAT 1 Lower Register */ | |
444 | #define DBAT1U SPRN_DBAT1U /* Data BAT 1 Upper Register */ | |
445 | #define DBAT2L SPRN_DBAT2L /* Data BAT 2 Lower Register */ | |
446 | #define DBAT2U SPRN_DBAT2U /* Data BAT 2 Upper Register */ | |
447 | #define DBAT3L SPRN_DBAT3L /* Data BAT 3 Lower Register */ | |
448 | #define DBAT3U SPRN_DBAT3U /* Data BAT 3 Upper Register */ | |
72755c71 WD |
449 | #define DBAT4L SPRN_DBAT4L /* Data BAT 4 Lower Register */ |
450 | #define DBAT4U SPRN_DBAT4U /* Data BAT 4 Upper Register */ | |
451 | #define DBAT5L SPRN_DBAT5L /* Data BAT 5 Lower Register */ | |
452 | #define DBAT5U SPRN_DBAT5U /* Data BAT 5 Upper Register */ | |
453 | #define DBAT6L SPRN_DBAT6L /* Data BAT 6 Lower Register */ | |
454 | #define DBAT6U SPRN_DBAT6U /* Data BAT 6 Upper Register */ | |
455 | #define DBAT7L SPRN_DBAT7L /* Data BAT 7 Lower Register */ | |
456 | #define DBAT7U SPRN_DBAT7U /* Data BAT 7 Upper Register */ | |
42d1f039 WD |
457 | #define DBCR0 SPRN_DBCR0 /* Debug Control Register 0 */ |
458 | #define DBCR1 SPRN_DBCR1 /* Debug Control Register 1 */ | |
459 | #define DBSR SPRN_DBSR /* Debug Status Register */ | |
935ecca1 WD |
460 | #define DCMP SPRN_DCMP /* Data TLB Compare Register */ |
461 | #define DEC SPRN_DEC /* Decrement Register */ | |
462 | #define DMISS SPRN_DMISS /* Data TLB Miss Register */ | |
463 | #define DSISR SPRN_DSISR /* Data Storage Interrupt Status Register */ | |
464 | #define EAR SPRN_EAR /* External Address Register */ | |
42d1f039 | 465 | #define ESR SPRN_ESR /* Exception Syndrome Register */ |
935ecca1 WD |
466 | #define HASH1 SPRN_HASH1 /* Primary Hash Address Register */ |
467 | #define HASH2 SPRN_HASH2 /* Secondary Hash Address Register */ | |
468 | #define HID0 SPRN_HID0 /* Hardware Implementation Register 0 */ | |
469 | #define HID1 SPRN_HID1 /* Hardware Implementation Register 1 */ | |
470 | #define IABR SPRN_IABR /* Instruction Address Breakpoint Register */ | |
42d1f039 WD |
471 | #define IAC1 SPRN_IAC1 /* Instruction Address Register 1 */ |
472 | #define IAC2 SPRN_IAC2 /* Instruction Address Register 2 */ | |
935ecca1 WD |
473 | #define IBAT0L SPRN_IBAT0L /* Instruction BAT 0 Lower Register */ |
474 | #define IBAT0U SPRN_IBAT0U /* Instruction BAT 0 Upper Register */ | |
475 | #define IBAT1L SPRN_IBAT1L /* Instruction BAT 1 Lower Register */ | |
476 | #define IBAT1U SPRN_IBAT1U /* Instruction BAT 1 Upper Register */ | |
477 | #define IBAT2L SPRN_IBAT2L /* Instruction BAT 2 Lower Register */ | |
478 | #define IBAT2U SPRN_IBAT2U /* Instruction BAT 2 Upper Register */ | |
479 | #define IBAT3L SPRN_IBAT3L /* Instruction BAT 3 Lower Register */ | |
480 | #define IBAT3U SPRN_IBAT3U /* Instruction BAT 3 Upper Register */ | |
72755c71 WD |
481 | #define IBAT4L SPRN_IBAT4L /* Instruction BAT 4 Lower Register */ |
482 | #define IBAT4U SPRN_IBAT4U /* Instruction BAT 4 Upper Register */ | |
483 | #define IBAT5L SPRN_IBAT5L /* Instruction BAT 5 Lower Register */ | |
484 | #define IBAT5U SPRN_IBAT5U /* Instruction BAT 5 Upper Register */ | |
485 | #define IBAT6L SPRN_IBAT6L /* Instruction BAT 6 Lower Register */ | |
486 | #define IBAT6U SPRN_IBAT6U /* Instruction BAT 6 Upper Register */ | |
487 | #define IBAT7L SPRN_IBAT7L /* Instruction BAT 7 Lower Register */ | |
488 | #define IBAT7U SPRN_IBAT7U /* Instruction BAT 7 Lower Register */ | |
935ecca1 WD |
489 | #define ICMP SPRN_ICMP /* Instruction TLB Compare Register */ |
490 | #define IMISS SPRN_IMISS /* Instruction TLB Miss Register */ | |
491 | #define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */ | |
492 | #define L2CR SPRN_L2CR /* PPC 750 L2 control register */ | |
493 | #define LR SPRN_LR | |
42d1f039 WD |
494 | #if defined(CONFIG_E500) |
495 | #define PIR SPRN_PIR | |
496 | #endif | |
935ecca1 WD |
497 | #define PVR SPRN_PVR /* Processor Version */ |
498 | #define RPA SPRN_RPA /* Required Physical Address Register */ | |
499 | #define SDR1 SPRN_SDR1 /* MMU hash base register */ | |
500 | #define SPR0 SPRN_SPRG0 /* Supervisor Private Registers */ | |
501 | #define SPR1 SPRN_SPRG1 | |
502 | #define SPR2 SPRN_SPRG2 | |
503 | #define SPR3 SPRN_SPRG3 | |
504 | #define SPRG0 SPRN_SPRG0 | |
505 | #define SPRG1 SPRN_SPRG1 | |
506 | #define SPRG2 SPRN_SPRG2 | |
507 | #define SPRG3 SPRN_SPRG3 | |
508 | #define SRR0 SPRN_SRR0 /* Save and Restore Register 0 */ | |
509 | #define SRR1 SPRN_SRR1 /* Save and Restore Register 1 */ | |
510 | #define TBRL SPRN_TBRL /* Time Base Read Lower Register */ | |
511 | #define TBRU SPRN_TBRU /* Time Base Read Upper Register */ | |
512 | #define TBWL SPRN_TBWL /* Time Base Write Lower Register */ | |
513 | #define TBWU SPRN_TBWU /* Time Base Write Upper Register */ | |
42d1f039 WD |
514 | #define TCR SPRN_TCR /* Timer Control Register */ |
515 | #define TSR SPRN_TSR /* Timer Status Register */ | |
935ecca1 WD |
516 | #define ICTC 1019 |
517 | #define THRM1 SPRN_THRM1 /* Thermal Management Register 1 */ | |
518 | #define THRM2 SPRN_THRM2 /* Thermal Management Register 2 */ | |
519 | #define THRM3 SPRN_THRM3 /* Thermal Management Register 3 */ | |
520 | #define XER SPRN_XER | |
521 | ||
42d1f039 WD |
522 | #define DECAR SPRN_DECAR |
523 | #define CSRR0 SPRN_CSRR0 | |
524 | #define CSRR1 SPRN_CSRR1 | |
525 | #define IVPR SPRN_IVPR | |
526 | #define USPRG0 SPRN_USPRG0 | |
527 | #define SPRG4R SPRN_SPRG4R | |
528 | #define SPRG5R SPRN_SPRG5R | |
529 | #define SPRG6R SPRN_SPRG6R | |
530 | #define SPRG7R SPRN_SPRG7R | |
531 | #define SPRG4W SPRN_SPRG4W | |
532 | #define SPRG5W SPRN_SPRG5W | |
533 | #define SPRG6W SPRN_SPRG6W | |
534 | #define SPRG7W SPRN_SPRG7W | |
535 | #define DEAR SPRN_DEAR | |
536 | #define DBCR2 SPRN_DBCR2 | |
537 | #define IAC3 SPRN_IAC3 | |
538 | #define IAC4 SPRN_IAC4 | |
539 | #define DVC1 SPRN_DVC1 | |
540 | #define DVC2 SPRN_DVC2 | |
541 | #define IVOR0 SPRN_IVOR0 | |
542 | #define IVOR1 SPRN_IVOR1 | |
543 | #define IVOR2 SPRN_IVOR2 | |
544 | #define IVOR3 SPRN_IVOR3 | |
545 | #define IVOR4 SPRN_IVOR4 | |
546 | #define IVOR5 SPRN_IVOR5 | |
547 | #define IVOR6 SPRN_IVOR6 | |
548 | #define IVOR7 SPRN_IVOR7 | |
549 | #define IVOR8 SPRN_IVOR8 | |
550 | #define IVOR9 SPRN_IVOR9 | |
551 | #define IVOR10 SPRN_IVOR10 | |
552 | #define IVOR11 SPRN_IVOR11 | |
553 | #define IVOR12 SPRN_IVOR12 | |
554 | #define IVOR13 SPRN_IVOR13 | |
555 | #define IVOR14 SPRN_IVOR14 | |
556 | #define IVOR15 SPRN_IVOR15 | |
557 | #define IVOR32 SPRN_IVOR32 | |
558 | #define IVOR33 SPRN_IVOR33 | |
559 | #define IVOR34 SPRN_IVOR34 | |
560 | #define IVOR35 SPRN_IVOR35 | |
561 | #define MCSRR0 SPRN_MCSRR0 | |
562 | #define MCSRR1 SPRN_MCSRR1 | |
563 | #define L1CSR0 SPRN_L1CSR0 | |
564 | #define L1CSR1 SPRN_L1CSR1 | |
565 | #define MCSR SPRN_MCSR | |
566 | #define MMUCSR0 SPRN_MMUCSR0 | |
567 | #define BUCSR SPRN_BUCSR | |
568 | #define PID0 SPRN_PID | |
569 | #define PID1 SPRN_PID1 | |
570 | #define PID2 SPRN_PID2 | |
571 | #define MAS0 SPRN_MAS0 | |
572 | #define MAS1 SPRN_MAS1 | |
573 | #define MAS2 SPRN_MAS2 | |
574 | #define MAS3 SPRN_MAS3 | |
575 | #define MAS4 SPRN_MAS4 | |
576 | #define MAS5 SPRN_MAS5 | |
577 | #define MAS6 SPRN_MAS6 | |
935ecca1 WD |
578 | |
579 | /* Device Control Registers */ | |
580 | ||
581 | #define DCRN_BEAR 0x090 /* Bus Error Address Register */ | |
582 | #define DCRN_BESR 0x091 /* Bus Error Syndrome Register */ | |
583 | #define BESR_DSES 0x80000000 /* Data-Side Error Status */ | |
584 | #define BESR_DMES 0x40000000 /* DMA Error Status */ | |
585 | #define BESR_RWS 0x20000000 /* Read/Write Status */ | |
586 | #define BESR_ETMASK 0x1C000000 /* Error Type */ | |
587 | #define ET_PROT 0 | |
588 | #define ET_PARITY 1 | |
589 | #define ET_NCFG 2 | |
590 | #define ET_BUSERR 4 | |
591 | #define ET_BUSTO 6 | |
592 | #define DCRN_DMACC0 0x0C4 /* DMA Chained Count Register 0 */ | |
593 | #define DCRN_DMACC1 0x0CC /* DMA Chained Count Register 1 */ | |
594 | #define DCRN_DMACC2 0x0D4 /* DMA Chained Count Register 2 */ | |
595 | #define DCRN_DMACC3 0x0DC /* DMA Chained Count Register 3 */ | |
596 | #define DCRN_DMACR0 0x0C0 /* DMA Channel Control Register 0 */ | |
597 | #define DCRN_DMACR1 0x0C8 /* DMA Channel Control Register 1 */ | |
598 | #define DCRN_DMACR2 0x0D0 /* DMA Channel Control Register 2 */ | |
599 | #define DCRN_DMACR3 0x0D8 /* DMA Channel Control Register 3 */ | |
600 | #define DCRN_DMACT0 0x0C1 /* DMA Count Register 0 */ | |
601 | #define DCRN_DMACT1 0x0C9 /* DMA Count Register 1 */ | |
602 | #define DCRN_DMACT2 0x0D1 /* DMA Count Register 2 */ | |
603 | #define DCRN_DMACT3 0x0D9 /* DMA Count Register 3 */ | |
604 | #define DCRN_DMADA0 0x0C2 /* DMA Destination Address Register 0 */ | |
605 | #define DCRN_DMADA1 0x0CA /* DMA Destination Address Register 1 */ | |
606 | #define DCRN_DMADA2 0x0D2 /* DMA Destination Address Register 2 */ | |
607 | #define DCRN_DMADA3 0x0DA /* DMA Destination Address Register 3 */ | |
608 | #define DCRN_DMASA0 0x0C3 /* DMA Source Address Register 0 */ | |
609 | #define DCRN_DMASA1 0x0CB /* DMA Source Address Register 1 */ | |
610 | #define DCRN_DMASA2 0x0D3 /* DMA Source Address Register 2 */ | |
611 | #define DCRN_DMASA3 0x0DB /* DMA Source Address Register 3 */ | |
612 | #define DCRN_DMASR 0x0E0 /* DMA Status Register */ | |
613 | #define DCRN_EXIER 0x042 /* External Interrupt Enable Register */ | |
614 | #define EXIER_CIE 0x80000000 /* Critical Interrupt Enable */ | |
615 | #define EXIER_SRIE 0x08000000 /* Serial Port Rx Int. Enable */ | |
616 | #define EXIER_STIE 0x04000000 /* Serial Port Tx Int. Enable */ | |
617 | #define EXIER_JRIE 0x02000000 /* JTAG Serial Port Rx Int. Enable */ | |
618 | #define EXIER_JTIE 0x01000000 /* JTAG Serial Port Tx Int. Enable */ | |
619 | #define EXIER_D0IE 0x00800000 /* DMA Channel 0 Interrupt Enable */ | |
620 | #define EXIER_D1IE 0x00400000 /* DMA Channel 1 Interrupt Enable */ | |
621 | #define EXIER_D2IE 0x00200000 /* DMA Channel 2 Interrupt Enable */ | |
622 | #define EXIER_D3IE 0x00100000 /* DMA Channel 3 Interrupt Enable */ | |
623 | #define EXIER_E0IE 0x00000010 /* External Interrupt 0 Enable */ | |
624 | #define EXIER_E1IE 0x00000008 /* External Interrupt 1 Enable */ | |
625 | #define EXIER_E2IE 0x00000004 /* External Interrupt 2 Enable */ | |
626 | #define EXIER_E3IE 0x00000002 /* External Interrupt 3 Enable */ | |
627 | #define EXIER_E4IE 0x00000001 /* External Interrupt 4 Enable */ | |
628 | #define DCRN_EXISR 0x040 /* External Interrupt Status Register */ | |
629 | #define DCRN_IOCR 0x0A0 /* Input/Output Configuration Register */ | |
630 | #define IOCR_E0TE 0x80000000 | |
631 | #define IOCR_E0LP 0x40000000 | |
632 | #define IOCR_E1TE 0x20000000 | |
633 | #define IOCR_E1LP 0x10000000 | |
634 | #define IOCR_E2TE 0x08000000 | |
635 | #define IOCR_E2LP 0x04000000 | |
636 | #define IOCR_E3TE 0x02000000 | |
637 | #define IOCR_E3LP 0x01000000 | |
638 | #define IOCR_E4TE 0x00800000 | |
639 | #define IOCR_E4LP 0x00400000 | |
640 | #define IOCR_EDT 0x00080000 | |
641 | #define IOCR_SOR 0x00040000 | |
642 | #define IOCR_EDO 0x00008000 | |
643 | #define IOCR_2XC 0x00004000 | |
644 | #define IOCR_ATC 0x00002000 | |
645 | #define IOCR_SPD 0x00001000 | |
646 | #define IOCR_BEM 0x00000800 | |
647 | #define IOCR_PTD 0x00000400 | |
648 | #define IOCR_ARE 0x00000080 | |
649 | #define IOCR_DRC 0x00000020 | |
650 | #define IOCR_RDM(x) (((x) & 0x3) << 3) | |
651 | #define IOCR_TCS 0x00000004 | |
652 | #define IOCR_SCS 0x00000002 | |
653 | #define IOCR_SPC 0x00000001 | |
654 | ||
655 | ||
656 | /* Processor Version Register */ | |
657 | ||
658 | /* Processor Version Register (PVR) field extraction */ | |
659 | ||
660 | #define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */ | |
661 | #define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */ | |
662 | ||
663 | /* | |
664 | * IBM has further subdivided the standard PowerPC 16-bit version and | |
665 | * revision subfields of the PVR for the PowerPC 403s into the following: | |
666 | */ | |
667 | ||
668 | #define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */ | |
669 | #define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */ | |
670 | #define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */ | |
671 | #define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */ | |
672 | #define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */ | |
673 | #define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */ | |
674 | ||
675 | /* Processor Version Numbers */ | |
676 | ||
677 | #define PVR_403GA 0x00200000 | |
678 | #define PVR_403GB 0x00200100 | |
679 | #define PVR_403GC 0x00200200 | |
680 | #define PVR_403GCX 0x00201400 | |
681 | #define PVR_405GP 0x40110000 | |
682 | #define PVR_405GP_RB 0x40110040 | |
683 | #define PVR_405GP_RC 0x40110082 | |
684 | #define PVR_405GP_RD 0x401100C4 | |
685 | #define PVR_405GP_RE 0x40110145 /* same as pc405cr rev c */ | |
686 | #define PVR_405CR_RA 0x40110041 | |
687 | #define PVR_405CR_RB 0x401100C5 | |
688 | #define PVR_405CR_RC 0x40110145 /* same as pc405gp rev e */ | |
12f34241 | 689 | #define PVR_405EP_RA 0x51210950 |
baa3d528 | 690 | #define PVR_405GPR_RB 0x50910951 |
935ecca1 WD |
691 | #define PVR_440GP_RB 0x40120440 |
692 | #define PVR_440GP_RC 0x40120481 | |
ba56f625 WD |
693 | #define PVR_440GX_RA 0x51B21850 |
694 | #define PVR_440GX_RB 0x51B21851 | |
b867d705 | 695 | #define PVR_405EP_RB 0x51210950 |
935ecca1 WD |
696 | #define PVR_601 0x00010000 |
697 | #define PVR_602 0x00050000 | |
698 | #define PVR_603 0x00030000 | |
699 | #define PVR_603e 0x00060000 | |
700 | #define PVR_603ev 0x00070000 | |
701 | #define PVR_603r 0x00071000 | |
702 | #define PVR_604 0x00040000 | |
703 | #define PVR_604e 0x00090000 | |
704 | #define PVR_604r 0x000A0000 | |
705 | #define PVR_620 0x00140000 | |
706 | #define PVR_740 0x00080000 | |
707 | #define PVR_750 PVR_740 | |
708 | #define PVR_740P 0x10080000 | |
709 | #define PVR_750P PVR_740P | |
42d1f039 WD |
710 | #define PVR_7400 0x000C0000 |
711 | #define PVR_7410 0x800C0000 | |
712 | #define PVR_7450 0x80000000 | |
713 | #define PVR_8540 0x80200010 | |
714 | #define PVR_8560 0x80200010 | |
715 | ||
935ecca1 WD |
716 | /* |
717 | * For the 8xx processors, all of them report the same PVR family for | |
718 | * the PowerPC core. The various versions of these processors must be | |
719 | * differentiated by the version number in the Communication Processor | |
720 | * Module (CPM). | |
721 | */ | |
722 | #define PVR_821 0x00500000 | |
723 | #define PVR_823 PVR_821 | |
724 | #define PVR_850 PVR_821 | |
725 | #define PVR_860 PVR_821 | |
726 | #define PVR_7400 0x000C0000 | |
727 | #define PVR_8240 0x00810100 | |
935ecca1 | 728 | |
8564acf9 WD |
729 | /* |
730 | * PowerQUICC II family processors report different PVR values depending | |
731 | * on silicon process (HiP3, HiP4, HiP7, etc.) | |
732 | */ | |
733 | #define PVR_8260 PVR_8240 | |
734 | #define PVR_8260_HIP3 0x00810101 | |
735 | #define PVR_8260_HIP4 0x80811014 | |
736 | #define PVR_8260_HIP7 0x80822011 | |
5779d8d9 | 737 | #define PVR_8260_HIP7R1 0x80822013 |
935ecca1 WD |
738 | |
739 | /* I am just adding a single entry for 8260 boards. I think we may be | |
740 | * able to combine mbx, fads, rpxlite, bseip, and classic into a single | |
741 | * generic 8xx as well. The boards containing these processors are either | |
742 | * identical at the processor level (due to the high integration) or so | |
743 | * wildly different that testing _machine at run time is best replaced by | |
744 | * conditional compilation by board type (found in their respective .h file). | |
745 | * -- Dan | |
746 | */ | |
747 | #define _MACH_prep 0x00000001 | |
748 | #define _MACH_Pmac 0x00000002 /* pmac or pmac clone (non-chrp) */ | |
749 | #define _MACH_chrp 0x00000004 /* chrp machine */ | |
750 | #define _MACH_mbx 0x00000008 /* Motorola MBX board */ | |
751 | #define _MACH_apus 0x00000010 /* amiga with phase5 powerup */ | |
752 | #define _MACH_fads 0x00000020 /* Motorola FADS board */ | |
753 | #define _MACH_rpxlite 0x00000040 /* RPCG RPX-Lite 8xx board */ | |
754 | #define _MACH_bseip 0x00000080 /* Bright Star Engineering ip-Engine */ | |
755 | #define _MACH_yk 0x00000100 /* Motorola Yellowknife */ | |
756 | #define _MACH_gemini 0x00000200 /* Synergy Microsystems gemini board */ | |
757 | #define _MACH_classic 0x00000400 /* RPCG RPX-Classic 8xx board */ | |
758 | #define _MACH_oak 0x00000800 /* IBM "Oak" 403 eval. board */ | |
759 | #define _MACH_walnut 0x00001000 /* IBM "Walnut" 405GP eval. board */ | |
760 | #define _MACH_8260 0x00002000 /* Generic 8260 */ | |
761 | #define _MACH_sandpoint 0x00004000 /* Motorola SPS Processor eval board */ | |
762 | #define _MACH_tqm860 0x00008000 /* TQM860/L */ | |
763 | #define _MACH_tqm8xxL 0x00010000 /* TQM8xxL */ | |
764 | ||
765 | ||
766 | /* see residual.h for these */ | |
767 | #define _PREP_Motorola 0x01 /* motorola prep */ | |
768 | #define _PREP_Firm 0x02 /* firmworks prep */ | |
769 | #define _PREP_IBM 0x00 /* ibm prep */ | |
770 | #define _PREP_Bull 0x03 /* bull prep */ | |
771 | #define _PREP_Radstone 0x04 /* Radstone Technology PLC prep */ | |
772 | ||
773 | /* | |
774 | * Radstone board types | |
775 | */ | |
776 | #define RS_SYS_TYPE_PPC1 0 | |
777 | #define RS_SYS_TYPE_PPC2 1 | |
778 | #define RS_SYS_TYPE_PPC1a 2 | |
779 | #define RS_SYS_TYPE_PPC2a 3 | |
780 | #define RS_SYS_TYPE_PPC4 4 | |
781 | #define RS_SYS_TYPE_PPC4a 5 | |
782 | #define RS_SYS_TYPE_PPC2ep 6 | |
783 | ||
784 | /* these are arbitrary */ | |
785 | #define _CHRP_Motorola 0x04 /* motorola chrp, the cobra */ | |
786 | #define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */ | |
787 | ||
788 | #define _GLOBAL(n)\ | |
789 | .globl n;\ | |
790 | n: | |
791 | ||
792 | /* Macros for setting and retrieving special purpose registers */ | |
793 | ||
794 | #define stringify(s) tostring(s) | |
795 | #define tostring(s) #s | |
796 | ||
797 | #define mfdcr(rn) ({unsigned int rval; \ | |
798 | asm volatile("mfdcr %0," stringify(rn) \ | |
799 | : "=r" (rval)); rval;}) | |
800 | #define mtdcr(rn, v) asm volatile("mtdcr " stringify(rn) ",%0" : : "r" (v)) | |
801 | ||
802 | #define mfmsr() ({unsigned int rval; \ | |
803 | asm volatile("mfmsr %0" : "=r" (rval)); rval;}) | |
804 | #define mtmsr(v) asm volatile("mtmsr %0" : : "r" (v)) | |
805 | ||
806 | #define mfspr(rn) ({unsigned int rval; \ | |
807 | asm volatile("mfspr %0," stringify(rn) \ | |
808 | : "=r" (rval)); rval;}) | |
809 | #define mtspr(rn, v) asm volatile("mtspr " stringify(rn) ",%0" : : "r" (v)) | |
810 | ||
811 | #define tlbie(v) asm volatile("tlbie %0 \n sync" : : "r" (v)) | |
812 | ||
813 | /* Segment Registers */ | |
814 | ||
815 | #define SR0 0 | |
816 | #define SR1 1 | |
817 | #define SR2 2 | |
818 | #define SR3 3 | |
819 | #define SR4 4 | |
820 | #define SR5 5 | |
821 | #define SR6 6 | |
822 | #define SR7 7 | |
823 | #define SR8 8 | |
824 | #define SR9 9 | |
825 | #define SR10 10 | |
826 | #define SR11 11 | |
827 | #define SR12 12 | |
828 | #define SR13 13 | |
829 | #define SR14 14 | |
830 | #define SR15 15 | |
831 | ||
832 | #ifndef __ASSEMBLY__ | |
833 | #ifndef CONFIG_MACH_SPECIFIC | |
834 | extern int _machine; | |
835 | extern int have_of; | |
836 | #endif /* CONFIG_MACH_SPECIFIC */ | |
837 | ||
838 | /* what kind of prep workstation we are */ | |
839 | extern int _prep_type; | |
840 | /* | |
841 | * This is used to identify the board type from a given PReP board | |
842 | * vendor. Board revision is also made available. | |
843 | */ | |
844 | extern unsigned char ucSystemType; | |
845 | extern unsigned char ucBoardRev; | |
846 | extern unsigned char ucBoardRevMaj, ucBoardRevMin; | |
847 | ||
848 | struct task_struct; | |
849 | void start_thread(struct pt_regs *regs, unsigned long nip, unsigned long sp); | |
850 | void release_thread(struct task_struct *); | |
851 | ||
852 | /* | |
853 | * Create a new kernel thread. | |
854 | */ | |
855 | extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags); | |
856 | ||
857 | /* | |
858 | * Bus types | |
859 | */ | |
860 | #define EISA_bus 0 | |
861 | #define EISA_bus__is_a_macro /* for versions in ksyms.c */ | |
862 | #define MCA_bus 0 | |
863 | #define MCA_bus__is_a_macro /* for versions in ksyms.c */ | |
864 | ||
865 | /* Lazy FPU handling on uni-processor */ | |
866 | extern struct task_struct *last_task_used_math; | |
867 | extern struct task_struct *last_task_used_altivec; | |
868 | ||
869 | /* | |
870 | * this is the minimum allowable io space due to the location | |
871 | * of the io areas on prep (first one at 0x80000000) but | |
872 | * as soon as I get around to remapping the io areas with the BATs | |
873 | * to match the mac we can raise this. -- Cort | |
874 | */ | |
875 | #define TASK_SIZE (0x80000000UL) | |
876 | ||
877 | /* This decides where the kernel will search for a free chunk of vm | |
878 | * space during mmap's. | |
879 | */ | |
880 | #define TASK_UNMAPPED_BASE (TASK_SIZE / 8 * 3) | |
881 | ||
882 | typedef struct { | |
883 | unsigned long seg; | |
884 | } mm_segment_t; | |
885 | ||
886 | struct thread_struct { | |
887 | unsigned long ksp; /* Kernel stack pointer */ | |
888 | unsigned long wchan; /* Event task is sleeping on */ | |
889 | struct pt_regs *regs; /* Pointer to saved register state */ | |
890 | mm_segment_t fs; /* for get_fs() validation */ | |
891 | void *pgdir; /* root of page-table tree */ | |
892 | signed long last_syscall; | |
893 | double fpr[32]; /* Complete floating point set */ | |
894 | unsigned long fpscr_pad; /* fpr ... fpscr must be contiguous */ | |
895 | unsigned long fpscr; /* Floating point status */ | |
896 | #ifdef CONFIG_ALTIVEC | |
897 | vector128 vr[32]; /* Complete AltiVec set */ | |
898 | vector128 vscr; /* AltiVec status */ | |
899 | unsigned long vrsave; | |
900 | #endif /* CONFIG_ALTIVEC */ | |
901 | }; | |
902 | ||
903 | #define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack) | |
904 | ||
905 | #define INIT_THREAD { \ | |
906 | INIT_SP, /* ksp */ \ | |
907 | 0, /* wchan */ \ | |
908 | (struct pt_regs *)INIT_SP - 1, /* regs */ \ | |
909 | KERNEL_DS, /*fs*/ \ | |
910 | swapper_pg_dir, /* pgdir */ \ | |
911 | 0, /* last_syscall */ \ | |
912 | {0}, 0, 0 \ | |
913 | } | |
914 | ||
915 | /* | |
916 | * Note: the vm_start and vm_end fields here should *not* | |
917 | * be in kernel space. (Could vm_end == vm_start perhaps?) | |
918 | */ | |
919 | #define INIT_MMAP { &init_mm, 0, 0x1000, NULL, \ | |
920 | PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, \ | |
921 | 1, NULL, NULL } | |
922 | ||
923 | /* | |
924 | * Return saved PC of a blocked thread. For now, this is the "user" PC | |
925 | */ | |
926 | static inline unsigned long thread_saved_pc(struct thread_struct *t) | |
927 | { | |
928 | return (t->regs) ? t->regs->nip : 0; | |
929 | } | |
930 | ||
931 | #define copy_segments(tsk, mm) do { } while (0) | |
932 | #define release_segments(mm) do { } while (0) | |
933 | #define forget_segments() do { } while (0) | |
934 | ||
935 | unsigned long get_wchan(struct task_struct *p); | |
936 | ||
937 | #define KSTK_EIP(tsk) ((tsk)->thread.regs->nip) | |
938 | #define KSTK_ESP(tsk) ((tsk)->thread.regs->gpr[1]) | |
939 | ||
940 | /* | |
941 | * NOTE! The task struct and the stack go together | |
942 | */ | |
943 | #define THREAD_SIZE (2*PAGE_SIZE) | |
944 | #define alloc_task_struct() \ | |
945 | ((struct task_struct *) __get_free_pages(GFP_KERNEL,1)) | |
946 | #define free_task_struct(p) free_pages((unsigned long)(p),1) | |
947 | #define get_task_struct(tsk) atomic_inc(&mem_map[MAP_NR(tsk)].count) | |
948 | ||
949 | /* in process.c - for early bootup debug -- Cort */ | |
950 | int ll_printk(const char *, ...); | |
951 | void ll_puts(const char *); | |
952 | ||
953 | #define init_task (init_task_union.task) | |
954 | #define init_stack (init_task_union.stack) | |
955 | ||
956 | /* In misc.c */ | |
957 | void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val); | |
958 | ||
959 | #endif /* ndef ASSEMBLY*/ | |
960 | ||
961 | #ifdef CONFIG_MACH_SPECIFIC | |
962 | #if defined(CONFIG_8xx) | |
963 | #define _machine _MACH_8xx | |
964 | #define have_of 0 | |
965 | #elif defined(CONFIG_OAK) | |
966 | #define _machine _MACH_oak | |
967 | #define have_of 0 | |
968 | #elif defined(CONFIG_WALNUT) | |
969 | #define _machine _MACH_walnut | |
970 | #define have_of 0 | |
971 | #elif defined(CONFIG_APUS) | |
972 | #define _machine _MACH_apus | |
973 | #define have_of 0 | |
974 | #elif defined(CONFIG_GEMINI) | |
975 | #define _machine _MACH_gemini | |
976 | #define have_of 0 | |
977 | #elif defined(CONFIG_8260) | |
978 | #define _machine _MACH_8260 | |
979 | #define have_of 0 | |
980 | #elif defined(CONFIG_SANDPOINT) | |
981 | #define _machine _MACH_sandpoint | |
982 | #define have_of 0 | |
983 | #else | |
984 | #error "Machine not defined correctly" | |
985 | #endif | |
986 | #endif /* CONFIG_MACH_SPECIFIC */ | |
987 | ||
988 | #endif /* __ASM_PPC_PROCESSOR_H */ |