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fe8c2806
WD		 1/*
2 * MPC8xx Communication Processor Module.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 *
8cba090c 5 * (C) Copyright 2000-2006
d4ca31c4
WD		 6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 *
fe8c2806
WD		 8 * This file contains structures and information for the communication
9 * processor channels. Some CPM control and status is available
10 * throught the MPC8xx internal memory map. See immap.h for details.
11 * This file only contains what I need for the moment, not the total
12 * CPM capabilities. I (or someone else) will add definitions as they
13 * are needed. -- Dan
14 *
fe8c2806
WD		 15 */
16#ifndef __CPM_8XX__
17#define __CPM_8XX__
18
fe8c2806
WD		 19#include <asm/8xx_immap.h>
20
21/* CPM Command register.
22*/
7c7a23bd
WD		 23#define CPM_CR_RST ((ushort)0x8000)
24#define CPM_CR_OPCODE ((ushort)0x0f00)
25#define CPM_CR_CHAN ((ushort)0x00f0)
26#define CPM_CR_FLG ((ushort)0x0001)
fe8c2806
WD		 27
28/* Some commands (there are more...later)
29*/
30#define CPM_CR_INIT_TRX ((ushort)0x0000)
31#define CPM_CR_INIT_RX ((ushort)0x0001)
32#define CPM_CR_INIT_TX ((ushort)0x0002)
33#define CPM_CR_HUNT_MODE ((ushort)0x0003)
34#define CPM_CR_STOP_TX ((ushort)0x0004)
35#define CPM_CR_RESTART_TX ((ushort)0x0006)
36#define CPM_CR_SET_GADDR ((ushort)0x0008)
37
38/* Channel numbers.
39*/
7c7a23bd
WD		 40#define CPM_CR_CH_SCC1 ((ushort)0x0000)
41#define CPM_CR_CH_I2C ((ushort)0x0001) /* I2C and IDMA1 */
42#define CPM_CR_CH_SCC2 ((ushort)0x0004)
43#define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI/IDMA2/Timers */
44#define CPM_CR_CH_SCC3 ((ushort)0x0008)
45#define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / DSP1 */
46#define CPM_CR_CH_SCC4 ((ushort)0x000c)
47#define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / DSP2 */
fe8c2806
WD		 48
49#define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4))
50
51/*
52 * DPRAM defines and allocation functions
53 */
fe8c2806
WD		 54#define CPM_SERIAL_BASE 0x0800
55#define CPM_I2C_BASE 0x0820
56#define CPM_SPI_BASE 0x0840
57#define CPM_FEC_BASE 0x0860
79536a6e 58#define CPM_SERIAL2_BASE 0x08E0
fe8c2806
WD		 59#define CPM_SCC_BASE 0x0900
60#define CPM_POST_BASE 0x0980
281e00a3 61#define CPM_WLKBD_BASE 0x0a00
fe8c2806 62
6d0f6bcf 63#ifndef CONFIG_SYS_CPM_POST_WORD_ADDR
fe8c2806 64#define CPM_POST_WORD_ADDR 0x07FC
ea909b76 65#else
6d0f6bcf 66#define CPM_POST_WORD_ADDR CONFIG_SYS_CPM_POST_WORD_ADDR
ea909b76 67#endif
fe8c2806 68
6d0f6bcf 69#ifndef CONFIG_SYS_CPM_BOOTCOUNT_ADDR
bdccc4fe
WD		 70#define CPM_BOOTCOUNT_ADDR (CPM_POST_WORD_ADDR - 2*sizeof(ulong))
71#else
6d0f6bcf 72#define CPM_BOOTCOUNT_ADDR CONFIG_SYS_CPM_BOOTCOUNT_ADDR
bdccc4fe
WD		 73#endif
74
fe8c2806
WD		 75#define BD_IIC_START ((uint) 0x0400) /* <- please use CPM_I2C_BASE !! */
76
77/* Export the base address of the communication processor registers
78 * and dual port ram.
79 */
80extern cpm8xx_t *cpmp; /* Pointer to comm processor */
81
82/* Buffer descriptors used by many of the CPM protocols.
83*/
84typedef struct cpm_buf_desc {
85 ushort cbd_sc; /* Status and Control */
86 ushort cbd_datlen; /* Data length in buffer */
87 uint cbd_bufaddr; /* Buffer address in host memory */
88} cbd_t;
89
16263087 90#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
fe8c2806
WD		 91#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
92#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
93#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
94#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */
95#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */
96#define BD_SC_CM ((ushort)0x0200) /* Continous mode */
97#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
98#define BD_SC_P ((ushort)0x0100) /* xmt preamble */
99#define BD_SC_BR ((ushort)0x0020) /* Break received */
100#define BD_SC_FR ((ushort)0x0010) /* Framing error */
101#define BD_SC_PR ((ushort)0x0008) /* Parity error */
102#define BD_SC_OV ((ushort)0x0002) /* Overrun */
103#define BD_SC_CD ((ushort)0x0001) /* Carrier Detect lost */
104
105/* Parameter RAM offsets.
106*/
107#define PROFF_SCC1 ((uint)0x0000)
108#define PROFF_IIC ((uint)0x0080)
a166fbca 109#define PROFF_REVNUM ((uint)0x00b0)
fe8c2806
WD		 110#define PROFF_SCC2 ((uint)0x0100)
111#define PROFF_SPI ((uint)0x0180)
112#define PROFF_SCC3 ((uint)0x0200)
113#define PROFF_SMC1 ((uint)0x0280)
114#define PROFF_SCC4 ((uint)0x0300)
115#define PROFF_SMC2 ((uint)0x0380)
116
117/* Define enough so I can at least use the serial port as a UART.
fe8c2806
WD		 118 */
119typedef struct smc_uart {
120 ushort smc_rbase; /* Rx Buffer descriptor base address */
121 ushort smc_tbase; /* Tx Buffer descriptor base address */
122 u_char smc_rfcr; /* Rx function code */
123 u_char smc_tfcr; /* Tx function code */
124 ushort smc_mrblr; /* Max receive buffer length */
125 uint smc_rstate; /* Internal */
126 uint smc_idp; /* Internal */
127 ushort smc_rbptr; /* Internal */
128 ushort smc_ibc; /* Internal */
129 uint smc_rxtmp; /* Internal */
130 uint smc_tstate; /* Internal */
131 uint smc_tdp; /* Internal */
132 ushort smc_tbptr; /* Internal */
133 ushort smc_tbc; /* Internal */
134 uint smc_txtmp; /* Internal */
135 ushort smc_maxidl; /* Maximum idle characters */
136 ushort smc_tmpidl; /* Temporary idle counter */
137 ushort smc_brklen; /* Last received break length */
138 ushort smc_brkec; /* rcv'd break condition counter */
139 ushort smc_brkcr; /* xmt break count register */
140 ushort smc_rmask; /* Temporary bit mask */
b423d055
HS		 141 u_char res1[8];
142 ushort smc_rpbase; /* Relocation pointer */
fe8c2806
WD		 143} smc_uart_t;
144
145/* Function code bits.
146*/
147#define SMC_EB ((u_char)0x10) /* Set big endian byte order */
148
149/* SMC uart mode register.
150*/
151#define SMCMR_REN ((ushort)0x0001)
152#define SMCMR_TEN ((ushort)0x0002)
153#define SMCMR_DM ((ushort)0x000c)
154#define SMCMR_SM_GCI ((ushort)0x0000)
155#define SMCMR_SM_UART ((ushort)0x0020)
156#define SMCMR_SM_TRANS ((ushort)0x0030)
157#define SMCMR_SM_MASK ((ushort)0x0030)
158#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */
159#define SMCMR_REVD SMCMR_PM_EVEN
160#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */
161#define SMCMR_BS SMCMR_PEN
162#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */
163#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */
164#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
165
166/* SMC2 as Centronics parallel printer. It is half duplex, in that
167 * it can only receive or transmit. The parameter ram values for
168 * each direction are either unique or properly overlap, so we can
169 * include them in one structure.
170 */
171typedef struct smc_centronics {
172 ushort scent_rbase;
173 ushort scent_tbase;
174 u_char scent_cfcr;
175 u_char scent_smask;
176 ushort scent_mrblr;
177 uint scent_rstate;
178 uint scent_r_ptr;
179 ushort scent_rbptr;
180 ushort scent_r_cnt;
181 uint scent_rtemp;
182 uint scent_tstate;
183 uint scent_t_ptr;
184 ushort scent_tbptr;
185 ushort scent_t_cnt;
186 uint scent_ttemp;
187 ushort scent_max_sl;
188 ushort scent_sl_cnt;
189 ushort scent_character1;
190 ushort scent_character2;
191 ushort scent_character3;
192 ushort scent_character4;
193 ushort scent_character5;
194 ushort scent_character6;
195 ushort scent_character7;
196 ushort scent_character8;
197 ushort scent_rccm;
198 ushort scent_rccr;
199} smc_cent_t;
200
201/* Centronics Status Mask Register.
202*/
203#define SMC_CENT_F ((u_char)0x08)
204#define SMC_CENT_PE ((u_char)0x04)
205#define SMC_CENT_S ((u_char)0x02)
206
207/* SMC Event and Mask register.
208*/
209#define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */
210#define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */
211#define SMCM_TXE ((unsigned char)0x10) /* When in Transparent Mode */
212#define SMCM_BSY ((unsigned char)0x04)
213#define SMCM_TX ((unsigned char)0x02)
214#define SMCM_RX ((unsigned char)0x01)
215
216/* Baud rate generators.
217*/
218#define CPM_BRG_RST ((uint)0x00020000)
219#define CPM_BRG_EN ((uint)0x00010000)
220#define CPM_BRG_EXTC_INT ((uint)0x00000000)
221#define CPM_BRG_EXTC_CLK2 ((uint)0x00004000)
222#define CPM_BRG_EXTC_CLK6 ((uint)0x00008000)
223#define CPM_BRG_ATB ((uint)0x00002000)
224#define CPM_BRG_CD_MASK ((uint)0x00001ffe)
225#define CPM_BRG_DIV16 ((uint)0x00000001)
226
227/* SI Clock Route Register
228*/
229#define SICR_RCLK_SCC1_BRG1 ((uint)0x00000000)
230#define SICR_TCLK_SCC1_BRG1 ((uint)0x00000000)
231#define SICR_RCLK_SCC2_BRG2 ((uint)0x00000800)
232#define SICR_TCLK_SCC2_BRG2 ((uint)0x00000100)
233#define SICR_RCLK_SCC3_BRG3 ((uint)0x00100000)
234#define SICR_TCLK_SCC3_BRG3 ((uint)0x00020000)
235#define SICR_RCLK_SCC4_BRG4 ((uint)0x18000000)
236#define SICR_TCLK_SCC4_BRG4 ((uint)0x03000000)
237
238/* SCCs.
239*/
240#define SCC_GSMRH_IRP ((uint)0x00040000)
241#define SCC_GSMRH_GDE ((uint)0x00010000)
242#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000)
243#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000)
244#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000)
245#define SCC_GSMRH_REVD ((uint)0x00002000)
246#define SCC_GSMRH_TRX ((uint)0x00001000)
247#define SCC_GSMRH_TTX ((uint)0x00000800)
248#define SCC_GSMRH_CDP ((uint)0x00000400)
249#define SCC_GSMRH_CTSP ((uint)0x00000200)
250#define SCC_GSMRH_CDS ((uint)0x00000100)
251#define SCC_GSMRH_CTSS ((uint)0x00000080)
252#define SCC_GSMRH_TFL ((uint)0x00000040)
253#define SCC_GSMRH_RFW ((uint)0x00000020)
254#define SCC_GSMRH_TXSY ((uint)0x00000010)
255#define SCC_GSMRH_SYNL16 ((uint)0x0000000c)
256#define SCC_GSMRH_SYNL8 ((uint)0x00000008)
257#define SCC_GSMRH_SYNL4 ((uint)0x00000004)
258#define SCC_GSMRH_RTSM ((uint)0x00000002)
259#define SCC_GSMRH_RSYN ((uint)0x00000001)
260
261#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */
262#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000)
263#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000)
264#define SCC_GSMRL_EDGE_POS ((uint)0x20000000)
265#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000)
266#define SCC_GSMRL_TCI ((uint)0x10000000)
267#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000)
268#define SCC_GSMRL_TSNC_4 ((uint)0x08000000)
269#define SCC_GSMRL_TSNC_14 ((uint)0x04000000)
270#define SCC_GSMRL_TSNC_INF ((uint)0x00000000)
271#define SCC_GSMRL_RINV ((uint)0x02000000)
272#define SCC_GSMRL_TINV ((uint)0x01000000)
273#define SCC_GSMRL_TPL_128 ((uint)0x00c00000)
274#define SCC_GSMRL_TPL_64 ((uint)0x00a00000)
275#define SCC_GSMRL_TPL_48 ((uint)0x00800000)
276#define SCC_GSMRL_TPL_32 ((uint)0x00600000)
277#define SCC_GSMRL_TPL_16 ((uint)0x00400000)
278#define SCC_GSMRL_TPL_8 ((uint)0x00200000)
279#define SCC_GSMRL_TPL_NONE ((uint)0x00000000)
280#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000)
281#define SCC_GSMRL_TPP_01 ((uint)0x00100000)
282#define SCC_GSMRL_TPP_10 ((uint)0x00080000)
283#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000)
284#define SCC_GSMRL_TEND ((uint)0x00040000)
285#define SCC_GSMRL_TDCR_32 ((uint)0x00030000)
286#define SCC_GSMRL_TDCR_16 ((uint)0x00020000)
287#define SCC_GSMRL_TDCR_8 ((uint)0x00010000)
288#define SCC_GSMRL_TDCR_1 ((uint)0x00000000)
289#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000)
290#define SCC_GSMRL_RDCR_16 ((uint)0x00008000)
291#define SCC_GSMRL_RDCR_8 ((uint)0x00004000)
292#define SCC_GSMRL_RDCR_1 ((uint)0x00000000)
293#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000)
294#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000)
295#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000)
296#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800)
297#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000)
298#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600)
299#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400)
300#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200)
301#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100)
302#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000)
303#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */
304#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080)
305#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040)
306#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000)
307#define SCC_GSMRL_ENR ((uint)0x00000020)
308#define SCC_GSMRL_ENT ((uint)0x00000010)
309#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c)
310#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009)
311#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008)
312#define SCC_GSMRL_MODE_V14 ((uint)0x00000007)
313#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006)
314#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
315#define SCC_GSMRL_MODE_UART ((uint)0x00000004)
316#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003)
317#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002)
318#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000)
319
320#define SCC_TODR_TOD ((ushort)0x8000)
321
322/* SCC Event and Mask register.
323*/
324#define SCCM_TXE ((unsigned char)0x10)
325#define SCCM_BSY ((unsigned char)0x04)
326#define SCCM_TX ((unsigned char)0x02)
327#define SCCM_RX ((unsigned char)0x01)
328
329typedef struct scc_param {
330 ushort scc_rbase; /* Rx Buffer descriptor base address */
331 ushort scc_tbase; /* Tx Buffer descriptor base address */
332 u_char scc_rfcr; /* Rx function code */
333 u_char scc_tfcr; /* Tx function code */
334 ushort scc_mrblr; /* Max receive buffer length */
335 uint scc_rstate; /* Internal */
336 uint scc_idp; /* Internal */
337 ushort scc_rbptr; /* Internal */
338 ushort scc_ibc; /* Internal */
339 uint scc_rxtmp; /* Internal */
340 uint scc_tstate; /* Internal */
341 uint scc_tdp; /* Internal */
342 ushort scc_tbptr; /* Internal */
343 ushort scc_tbc; /* Internal */
344 uint scc_txtmp; /* Internal */
345 uint scc_rcrc; /* Internal */
346 uint scc_tcrc; /* Internal */
347} sccp_t;
348
349/* Function code bits.
350*/
351#define SCC_EB ((u_char)0x10) /* Set big endian byte order */
352
353/* CPM Ethernet through SCCx.
354 */
355typedef struct scc_enet {
356 sccp_t sen_genscc;
357 uint sen_cpres; /* Preset CRC */
358 uint sen_cmask; /* Constant mask for CRC */
359 uint sen_crcec; /* CRC Error counter */
360 uint sen_alec; /* alignment error counter */
361 uint sen_disfc; /* discard frame counter */
362 ushort sen_pads; /* Tx short frame pad character */
363 ushort sen_retlim; /* Retry limit threshold */
364 ushort sen_retcnt; /* Retry limit counter */
365 ushort sen_maxflr; /* maximum frame length register */
366 ushort sen_minflr; /* minimum frame length register */
367 ushort sen_maxd1; /* maximum DMA1 length */
368 ushort sen_maxd2; /* maximum DMA2 length */
369 ushort sen_maxd; /* Rx max DMA */
370 ushort sen_dmacnt; /* Rx DMA counter */
371 ushort sen_maxb; /* Max BD byte count */
372 ushort sen_gaddr1; /* Group address filter */
373 ushort sen_gaddr2;
374 ushort sen_gaddr3;
375 ushort sen_gaddr4;
376 uint sen_tbuf0data0; /* Save area 0 - current frame */
377 uint sen_tbuf0data1; /* Save area 1 - current frame */
378 uint sen_tbuf0rba; /* Internal */
379 uint sen_tbuf0crc; /* Internal */
380 ushort sen_tbuf0bcnt; /* Internal */
381 ushort sen_paddrh; /* physical address (MSB) */
382 ushort sen_paddrm;
383 ushort sen_paddrl; /* physical address (LSB) */
384 ushort sen_pper; /* persistence */
385 ushort sen_rfbdptr; /* Rx first BD pointer */
386 ushort sen_tfbdptr; /* Tx first BD pointer */
387 ushort sen_tlbdptr; /* Tx last BD pointer */
388 uint sen_tbuf1data0; /* Save area 0 - current frame */
389 uint sen_tbuf1data1; /* Save area 1 - current frame */
390 uint sen_tbuf1rba; /* Internal */
391 uint sen_tbuf1crc; /* Internal */
392 ushort sen_tbuf1bcnt; /* Internal */
393 ushort sen_txlen; /* Tx Frame length counter */
394 ushort sen_iaddr1; /* Individual address filter */
395 ushort sen_iaddr2;
396 ushort sen_iaddr3;
397 ushort sen_iaddr4;
398 ushort sen_boffcnt; /* Backoff counter */
399
400 /* NOTE: Some versions of the manual have the following items
401 * incorrectly documented. Below is the proper order.
402 */
403 ushort sen_taddrh; /* temp address (MSB) */
404 ushort sen_taddrm;
405 ushort sen_taddrl; /* temp address (LSB) */
406} scc_enet_t;
407
408/**********************************************************************
409 *
410 * Board specific configuration settings.
411 *
412 * Please note that we use the presence of a #define SCC_ENET and/or
413 * #define FEC_ENET to enable the SCC resp. FEC ethernet drivers.
414 **********************************************************************/
415
fe8c2806
WD		 416/*** BSEIP **********************************************************/
417
418#ifdef CONFIG_BSEIP
419/* This ENET stuff is for the MPC823 with ethernet on SCC2.
420 * This is unique to the BSE ip-Engine board.
421 */
422#define PROFF_ENET PROFF_SCC2
423#define CPM_CR_ENET CPM_CR_CH_SCC2
424#define SCC_ENET 1
425#define PA_ENET_RXD ((ushort)0x0004)
426#define PA_ENET_TXD ((ushort)0x0008)
427#define PA_ENET_TCLK ((ushort)0x0100)
428#define PA_ENET_RCLK ((ushort)0x0200)
429#define PB_ENET_TENA ((uint)0x00002000)
430#define PC_ENET_CLSN ((ushort)0x0040)
431#define PC_ENET_RENA ((ushort)0x0080)
432
433/* BSE uses port B and C bits for PHY control also.
434*/
435#define PB_BSE_POWERUP ((uint)0x00000004)
436#define PB_BSE_FDXDIS ((uint)0x00008000)
437#define PC_BSE_LOOPBACK ((ushort)0x0800)
438
439#define SICR_ENET_MASK ((uint)0x0000ff00)
440#define SICR_ENET_CLKRT ((uint)0x00002c00)
441#endif /* CONFIG_BSEIP */
442
d044954f 443/*** KM8XX *********************************************************/
381e4e63 444
d044954f 445/* The KM8XX Service Module uses SCC3 for Ethernet */
381e4e63 446
d044954f 447#ifdef CONFIG_KM8XX
381e4e63
HS		 448#define PROFF_ENET PROFF_SCC3 /* Ethernet on SCC3 */
449#define CPM_CR_ENET CPM_CR_CH_SCC3
450#define SCC_ENET 2
451#define PA_ENET_RXD ((ushort)0x0010) /* PA 11 */
452#define PA_ENET_TXD ((ushort)0x0020) /* PA 10 */
453#define PA_ENET_RCLK ((ushort)0x1000) /* PA 3 CLK 5 */
454#define PA_ENET_TCLK ((ushort)0x2000) /* PA 2 CLK 6 */
455
456#define PC_ENET_TENA ((ushort)0x0004) /* PC 13 */
457
458#define PC_ENET_RENA ((ushort)0x0200) /* PC 6 */
459#define PC_ENET_CLSN ((ushort)0x0100) /* PC 7 */
460
461/* Control bits in the SICR to route TCLK (CLK6) and RCLK (CLK5) to
462 * SCC3. Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero.
463 */
464#define SICR_ENET_MASK ((uint)0x00FF0000)
465#define SICR_ENET_CLKRT ((uint)0x00250000)
d044954f 466#endif /* CONFIG_KM8XX */
381e4e63 467
1b0757ec 468/*** MVS1, TQM823L/M, TQM850L/M, TQM885D, R360MPI **********/
fe8c2806
WD		 469
470#if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \
8737fc75 471 defined(CONFIG_TQM823L) || \
1b0757ec 472 defined(CONFIG_TQM823M) || defined(CONFIG_TQM850L) || \
8737fc75 473 defined(CONFIG_TQM850M) || defined(CONFIG_TQM885D)
090eb735 474
fe8c2806
WD		 475/* Bits in parallel I/O port registers that have to be set/cleared
476 * to configure the pins for SCC2 use.
477 */
478#define PROFF_ENET PROFF_SCC2
479#define CPM_CR_ENET CPM_CR_CH_SCC2
480#define SCC_ENET 1
481#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
482#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
483#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
484#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
485
486#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
487
488#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
489#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
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WD		 490
491/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
492 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
493 */
494#define SICR_ENET_MASK ((uint)0x0000ff00)
495#define SICR_ENET_CLKRT ((uint)0x00002600)
090eb735
MK		 496
497# ifdef CONFIG_FEC_ENET /* Use FEC for Fast Ethernet */
498#define FEC_ENET
499# endif /* CONFIG_FEC_ENET */
500
71f95118 501#endif /* CONFIG_MVS v1, CONFIG_TQM823L/M, CONFIG_TQM850L/M, etc. */
fe8c2806 502
d4ca31c4 503/*** TQM855L/M, TQM860L/M, TQM862L/M, TQM866L/M *********************/
fe8c2806 504
71f95118
WD		 505#if defined(CONFIG_TQM855L) || defined(CONFIG_TQM855M) || \
506 defined(CONFIG_TQM860L) || defined(CONFIG_TQM860M) || \
d4ca31c4
WD		 507 defined(CONFIG_TQM862L) || defined(CONFIG_TQM862M) || \
508 defined(CONFIG_TQM866L) || defined(CONFIG_TQM866M)
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WD		 509
510# ifdef CONFIG_SCC1_ENET /* use SCC for 10Mbps Ethernet */
511
512/* Bits in parallel I/O port registers that have to be set/cleared
513 * to configure the pins for SCC1 use.
514 */
515#define PROFF_ENET PROFF_SCC1
516#define CPM_CR_ENET CPM_CR_CH_SCC1
517#define SCC_ENET 0
518#define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */
519#define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */
520#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
521#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
522
523#define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */
524#define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */
525#define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */
526
527/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
528 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
529 */
530#define SICR_ENET_MASK ((uint)0x000000ff)
531#define SICR_ENET_CLKRT ((uint)0x00000026)
532
533# endif /* CONFIG_SCC1_ENET */
534
535# ifdef CONFIG_FEC_ENET /* Use FEC for Fast Ethernet */
536
537#define FEC_ENET
538
539#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
540#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
541#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
542#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
543#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
544#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
545#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
546#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
547#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
548#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
549#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
550#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
551#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
552
553#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
554
555# endif /* CONFIG_FEC_ENET */
71f95118 556#endif /* CONFIG_TQM855L/M, TQM860L/M, TQM862L/M */
fe8c2806 557
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WD		 558/*********************************************************************/
559
560/* SCC Event register as used by Ethernet.
561*/
562#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
563#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */
564#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */
565#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */
566#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
567#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */
568
569/* SCC Mode Register (PSMR) as used by Ethernet.
570*/
571#define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */
572#define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */
573#define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */
574#define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */
575#define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */
576#define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */
577#define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */
578#define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */
579#define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */
580#define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */
581#define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */
582#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */
583#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */
584
585/* Buffer descriptor control/status used by Ethernet receive.
586*/
587#define BD_ENET_RX_EMPTY ((ushort)0x8000)
588#define BD_ENET_RX_WRAP ((ushort)0x2000)
589#define BD_ENET_RX_INTR ((ushort)0x1000)
590#define BD_ENET_RX_LAST ((ushort)0x0800)
591#define BD_ENET_RX_FIRST ((ushort)0x0400)
592#define BD_ENET_RX_MISS ((ushort)0x0100)
593#define BD_ENET_RX_LG ((ushort)0x0020)
594#define BD_ENET_RX_NO ((ushort)0x0010)
595#define BD_ENET_RX_SH ((ushort)0x0008)
596#define BD_ENET_RX_CR ((ushort)0x0004)
597#define BD_ENET_RX_OV ((ushort)0x0002)
598#define BD_ENET_RX_CL ((ushort)0x0001)
599#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
600
601/* Buffer descriptor control/status used by Ethernet transmit.
602*/
603#define BD_ENET_TX_READY ((ushort)0x8000)
604#define BD_ENET_TX_PAD ((ushort)0x4000)
605#define BD_ENET_TX_WRAP ((ushort)0x2000)
606#define BD_ENET_TX_INTR ((ushort)0x1000)
607#define BD_ENET_TX_LAST ((ushort)0x0800)
608#define BD_ENET_TX_TC ((ushort)0x0400)
609#define BD_ENET_TX_DEF ((ushort)0x0200)
610#define BD_ENET_TX_HB ((ushort)0x0100)
611#define BD_ENET_TX_LC ((ushort)0x0080)
612#define BD_ENET_TX_RL ((ushort)0x0040)
613#define BD_ENET_TX_RCMASK ((ushort)0x003c)
614#define BD_ENET_TX_UN ((ushort)0x0002)
615#define BD_ENET_TX_CSL ((ushort)0x0001)
616#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
617
618/* SCC as UART
619*/
620typedef struct scc_uart {
621 sccp_t scc_genscc;
622 uint scc_res1; /* Reserved */
623 uint scc_res2; /* Reserved */
624 ushort scc_maxidl; /* Maximum idle chars */
625 ushort scc_idlc; /* temp idle counter */
626 ushort scc_brkcr; /* Break count register */
627 ushort scc_parec; /* receive parity error counter */
628 ushort scc_frmec; /* receive framing error counter */
629 ushort scc_nosec; /* receive noise counter */
630 ushort scc_brkec; /* receive break condition counter */
631 ushort scc_brkln; /* last received break length */
632 ushort scc_uaddr1; /* UART address character 1 */
633 ushort scc_uaddr2; /* UART address character 2 */
634 ushort scc_rtemp; /* Temp storage */
635 ushort scc_toseq; /* Transmit out of sequence char */
636 ushort scc_char1; /* control character 1 */
637 ushort scc_char2; /* control character 2 */
638 ushort scc_char3; /* control character 3 */
639 ushort scc_char4; /* control character 4 */
640 ushort scc_char5; /* control character 5 */
641 ushort scc_char6; /* control character 6 */
642 ushort scc_char7; /* control character 7 */
643 ushort scc_char8; /* control character 8 */
644 ushort scc_rccm; /* receive control character mask */
645 ushort scc_rccr; /* receive control character register */
646 ushort scc_rlbc; /* receive last break character */
647} scc_uart_t;
648
649/* SCC Event and Mask registers when it is used as a UART.
650*/
651#define UART_SCCM_GLR ((ushort)0x1000)
652#define UART_SCCM_GLT ((ushort)0x0800)
653#define UART_SCCM_AB ((ushort)0x0200)
654#define UART_SCCM_IDL ((ushort)0x0100)
655#define UART_SCCM_GRA ((ushort)0x0080)
656#define UART_SCCM_BRKE ((ushort)0x0040)
657#define UART_SCCM_BRKS ((ushort)0x0020)
658#define UART_SCCM_CCR ((ushort)0x0008)
659#define UART_SCCM_BSY ((ushort)0x0004)
660#define UART_SCCM_TX ((ushort)0x0002)
661#define UART_SCCM_RX ((ushort)0x0001)
662
663/* The SCC PSMR when used as a UART.
664*/
665#define SCU_PSMR_FLC ((ushort)0x8000)
666#define SCU_PSMR_SL ((ushort)0x4000)
667#define SCU_PSMR_CL ((ushort)0x3000)
668#define SCU_PSMR_UM ((ushort)0x0c00)
669#define SCU_PSMR_FRZ ((ushort)0x0200)
670#define SCU_PSMR_RZS ((ushort)0x0100)
671#define SCU_PSMR_SYN ((ushort)0x0080)
672#define SCU_PSMR_DRT ((ushort)0x0040)
673#define SCU_PSMR_PEN ((ushort)0x0010)
674#define SCU_PSMR_RPM ((ushort)0x000c)
675#define SCU_PSMR_REVP ((ushort)0x0008)
676#define SCU_PSMR_TPM ((ushort)0x0003)
677#define SCU_PSMR_TEVP ((ushort)0x0003)
678
679/* CPM Transparent mode SCC.
680 */
681typedef struct scc_trans {
682 sccp_t st_genscc;
683 uint st_cpres; /* Preset CRC */
684 uint st_cmask; /* Constant mask for CRC */
685} scc_trans_t;
686
687#define BD_SCC_TX_LAST ((ushort)0x0800)
688
689/* IIC parameter RAM.
690*/
691typedef struct iic {
692 ushort iic_rbase; /* Rx Buffer descriptor base address */
693 ushort iic_tbase; /* Tx Buffer descriptor base address */
694 u_char iic_rfcr; /* Rx function code */
695 u_char iic_tfcr; /* Tx function code */
696 ushort iic_mrblr; /* Max receive buffer length */
697 uint iic_rstate; /* Internal */
698 uint iic_rdp; /* Internal */
699 ushort iic_rbptr; /* Internal */
700 ushort iic_rbc; /* Internal */
701 uint iic_rxtmp; /* Internal */
702 uint iic_tstate; /* Internal */
703 uint iic_tdp; /* Internal */
704 ushort iic_tbptr; /* Internal */
705 ushort iic_tbc; /* Internal */
706 uint iic_txtmp; /* Internal */
707 uint iic_res; /* reserved */
708 ushort iic_rpbase; /* Relocation pointer */
709 ushort iic_res2; /* reserved */
710} iic_t;
711
712/* SPI parameter RAM.
713*/
714typedef struct spi {
715 ushort spi_rbase; /* Rx Buffer descriptor base address */
716 ushort spi_tbase; /* Tx Buffer descriptor base address */
717 u_char spi_rfcr; /* Rx function code */
718 u_char spi_tfcr; /* Tx function code */
719 ushort spi_mrblr; /* Max receive buffer length */
720 uint spi_rstate; /* Internal */
721 uint spi_rdp; /* Internal */
722 ushort spi_rbptr; /* Internal */
723 ushort spi_rbc; /* Internal */
724 uint spi_rxtmp; /* Internal */
725 uint spi_tstate; /* Internal */
726 uint spi_tdp; /* Internal */
727 ushort spi_tbptr; /* Internal */
728 ushort spi_tbc; /* Internal */
729 uint spi_txtmp; /* Internal */
730 uint spi_res;
731 ushort spi_rpbase; /* Relocation pointer */
732 ushort spi_res2;
733} spi_t;
734
735/* SPI Mode register.
736*/
737#define SPMODE_LOOP ((ushort)0x4000) /* Loopback */
738#define SPMODE_CI ((ushort)0x2000) /* Clock Invert */
739#define SPMODE_CP ((ushort)0x1000) /* Clock Phase */
740#define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */
741#define SPMODE_REV ((ushort)0x0400) /* Reversed Data */
742#define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */
743#define SPMODE_EN ((ushort)0x0100) /* Enable */
744#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */
745#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */
746
747#define SPMODE_LEN(x) ((((x)-1)&0xF)<<4)
748#define SPMODE_PM(x) ((x) &0xF)
749
750/* HDLC parameter RAM.
751*/
752
753typedef struct hdlc_pram_s {
754 /*
755 * SCC parameter RAM
756 */
757 ushort rbase; /* Rx Buffer descriptor base address */
758 ushort tbase; /* Tx Buffer descriptor base address */
759 uchar rfcr; /* Rx function code */
760 uchar tfcr; /* Tx function code */
761 ushort mrblr; /* Rx buffer length */
762 ulong rstate; /* Rx internal state */
763 ulong rptr; /* Rx internal data pointer */
764 ushort rbptr; /* rb BD Pointer */
765 ushort rcount; /* Rx internal byte count */
766 ulong rtemp; /* Rx temp */
767 ulong tstate; /* Tx internal state */
768 ulong tptr; /* Tx internal data pointer */
769 ushort tbptr; /* Tx BD pointer */
770 ushort tcount; /* Tx byte count */
771 ulong ttemp; /* Tx temp */
772 ulong rcrc; /* temp receive CRC */
773 ulong tcrc; /* temp transmit CRC */
774 /*
775 * HDLC specific parameter RAM
776 */
777 uchar res[4]; /* reserved */
778 ulong c_mask; /* CRC constant */
779 ulong c_pres; /* CRC preset */
780 ushort disfc; /* discarded frame counter */
781 ushort crcec; /* CRC error counter */
782 ushort abtsc; /* abort sequence counter */
783 ushort nmarc; /* nonmatching address rx cnt */
784 ushort retrc; /* frame retransmission cnt */
785 ushort mflr; /* maximum frame length reg */
786 ushort max_cnt; /* maximum length counter */
787 ushort rfthr; /* received frames threshold */
788 ushort rfcnt; /* received frames count */
789 ushort hmask; /* user defined frm addr mask */
790 ushort haddr1; /* user defined frm address 1 */
791 ushort haddr2; /* user defined frm address 2 */
792 ushort haddr3; /* user defined frm address 3 */
793 ushort haddr4; /* user defined frm address 4 */
794 ushort tmp; /* temp */
795 ushort tmp_mb; /* temp */
796} hdlc_pram_t;
797
798/* CPM interrupts. There are nearly 32 interrupts generated by CPM
799 * channels or devices. All of these are presented to the PPC core
800 * as a single interrupt. The CPM interrupt handler dispatches its
801 * own handlers, in a similar fashion to the PPC core handler. We
802 * use the table as defined in the manuals (i.e. no special high
803 * priority and SCC1 == SCCa, etc...).
804 */
805#define CPMVEC_NR 32
7c7a23bd
WD		 806#define CPMVEC_OFFSET 0x00010000
807#define CPMVEC_PIO_PC15 ((ushort)0x1f | CPMVEC_OFFSET)
808#define CPMVEC_SCC1 ((ushort)0x1e | CPMVEC_OFFSET)
809#define CPMVEC_SCC2 ((ushort)0x1d | CPMVEC_OFFSET)
810#define CPMVEC_SCC3 ((ushort)0x1c | CPMVEC_OFFSET)
811#define CPMVEC_SCC4 ((ushort)0x1b | CPMVEC_OFFSET)
812#define CPMVEC_PIO_PC14 ((ushort)0x1a | CPMVEC_OFFSET)
813#define CPMVEC_TIMER1 ((ushort)0x19 | CPMVEC_OFFSET)
814#define CPMVEC_PIO_PC13 ((ushort)0x18 | CPMVEC_OFFSET)
815#define CPMVEC_PIO_PC12 ((ushort)0x17 | CPMVEC_OFFSET)
816#define CPMVEC_SDMA_CB_ERR ((ushort)0x16 | CPMVEC_OFFSET)
817#define CPMVEC_IDMA1 ((ushort)0x15 | CPMVEC_OFFSET)
818#define CPMVEC_IDMA2 ((ushort)0x14 | CPMVEC_OFFSET)
819#define CPMVEC_TIMER2 ((ushort)0x12 | CPMVEC_OFFSET)
820#define CPMVEC_RISCTIMER ((ushort)0x11 | CPMVEC_OFFSET)
821#define CPMVEC_I2C ((ushort)0x10 | CPMVEC_OFFSET)
822#define CPMVEC_PIO_PC11 ((ushort)0x0f | CPMVEC_OFFSET)
823#define CPMVEC_PIO_PC10 ((ushort)0x0e | CPMVEC_OFFSET)
824#define CPMVEC_TIMER3 ((ushort)0x0c | CPMVEC_OFFSET)
825#define CPMVEC_PIO_PC9 ((ushort)0x0b | CPMVEC_OFFSET)
826#define CPMVEC_PIO_PC8 ((ushort)0x0a | CPMVEC_OFFSET)
827#define CPMVEC_PIO_PC7 ((ushort)0x09 | CPMVEC_OFFSET)
828#define CPMVEC_TIMER4 ((ushort)0x07 | CPMVEC_OFFSET)
829#define CPMVEC_PIO_PC6 ((ushort)0x06 | CPMVEC_OFFSET)
830#define CPMVEC_SPI ((ushort)0x05 | CPMVEC_OFFSET)
831#define CPMVEC_SMC1 ((ushort)0x04 | CPMVEC_OFFSET)
832#define CPMVEC_SMC2 ((ushort)0x03 | CPMVEC_OFFSET)
833#define CPMVEC_PIO_PC5 ((ushort)0x02 | CPMVEC_OFFSET)
834#define CPMVEC_PIO_PC4 ((ushort)0x01 | CPMVEC_OFFSET)
835#define CPMVEC_ERROR ((ushort)0x00 | CPMVEC_OFFSET)
fe8c2806
WD		 836
837extern void irq_install_handler(int vec, void (*handler)(void *), void *dev_id);
838
839/* CPM interrupt configuration vector.
840*/
841#define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */
842#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */
843#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */
844#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */
845#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrrupt */
846#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */
847#define CICR_IEN ((uint)0x00000080) /* Int. enable */
848#define CICR_SPS ((uint)0x00000001) /* SCC Spread */
849#endif /* __CPM_8XX__ */
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