projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 0332990b WD |
1 | /* |
| 2 | * (C) Copyright 2001, 2002, 2003 | |
| 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
| 4 | * | |
| 5 | * See file CREDITS for list of people who contributed to this | |
| 6 | * project. | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or | |
| 9 | * modify it under the terms of the GNU General Public License as | |
| 10 | * published by the Free Software Foundation; either version 2 of | |
| 11 | * the License, or (at your option) any later version. | |
| 12 | * | |
| 13 | * This program is distributed in the hope that it will be useful, | |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | * GNU General Public License for more details. | |
| 17 | * | |
| 18 | * You should have received a copy of the GNU General Public License | |
| 19 | * along with this program; if not, write to the Free Software | |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 21 | * MA 02111-1307 USA | |
| 22 | */ | |
| 23 | ||
| 24 | /* ------------------------------------------------------------------------- */ | |
| 25 | /* | |
| 26 | * Configuration settings for the A-3000 board (Artis Microsystems Inc.). | |
| 27 | * http://artismicro.com | |
| 28 | */ | |
| 29 | ||
| 30 | /* ------------------------------------------------------------------------- */ | |
| 31 | ||
| 32 | /* | |
| 33 | * board/config.h - configuration options, board specific | |
| 34 | */ | |
| 35 | ||
| 36 | #ifndef __CONFIG_H | |
| 37 | #define __CONFIG_H | |
| 38 | ||
| 39 | /* | |
| 40 | * High Level Configuration Options | |
| 41 | * (easy to change) | |
| 42 | */ | |
| 43 | ||
| 44 | #define CONFIG_MPC824X 1 | |
| 45 | #define CONFIG_MPC8245 1 | |
| 46 | #define CONFIG_A3000 1 | |
| 47 | ||
| 48 | ||
| 49 | #define CONFIG_CONS_INDEX 1 | |
| 50 | #define CONFIG_BAUDRATE 9600 | |
| 51 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } | |
| 52 | ||
| 53 | #define CONFIG_BOOTDELAY 5 | |
| 54 | ||
| 55 | #if 0 | |
| 56 | #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ | |
| 57 | CFG_CMD_BEDBUG | \ | |
| 58 | CFG_CMD_BSP | \ | |
| 59 | CFG_CMD_ELF | \ | |
| 60 | CFG_CMD_I2C | \ | |
| 61 | CFG_CMD_FLASH | \ | |
| 62 | CFG_CMD_BEDBUG | \ | |
| 63 | CFG_CMD_NET | \ | |
| 64 | CFG_CMD_PCI ) | |
| 65 | #endif | |
| 66 | ||
| 67 | #define CONFIG_COMMANDS ( CONFIG_CMD_DFL ) | |
| 68 | ||
| 69 | /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ | |
| 70 | ||
| 71 | #include <cmd_confdefs.h> | |
| 72 | ||
| 73 | ||
| 74 | /* | |
| 75 | * Miscellaneous configurable options | |
| 76 | */ | |
| 77 | #undef CFG_LONGHELP /* undef to save memory */ | |
| 78 | #define CFG_PROMPT "A3000> " /* Monitor Command Prompt */ | |
| 79 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
| 80 | ||
| 81 | /* Print Buffer Size | |
| 82 | */ | |
| 83 | #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) | |
| 84 | #define CFG_MAXARGS 8 /* Max number of command args */ | |
| 85 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
| 86 | #define CFG_LOAD_ADDR 0x00400000 /* Default load address */ | |
| 87 | ||
| 88 | /*----------------------------------------------------------------------- | |
| 89 | * PCI stuff | |
| 90 | *----------------------------------------------------------------------- | |
| 91 | */ | |
| 92 | #define CONFIG_HARD_I2C 1 /* To enable I2C support */ | |
| 93 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
| 94 | #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ | |
| 95 | #define CFG_I2C_SLAVE 0x7F | |
| 96 | ||
| 97 | /*----------------------------------------------------------------------- | |
| 98 | * PCI stuff | |
| 99 | *----------------------------------------------------------------------- | |
| 100 | */ | |
| 101 | #define CONFIG_PCI /* include pci support */ | |
| 102 | #undef CONFIG_PCI_PNP | |
| 103 | #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ | |
| 104 | ||
| 105 | #define CONFIG_NET_MULTI /* Multi ethernet cards support */ | |
| 106 | ||
| 107 | /* #define CONFIG_TULIP */ | |
| 108 | /* #define CONFIG_EEPRO100 */ | |
| 8bde7f77 | 109 | #define CONFIG_NATSEMI |
| 0332990b WD |
110 | |
| 111 | #define PCI_ENET0_IOADDR 0x80000000 | |
| 112 | #define PCI_ENET0_MEMADDR 0x80000000 | |
| 113 | #define PCI_ENET1_IOADDR 0x81000000 | |
| 114 | #define PCI_ENET1_MEMADDR 0x81000000 | |
| 115 | #define PCI_ENET2_IOADDR 0x82000000 | |
| 116 | #define PCI_ENET2_MEMADDR 0x82000000 | |
| 8564acf9 WD |
117 | #define PCI_ENET3_IOADDR 0x83000000 |
| 118 | #define PCI_ENET3_MEMADDR 0x83000000 | |
| 0332990b WD |
119 | |
| 120 | ||
| 121 | /*----------------------------------------------------------------------- | |
| 122 | * Start addresses for the final memory configuration | |
| 123 | * (Set up by the startup code) | |
| 124 | * Please note that CFG_SDRAM_BASE _must_ start at 0 | |
| 125 | */ | |
| 126 | #define CFG_SDRAM_BASE 0x00000000 | |
| 127 | ||
| 128 | #define CFG_FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank on RCS#0 */ | |
| 129 | #define CFG_FLASH_BASE1_PRELIM 0xFF000000 /* FLASH bank on RCS#1 */ | |
| 130 | #define CFG_FLASH_BASE CFG_FLASH_BASE0_PRELIM | |
| 131 | #define CFG_FLASH_BANKS { CFG_FLASH_BASE0_PRELIM } | |
| 132 | ||
| 133 | /* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the | |
| 134 | * reset vector is actually located at FFB00100, but the 8245 | |
| 135 | * takes care of us. | |
| 136 | */ | |
| 137 | #define CFG_RESET_ADDRESS 0xFFF00100 | |
| 138 | ||
| 139 | #define CFG_EUMB_ADDR 0xFC000000 | |
| 140 | ||
| 141 | #define CFG_MONITOR_BASE TEXT_BASE | |
| 142 | #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
| 143 | #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
| 144 | ||
| 145 | #define CFG_MEMTEST_START 0x00004000 /* memtest works on */ | |
| 146 | #define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ | |
| 147 | ||
| 148 | /* Maximum amount of RAM. | |
| 149 | */ | |
| 150 | #define CFG_MAX_RAM_SIZE 0x04000000 /* 0 .. 128 MB of (S)DRAM */ | |
| 151 | ||
| 152 | ||
| 153 | #if CFG_MONITOR_BASE >= CFG_FLASH_BASE | |
| 154 | #undef CFG_RAMBOOT | |
| 155 | #else | |
| 156 | #define CFG_RAMBOOT | |
| 157 | #endif | |
| 158 | ||
| 159 | /* | |
| 160 | * NS16550 Configuration | |
| 161 | */ | |
| 162 | #define CFG_NS16550 | |
| 163 | #define CFG_NS16550_SERIAL | |
| 164 | ||
| 165 | #define CFG_NS16550_REG_SIZE 1 | |
| 166 | ||
| 167 | #define CFG_NS16550_CLK get_bus_freq(0) | |
| 168 | ||
| 169 | #define CFG_NS16550_COM1 (CFG_EUMB_ADDR + 0x4500) | |
| 170 | #define CFG_NS16550_COM2 (CFG_EUMB_ADDR + 0x4600) | |
| 171 | ||
| 172 | /*----------------------------------------------------------------------- | |
| 173 | * Definitions for initial stack pointer and data area | |
| 174 | */ | |
| 175 | ||
| 176 | /* #define CFG_MONITOR_BASE TEXT_BASE */ | |
| 177 | /*#define CFG_GBL_DATA_SIZE 256*/ | |
| 178 | #define CFG_GBL_DATA_SIZE 128 | |
| 179 | #define CFG_INIT_RAM_ADDR 0x40000000 | |
| 180 | #define CFG_INIT_RAM_END 0x1000 | |
| 181 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
| 182 | ||
| 183 | ||
| 184 | /* | |
| 185 | * Low Level Configuration Settings | |
| 186 | * (address mappings, register initial values, etc.) | |
| 187 | * You should know what you are doing if you make changes here. | |
| 188 | * For the detail description refer to the MPC8240 user's manual. | |
| 189 | */ | |
| 190 | ||
| 191 | #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ | |
| 192 | #define CFG_HZ 1000 | |
| 193 | ||
| 194 | /* Bit-field values for MCCR1. | |
| 195 | */ | |
| 196 | #define CFG_ROMNAL 7 | |
| 197 | #define CFG_ROMFAL 11 | |
| 198 | #define CFG_DBUS_SIZE 0x3 | |
| 199 | ||
| 200 | /* Bit-field values for MCCR2. | |
| 201 | */ | |
| 202 | #define CFG_TSWAIT 0x5 /* Transaction Start Wait States timer */ | |
| 203 | #define CFG_REFINT 0x400 /* Refresh interval FIXME: was 0t430 */ | |
| 204 | ||
| 205 | /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. | |
| 206 | */ | |
| 207 | #define CFG_BSTOPRE 121 | |
| 208 | ||
| 209 | /* Bit-field values for MCCR3. | |
| 210 | */ | |
| 211 | #define CFG_REFREC 8 /* Refresh to activate interval */ | |
| 212 | ||
| 213 | /* Bit-field values for MCCR4. | |
| 214 | */ | |
| 215 | #define CFG_PRETOACT 3 /* Precharge to activate interval FIXME: was 2 */ | |
| 216 | #define CFG_ACTTOPRE 5 /* Activate to Precharge interval FIXME: was 5 */ | |
| 217 | #define CFG_ACTORW 3 /* FIXME was 2 */ | |
| 218 | #define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */ | |
| 219 | #define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */ | |
| 220 | #define CFG_REGISTERD_TYPE_BUFFER 1 | |
| 221 | #define CFG_EXTROM 1 | |
| 222 | #define CFG_REGDIMM 0 | |
| 223 | ||
| 224 | #define CFG_PGMAX 0x32 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/ | |
| 225 | ||
| 226 | #define CFG_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */ | |
| 227 | ||
| 228 | /* Memory bank settings. | |
| 229 | * Only bits 20-29 are actually used from these vales to set the | |
| 230 | * start/end addresses. The upper two bits will always be 0, and the lower | |
| 231 | * 20 bits will be 0x00000 for a start address, or 0xfffff for an end | |
| 232 | * address. Refer to the MPC8240 book. | |
| 233 | */ | |
| 234 | ||
| 235 | #define CFG_BANK0_START 0x00000000 | |
| 236 | #define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1) | |
| 237 | #define CFG_BANK0_ENABLE 1 | |
| 238 | #define CFG_BANK1_START 0x3ff00000 | |
| 239 | #define CFG_BANK1_END 0x3fffffff | |
| 240 | #define CFG_BANK1_ENABLE 0 | |
| 241 | #define CFG_BANK2_START 0x3ff00000 | |
| 242 | #define CFG_BANK2_END 0x3fffffff | |
| 243 | #define CFG_BANK2_ENABLE 0 | |
| 244 | #define CFG_BANK3_START 0x3ff00000 | |
| 245 | #define CFG_BANK3_END 0x3fffffff | |
| 246 | #define CFG_BANK3_ENABLE 0 | |
| 247 | #define CFG_BANK4_START 0x3ff00000 | |
| 248 | #define CFG_BANK4_END 0x3fffffff | |
| 249 | #define CFG_BANK4_ENABLE 0 | |
| 250 | #define CFG_BANK5_START 0x3ff00000 | |
| 251 | #define CFG_BANK5_END 0x3fffffff | |
| 252 | #define CFG_BANK5_ENABLE 0 | |
| 253 | #define CFG_BANK6_START 0x3ff00000 | |
| 254 | #define CFG_BANK6_END 0x3fffffff | |
| 255 | #define CFG_BANK6_ENABLE 0 | |
| 256 | #define CFG_BANK7_START 0x3ff00000 | |
| 257 | #define CFG_BANK7_END 0x3fffffff | |
| 258 | #define CFG_BANK7_ENABLE 0 | |
| 259 | ||
| 260 | #define CFG_ODCR 0xff | |
| 261 | ||
| 262 | #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) | |
| 263 | #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 264 | ||
| 265 | #define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) | |
| 266 | #define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) | |
| 267 | ||
| 268 | #define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) | |
| 269 | #define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 270 | ||
| 271 | #define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) | |
| 272 | #define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 273 | ||
| 274 | #define CFG_DBAT0L CFG_IBAT0L | |
| 275 | #define CFG_DBAT0U CFG_IBAT0U | |
| 276 | #define CFG_DBAT1L CFG_IBAT1L | |
| 277 | #define CFG_DBAT1U CFG_IBAT1U | |
| 278 | #define CFG_DBAT2L CFG_IBAT2L | |
| 279 | #define CFG_DBAT2U CFG_IBAT2U | |
| 280 | #define CFG_DBAT3L CFG_IBAT3L | |
| 281 | #define CFG_DBAT3U CFG_IBAT3U | |
| 282 | ||
| 283 | /* | |
| 284 | * For booting Linux, the board info and command line data | |
| 285 | * have to be in the first 8 MB of memory, since this is | |
| 286 | * the maximum mapped by the Linux kernel during initialization. | |
| 287 | */ | |
| 288 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
| 289 | ||
| 290 | /*----------------------------------------------------------------------- | |
| 291 | * FLASH organization | |
| 292 | */ | |
| 293 | #define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */ | |
| 294 | #define CFG_MAX_FLASH_SECT 128 /* Max number of sectors per flash */ | |
| 295 | ||
| 296 | #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ | |
| 297 | #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
| 298 | ||
| 299 | ||
| 300 | /* Warining: environment is not EMBEDDED in the U-Boot code. | |
| 301 | * It's stored in flash separately. | |
| 302 | */ | |
| 303 | #define CFG_ENV_IS_IN_FLASH 1 | |
| 304 | #define CFG_ENV_ADDR 0xFFFE0000 | |
| 305 | #define CFG_ENV_SIZE 0x00020000 /* Size of the Environment */ | |
| 306 | #define CFG_ENV_SECT_SIZE 0x00020000 /* Size of the Environment Sector */ | |
| 307 | ||
| 308 | /*----------------------------------------------------------------------- | |
| 309 | * Cache Configuration | |
| 310 | */ | |
| 311 | #define CFG_CACHELINE_SIZE 32 | |
| 312 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
| 313 | # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ | |
| 314 | #endif | |
| 315 | ||
| 316 | /* | |
| 317 | * Internal Definitions | |
| 318 | * | |
| 319 | * Boot Flags | |
| 320 | */ | |
| 321 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
| 322 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
| 323 | ||
| 0332990b | 324 | #endif /* __CONFIG_H */ |