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0332990b WD |
1 | /* |
2 | * (C) Copyright 2001, 2002, 2003 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
0332990b WD |
6 | */ |
7 | ||
8 | /* ------------------------------------------------------------------------- */ | |
9 | /* | |
10 | * Configuration settings for the A-3000 board (Artis Microsystems Inc.). | |
11 | * http://artismicro.com | |
12 | */ | |
13 | ||
14 | /* ------------------------------------------------------------------------- */ | |
15 | ||
16 | /* | |
17 | * board/config.h - configuration options, board specific | |
18 | */ | |
19 | ||
20 | #ifndef __CONFIG_H | |
21 | #define __CONFIG_H | |
22 | ||
23 | /* | |
24 | * High Level Configuration Options | |
25 | * (easy to change) | |
26 | */ | |
27 | ||
0332990b WD |
28 | #define CONFIG_MPC8245 1 |
29 | #define CONFIG_A3000 1 | |
30 | ||
2ae18241 | 31 | #define CONFIG_SYS_TEXT_BASE 0xFFF00000 |
0332990b WD |
32 | |
33 | #define CONFIG_CONS_INDEX 1 | |
34 | #define CONFIG_BAUDRATE 9600 | |
0332990b WD |
35 | |
36 | #define CONFIG_BOOTDELAY 5 | |
37 | ||
0332990b | 38 | |
11799434 JL |
39 | /* |
40 | * BOOTP options | |
41 | */ | |
42 | #define CONFIG_BOOTP_BOOTFILESIZE | |
43 | #define CONFIG_BOOTP_BOOTPATH | |
44 | #define CONFIG_BOOTP_GATEWAY | |
45 | #define CONFIG_BOOTP_HOSTNAME | |
46 | ||
47 | ||
498ff9a2 JL |
48 | /* |
49 | * Command line configuration. | |
50 | */ | |
51 | #include <config_cmd_default.h> | |
0332990b WD |
52 | |
53 | ||
54 | /* | |
55 | * Miscellaneous configurable options | |
56 | */ | |
6d0f6bcf JCPV |
57 | #undef CONFIG_SYS_LONGHELP /* undef to save memory */ |
58 | #define CONFIG_SYS_PROMPT "A3000> " /* Monitor Command Prompt */ | |
59 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
0332990b WD |
60 | |
61 | /* Print Buffer Size | |
62 | */ | |
6d0f6bcf JCPV |
63 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) |
64 | #define CONFIG_SYS_MAXARGS 8 /* Max number of command args */ | |
65 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
66 | #define CONFIG_SYS_LOAD_ADDR 0x00400000 /* Default load address */ | |
0332990b WD |
67 | |
68 | /*----------------------------------------------------------------------- | |
69 | * PCI stuff | |
70 | *----------------------------------------------------------------------- | |
71 | */ | |
ea818dbb HS |
72 | #define CONFIG_HARD_I2C 1 /* To enable I2C support */ |
73 | #undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ | |
6d0f6bcf JCPV |
74 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
75 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
0332990b WD |
76 | |
77 | /*----------------------------------------------------------------------- | |
78 | * PCI stuff | |
79 | *----------------------------------------------------------------------- | |
80 | */ | |
53677ef1 | 81 | #define CONFIG_PCI /* include pci support */ |
842033e6 | 82 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ |
53677ef1 WD |
83 | #undef CONFIG_PCI_PNP |
84 | #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ | |
0332990b | 85 | |
0332990b WD |
86 | |
87 | /* #define CONFIG_TULIP */ | |
88 | /* #define CONFIG_EEPRO100 */ | |
8bde7f77 | 89 | #define CONFIG_NATSEMI |
0332990b WD |
90 | |
91 | #define PCI_ENET0_IOADDR 0x80000000 | |
92 | #define PCI_ENET0_MEMADDR 0x80000000 | |
93 | #define PCI_ENET1_IOADDR 0x81000000 | |
94 | #define PCI_ENET1_MEMADDR 0x81000000 | |
95 | #define PCI_ENET2_IOADDR 0x82000000 | |
96 | #define PCI_ENET2_MEMADDR 0x82000000 | |
8564acf9 WD |
97 | #define PCI_ENET3_IOADDR 0x83000000 |
98 | #define PCI_ENET3_MEMADDR 0x83000000 | |
0332990b WD |
99 | |
100 | ||
101 | /*----------------------------------------------------------------------- | |
102 | * Start addresses for the final memory configuration | |
103 | * (Set up by the startup code) | |
6d0f6bcf | 104 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
0332990b | 105 | */ |
6d0f6bcf | 106 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
0332990b | 107 | |
6d0f6bcf JCPV |
108 | #define CONFIG_SYS_FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank on RCS#0 */ |
109 | #define CONFIG_SYS_FLASH_BASE1_PRELIM 0xFF000000 /* FLASH bank on RCS#1 */ | |
110 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH_BASE0_PRELIM | |
111 | #define CONFIG_SYS_FLASH_BANKS { CONFIG_SYS_FLASH_BASE0_PRELIM } | |
0332990b WD |
112 | |
113 | /* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the | |
114 | * reset vector is actually located at FFB00100, but the 8245 | |
115 | * takes care of us. | |
116 | */ | |
6d0f6bcf | 117 | #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 |
0332990b | 118 | |
6d0f6bcf | 119 | #define CONFIG_SYS_EUMB_ADDR 0xFC000000 |
0332990b | 120 | |
14d0a02a | 121 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf JCPV |
122 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
123 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
0332990b | 124 | |
6d0f6bcf JCPV |
125 | #define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */ |
126 | #define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ | |
0332990b WD |
127 | |
128 | /* Maximum amount of RAM. | |
129 | */ | |
6d0f6bcf | 130 | #define CONFIG_SYS_MAX_RAM_SIZE 0x04000000 /* 0 .. 128 MB of (S)DRAM */ |
0332990b WD |
131 | |
132 | ||
6d0f6bcf JCPV |
133 | #if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE |
134 | #undef CONFIG_SYS_RAMBOOT | |
0332990b | 135 | #else |
6d0f6bcf | 136 | #define CONFIG_SYS_RAMBOOT |
0332990b WD |
137 | #endif |
138 | ||
139 | /* | |
140 | * NS16550 Configuration | |
141 | */ | |
6d0f6bcf JCPV |
142 | #define CONFIG_SYS_NS16550 |
143 | #define CONFIG_SYS_NS16550_SERIAL | |
0332990b | 144 | |
6d0f6bcf | 145 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
0332990b | 146 | |
6d0f6bcf | 147 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) |
0332990b | 148 | |
6d0f6bcf JCPV |
149 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_EUMB_ADDR + 0x4500) |
150 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4600) | |
0332990b WD |
151 | |
152 | /*----------------------------------------------------------------------- | |
153 | * Definitions for initial stack pointer and data area | |
154 | */ | |
155 | ||
14d0a02a | 156 | /* #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE */ |
6d0f6bcf | 157 | #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 |
553f0982 | 158 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 |
25ddd1fb | 159 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
0332990b WD |
160 | |
161 | ||
162 | /* | |
163 | * Low Level Configuration Settings | |
164 | * (address mappings, register initial values, etc.) | |
165 | * You should know what you are doing if you make changes here. | |
166 | * For the detail description refer to the MPC8240 user's manual. | |
167 | */ | |
168 | ||
169 | #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ | |
0332990b WD |
170 | |
171 | /* Bit-field values for MCCR1. | |
172 | */ | |
6d0f6bcf JCPV |
173 | #define CONFIG_SYS_ROMNAL 7 |
174 | #define CONFIG_SYS_ROMFAL 11 | |
175 | #define CONFIG_SYS_DBUS_SIZE 0x3 | |
0332990b WD |
176 | |
177 | /* Bit-field values for MCCR2. | |
178 | */ | |
6d0f6bcf JCPV |
179 | #define CONFIG_SYS_TSWAIT 0x5 /* Transaction Start Wait States timer */ |
180 | #define CONFIG_SYS_REFINT 0x400 /* Refresh interval FIXME: was 0t430 */ | |
0332990b WD |
181 | |
182 | /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. | |
183 | */ | |
6d0f6bcf | 184 | #define CONFIG_SYS_BSTOPRE 121 |
0332990b WD |
185 | |
186 | /* Bit-field values for MCCR3. | |
187 | */ | |
6d0f6bcf | 188 | #define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */ |
0332990b WD |
189 | |
190 | /* Bit-field values for MCCR4. | |
191 | */ | |
6d0f6bcf JCPV |
192 | #define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval FIXME: was 2 */ |
193 | #define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval FIXME: was 5 */ | |
194 | #define CONFIG_SYS_ACTORW 3 /* FIXME was 2 */ | |
195 | #define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */ | |
196 | #define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */ | |
197 | #define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1 | |
198 | #define CONFIG_SYS_EXTROM 1 | |
199 | #define CONFIG_SYS_REGDIMM 0 | |
0332990b | 200 | |
6d0f6bcf | 201 | #define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/ |
0332990b | 202 | |
6d0f6bcf | 203 | #define CONFIG_SYS_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */ |
0332990b WD |
204 | |
205 | /* Memory bank settings. | |
206 | * Only bits 20-29 are actually used from these vales to set the | |
207 | * start/end addresses. The upper two bits will always be 0, and the lower | |
208 | * 20 bits will be 0x00000 for a start address, or 0xfffff for an end | |
209 | * address. Refer to the MPC8240 book. | |
210 | */ | |
211 | ||
6d0f6bcf JCPV |
212 | #define CONFIG_SYS_BANK0_START 0x00000000 |
213 | #define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1) | |
214 | #define CONFIG_SYS_BANK0_ENABLE 1 | |
215 | #define CONFIG_SYS_BANK1_START 0x3ff00000 | |
216 | #define CONFIG_SYS_BANK1_END 0x3fffffff | |
217 | #define CONFIG_SYS_BANK1_ENABLE 0 | |
218 | #define CONFIG_SYS_BANK2_START 0x3ff00000 | |
219 | #define CONFIG_SYS_BANK2_END 0x3fffffff | |
220 | #define CONFIG_SYS_BANK2_ENABLE 0 | |
221 | #define CONFIG_SYS_BANK3_START 0x3ff00000 | |
222 | #define CONFIG_SYS_BANK3_END 0x3fffffff | |
223 | #define CONFIG_SYS_BANK3_ENABLE 0 | |
224 | #define CONFIG_SYS_BANK4_START 0x3ff00000 | |
225 | #define CONFIG_SYS_BANK4_END 0x3fffffff | |
226 | #define CONFIG_SYS_BANK4_ENABLE 0 | |
227 | #define CONFIG_SYS_BANK5_START 0x3ff00000 | |
228 | #define CONFIG_SYS_BANK5_END 0x3fffffff | |
229 | #define CONFIG_SYS_BANK5_ENABLE 0 | |
230 | #define CONFIG_SYS_BANK6_START 0x3ff00000 | |
231 | #define CONFIG_SYS_BANK6_END 0x3fffffff | |
232 | #define CONFIG_SYS_BANK6_ENABLE 0 | |
233 | #define CONFIG_SYS_BANK7_START 0x3ff00000 | |
234 | #define CONFIG_SYS_BANK7_END 0x3fffffff | |
235 | #define CONFIG_SYS_BANK7_ENABLE 0 | |
236 | ||
237 | #define CONFIG_SYS_ODCR 0xff | |
238 | ||
239 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) | |
240 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
241 | ||
242 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) | |
243 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) | |
244 | ||
245 | #define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) | |
246 | #define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) | |
247 | ||
248 | #define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) | |
249 | #define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) | |
250 | ||
251 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L | |
252 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
253 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L | |
254 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
255 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L | |
256 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
257 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L | |
258 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
0332990b WD |
259 | |
260 | /* | |
261 | * For booting Linux, the board info and command line data | |
262 | * have to be in the first 8 MB of memory, since this is | |
263 | * the maximum mapped by the Linux kernel during initialization. | |
264 | */ | |
6d0f6bcf | 265 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
0332990b WD |
266 | |
267 | /*----------------------------------------------------------------------- | |
268 | * FLASH organization | |
269 | */ | |
6d0f6bcf JCPV |
270 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */ |
271 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max number of sectors per flash */ | |
0332990b | 272 | |
6d0f6bcf JCPV |
273 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
274 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
0332990b WD |
275 | |
276 | ||
277 | /* Warining: environment is not EMBEDDED in the U-Boot code. | |
278 | * It's stored in flash separately. | |
279 | */ | |
5a1aceb0 | 280 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
281 | #define CONFIG_ENV_ADDR 0xFFFE0000 |
282 | #define CONFIG_ENV_SIZE 0x00020000 /* Size of the Environment */ | |
283 | #define CONFIG_ENV_SECT_SIZE 0x00020000 /* Size of the Environment Sector */ | |
0332990b WD |
284 | |
285 | /*----------------------------------------------------------------------- | |
286 | * Cache Configuration | |
287 | */ | |
6d0f6bcf | 288 | #define CONFIG_SYS_CACHELINE_SIZE 32 |
498ff9a2 | 289 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 290 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
0332990b WD |
291 | #endif |
292 | ||
0332990b | 293 | #endif /* __CONFIG_H */ |