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7521af1c WD |
1 | /* |
2 | * AMIRIX.h: AMIRIX specific config options | |
3 | * | |
4 | * Author : Frank Smith (smith at amirix dot com) | |
5 | * | |
6 | * Derived from : other configuration header files in this tree | |
7 | * | |
8 | * This software may be used and distributed according to the terms of | |
9 | * the GNU General Public License (GPL) version 2, incorporated herein by | |
10 | * reference. Drivers based on or derived from this code fall under the GPL | |
11 | * and must retain the authorship, copyright and this license notice. This | |
12 | * file is not a complete program and may only be used when the entire | |
13 | * program is licensed under the GPL. | |
14 | * | |
15 | */ | |
16 | ||
17 | #ifndef __CONFIG_H | |
18 | #define __CONFIG_H | |
19 | ||
20 | /* | |
21 | * High Level Configuration Options | |
22 | * (easy to change) | |
23 | */ | |
24 | ||
f57f70aa WD |
25 | #define CONFIG_405 1 /* This is a PPC405 CPU */ |
26 | #define CONFIG_4xx 1 /* ...member of PPC4xx family */ | |
7521af1c | 27 | |
f57f70aa | 28 | #define CONFIG_AP1000 1 /* ...on an AP1000 board */ |
7521af1c | 29 | |
2ae18241 WD |
30 | /* |
31 | * Start at bottom of RAM, but at an aliased address so that it looks | |
32 | * like it's not in RAM. This is a bit of voodoo to allow it to be | |
33 | * run from RAM instead of Flash. | |
34 | */ | |
35 | #define CONFIG_SYS_TEXT_BASE 0x08000000 | |
2ced53e1 | 36 | #define CONFIG_SYS_LDSCRIPT "board/amirix/ap1000/u-boot.lds" |
2ae18241 | 37 | |
f57f70aa | 38 | #define CONFIG_PCI 1 |
7521af1c | 39 | |
6d0f6bcf JCPV |
40 | #define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ |
41 | #define CONFIG_SYS_PROMPT "0> " | |
7521af1c | 42 | |
f57f70aa | 43 | #define CONFIG_COMMAND_EDIT 1 |
7521af1c WD |
44 | #define CONFIG_COMPLETE_ADDRESSES 1 |
45 | ||
5a1aceb0 | 46 | #define CONFIG_ENV_IS_IN_FLASH 1 |
6d0f6bcf | 47 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
7521af1c | 48 | |
9314cee6 | 49 | #ifdef CONFIG_ENV_IS_IN_NVRAM |
5a1aceb0 | 50 | #undef CONFIG_ENV_IS_IN_FLASH |
7521af1c | 51 | #else |
5a1aceb0 | 52 | #ifdef CONFIG_ENV_IS_IN_FLASH |
9314cee6 | 53 | #undef CONFIG_ENV_IS_IN_NVRAM |
7521af1c WD |
54 | #endif |
55 | #endif | |
56 | ||
f57f70aa WD |
57 | #define CONFIG_BAUDRATE 57600 |
58 | #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ | |
7521af1c | 59 | |
f57f70aa | 60 | #define CONFIG_BOOTCOMMAND "" /* autoboot command */ |
7521af1c | 61 | |
f57f70aa | 62 | #define CONFIG_BOOTARGS "console=ttyS0,57600" |
7521af1c | 63 | |
f57f70aa | 64 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
6d0f6bcf | 65 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
7521af1c | 66 | |
498ff9a2 | 67 | |
11799434 JL |
68 | /* |
69 | * BOOTP options | |
70 | */ | |
71 | #define CONFIG_BOOTP_BOOTFILESIZE | |
72 | #define CONFIG_BOOTP_BOOTPATH | |
73 | #define CONFIG_BOOTP_GATEWAY | |
74 | #define CONFIG_BOOTP_HOSTNAME | |
75 | ||
498ff9a2 JL |
76 | /* |
77 | * Command line configuration. | |
78 | */ | |
79 | #include <config_cmd_default.h> | |
80 | ||
81 | #define CONFIG_CMD_ASKENV | |
82 | #define CONFIG_CMD_DHCP | |
83 | #define CONFIG_CMD_ELF | |
84 | #define CONFIG_CMD_IRQ | |
85 | #define CONFIG_CMD_MVENV | |
86 | #define CONFIG_CMD_PCI | |
87 | #define CONFIG_CMD_PING | |
88 | ||
7521af1c | 89 | |
f57f70aa | 90 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
7521af1c | 91 | |
f57f70aa | 92 | #define CONFIG_SYS_CLK_FREQ 30000000 |
7521af1c | 93 | |
f57f70aa | 94 | #define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */ |
7521af1c | 95 | |
ee8028b7 WD |
96 | /* |
97 | * I2C | |
98 | */ | |
99 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
100 | #define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ | |
101 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
102 | #define CONFIG_SYS_I2C_SPEED 400000 | |
103 | ||
7521af1c WD |
104 | /* |
105 | * Miscellaneous configurable options | |
106 | */ | |
6d0f6bcf | 107 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
498ff9a2 | 108 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 109 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
7521af1c | 110 | #else |
6d0f6bcf | 111 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
7521af1c | 112 | #endif |
6d0f6bcf JCPV |
113 | /* usually: (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) */ |
114 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+4+16) /* Print Buffer Size */ | |
115 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
116 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
7521af1c | 117 | |
6d0f6bcf JCPV |
118 | #define CONFIG_SYS_ALT_MEMTEST 1 |
119 | #define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ | |
120 | #define CONFIG_SYS_MEMTEST_END 0x01000000 /* 4 ... 16 MB in DRAM */ | |
7521af1c WD |
121 | |
122 | /* | |
6d0f6bcf JCPV |
123 | * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1. |
124 | * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31. | |
125 | * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value. | |
7521af1c WD |
126 | * The Linux BASE_BAUD define should match this configuration. |
127 | * baseBaud = cpuClock/(uartDivisor*16) | |
6d0f6bcf | 128 | * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock, |
7521af1c WD |
129 | * set Linux BASE_BAUD to 403200. |
130 | */ | |
6d0f6bcf JCPV |
131 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ |
132 | #undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ | |
133 | ||
134 | #define CONFIG_SYS_NS16550_CLK 40000000 | |
135 | #define CONFIG_SYS_DUART_CHAN 0 | |
136 | #define CONFIG_SYS_NS16550_COM1 (0x4C000000 + 0x1000) | |
137 | #define CONFIG_SYS_NS16550_COM2 (0x4C800000 + 0x1000) | |
138 | #define CONFIG_SYS_NS16550_REG_SIZE 4 | |
139 | #define CONFIG_SYS_NS16550 1 | |
140 | #define CONFIG_SYS_INIT_CHAN1 1 | |
141 | #define CONFIG_SYS_INIT_CHAN2 0 | |
7521af1c WD |
142 | |
143 | /* The following table includes the supported baudrates */ | |
6d0f6bcf | 144 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
7521af1c WD |
145 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} |
146 | ||
6d0f6bcf JCPV |
147 | #define CONFIG_SYS_LOAD_ADDR 0x00200000 /* default load address */ |
148 | #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
7521af1c | 149 | |
6d0f6bcf | 150 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
7521af1c WD |
151 | |
152 | /*----------------------------------------------------------------------- | |
153 | * Start addresses for the final memory configuration | |
154 | * (Set up by the startup code) | |
6d0f6bcf | 155 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
7521af1c | 156 | */ |
6d0f6bcf JCPV |
157 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
158 | #define CONFIG_SYS_FLASH_BASE 0x20000000 | |
14d0a02a | 159 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf JCPV |
160 | #define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */ |
161 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ | |
7521af1c WD |
162 | |
163 | /* | |
164 | * For booting Linux, the board info and command line data | |
165 | * have to be in the first 8 MB of memory, since this is | |
166 | * the maximum mapped by the Linux kernel during initialization. | |
167 | */ | |
6d0f6bcf | 168 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
7521af1c WD |
169 | /*----------------------------------------------------------------------- |
170 | * FLASH organization | |
171 | */ | |
6d0f6bcf JCPV |
172 | #define CONFIG_SYS_FLASH_CFI 1 |
173 | #define CONFIG_SYS_PROGFLASH_BASE CONFIG_SYS_FLASH_BASE | |
174 | #define CONFIG_SYS_CONFFLASH_BASE 0x24000000 | |
7521af1c | 175 | |
6d0f6bcf JCPV |
176 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
177 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ | |
7521af1c | 178 | |
6d0f6bcf JCPV |
179 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
180 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
7521af1c | 181 | |
6d0f6bcf | 182 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware protection */ |
7521af1c WD |
183 | |
184 | /* BEG ENVIRONNEMENT FLASH */ | |
5a1aceb0 | 185 | #ifdef CONFIG_ENV_IS_IN_FLASH |
0e8d1586 JCPV |
186 | #define CONFIG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */ |
187 | #define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ | |
188 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* see README - env sector total size */ | |
7521af1c WD |
189 | #endif |
190 | /* END ENVIRONNEMENT FLASH */ | |
191 | /*----------------------------------------------------------------------- | |
192 | * NVRAM organization | |
193 | */ | |
6d0f6bcf JCPV |
194 | #define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */ |
195 | #define CONFIG_SYS_NVRAM_SIZE 0x1ff8 /* NVRAM size */ | |
7521af1c | 196 | |
9314cee6 | 197 | #ifdef CONFIG_ENV_IS_IN_NVRAM |
0e8d1586 JCPV |
198 | #define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */ |
199 | #define CONFIG_ENV_ADDR \ | |
6d0f6bcf | 200 | (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */ |
7521af1c | 201 | #endif |
7521af1c WD |
202 | |
203 | /* | |
204 | * Init Memory Controller: | |
205 | * | |
206 | * BR0/1 and OR0/1 (FLASH) | |
207 | */ | |
208 | ||
6d0f6bcf | 209 | #define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */ |
f57f70aa | 210 | #define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ |
7521af1c WD |
211 | |
212 | /* Configuration Port location */ | |
f57f70aa | 213 | #define CONFIG_PORT_ADDR 0xF0000500 |
7521af1c WD |
214 | |
215 | /*----------------------------------------------------------------------- | |
216 | * Definitions for initial stack pointer and data area (in DPRAM) | |
217 | */ | |
218 | ||
6d0f6bcf | 219 | #define CONFIG_SYS_INIT_RAM_ADDR 0x400000 /* inside of SDRAM */ |
553f0982 | 220 | #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */ |
25ddd1fb | 221 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 222 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
7521af1c WD |
223 | |
224 | /*----------------------------------------------------------------------- | |
225 | * Definitions for Serial Presence Detect EEPROM address | |
226 | * (to get SDRAM settings) | |
227 | */ | |
3df5bea0 | 228 | #define SPD_EEPROM_ADDRESS 0x50 |
7521af1c | 229 | |
498ff9a2 | 230 | #if defined(CONFIG_CMD_KGDB) |
3df5bea0 | 231 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
f57f70aa | 232 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
7521af1c WD |
233 | #endif |
234 | ||
235 | /* JFFS2 stuff */ | |
236 | ||
6d0f6bcf JCPV |
237 | #define CONFIG_SYS_JFFS2_FIRST_BANK 0 |
238 | #define CONFIG_SYS_JFFS2_NUM_BANKS 1 | |
239 | #define CONFIG_SYS_JFFS2_FIRST_SECTOR 1 | |
7521af1c | 240 | |
7521af1c WD |
241 | #define CONFIG_E1000 |
242 | ||
6d0f6bcf JCPV |
243 | #define CONFIG_SYS_ETH_DEV_FN 0x0800 |
244 | #define CONFIG_SYS_ETH_IOBASE 0x31000000 | |
245 | #define CONFIG_SYS_ETH_MEMBASE 0x32000000 | |
7521af1c | 246 | |
3df5bea0 | 247 | #endif /* __CONFIG_H */ |