projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| c93f7096 SR |
1 | /* |
| 2 | * (C) Copyright 2001-2003 | |
| 3 | * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com | |
| 4 | * | |
| 5 | * See file CREDITS for list of people who contributed to this | |
| 6 | * project. | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or | |
| 9 | * modify it under the terms of the GNU General Public License as | |
| 10 | * published by the Free Software Foundation; either version 2 of | |
| 11 | * the License, or (at your option) any later version. | |
| 12 | * | |
| 13 | * This program is distributed in the hope that it will be useful, | |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | * GNU General Public License for more details. | |
| 17 | * | |
| 18 | * You should have received a copy of the GNU General Public License | |
| 19 | * along with this program; if not, write to the Free Software | |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 21 | * MA 02111-1307 USA | |
| 22 | */ | |
| 23 | ||
| 24 | /* | |
| 25 | * board/config.h - configuration options, board specific | |
| 26 | */ | |
| 27 | ||
| 28 | #ifndef __CONFIG_H | |
| 29 | #define __CONFIG_H | |
| 30 | ||
| 31 | /* | |
| 32 | * High Level Configuration Options | |
| 33 | * (easy to change) | |
| 34 | */ | |
| 35 | ||
| 36 | #define CONFIG_405EP 1 /* This is a PPC405 CPU */ | |
| 37 | #define CONFIG_4xx 1 /* ...member of PPC4xx family */ | |
| 38 | #define CONFIG_ASH405 1 /* ...on a ASH405 board */ | |
| 39 | ||
| 40 | #define CONFIG_BOARD_PRE_INIT 1 /* call board_pre_init() */ | |
| 41 | #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ | |
| 42 | ||
| 43 | #define CONFIG_SYS_CLK_FREQ 33333334 /* external frequency to pll */ | |
| 44 | ||
| 45 | #define CONFIG_BAUDRATE 9600 | |
| 46 | #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ | |
| 47 | ||
| 48 | #undef CONFIG_BOOTARGS | |
| 49 | #define CONFIG_RAMBOOTCOMMAND \ | |
| 50 | "setenv bootargs root=/dev/ram rw nfsroot=$(serverip):$(rootpath) " \ | |
| 51 | "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \ | |
| 52 | "bootm ffc00000 ffca0000" | |
| 53 | #define CONFIG_NFSBOOTCOMMAND \ | |
| 54 | "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ | |
| 55 | "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \ | |
| 56 | "bootm ffc00000" | |
| 57 | #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND | |
| 58 | ||
| 59 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
| 60 | #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
| 61 | ||
| 62 | #define CONFIG_MII 1 /* MII PHY management */ | |
| 63 | #define CONFIG_PHY_ADDR 0 /* PHY address */ | |
| 64 | ||
| 65 | #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ | |
| 66 | CFG_CMD_DHCP | \ | |
| 67 | CFG_CMD_IRQ | \ | |
| 68 | CFG_CMD_ELF | \ | |
| 69 | CFG_CMD_NAND | \ | |
| 70 | CFG_CMD_DATE | \ | |
| 71 | CFG_CMD_I2C | \ | |
| a0e135b4 SR |
72 | CFG_CMD_MII | \ |
| 73 | CFG_CMD_PING | \ | |
| c93f7096 SR |
74 | CFG_CMD_EEPROM ) |
| 75 | ||
| 76 | /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ | |
| 77 | #include <cmd_confdefs.h> | |
| 78 | ||
| 79 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
| 80 | ||
| 81 | #define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/ | |
| 82 | #define CFG_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */ | |
| 83 | ||
| 84 | #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ | |
| 85 | ||
| 86 | /* | |
| 87 | * Miscellaneous configurable options | |
| 88 | */ | |
| 89 | #define CFG_LONGHELP /* undef to save memory */ | |
| 90 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
| 91 | ||
| 92 | #undef CFG_HUSH_PARSER /* use "hush" command parser */ | |
| 93 | #ifdef CFG_HUSH_PARSER | |
| 94 | #define CFG_PROMPT_HUSH_PS2 "> " | |
| 95 | #endif | |
| 96 | ||
| 97 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
| 98 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ | |
| 99 | #else | |
| 100 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
| 101 | #endif | |
| 102 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
| 103 | #define CFG_MAXARGS 16 /* max number of command args */ | |
| 104 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
| 105 | ||
| 106 | #define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ | |
| 107 | ||
| 108 | #define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ | |
| 109 | ||
| 110 | #define CFG_MEMTEST_START 0x0400000 /* memtest works on */ | |
| 111 | #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
| 112 | ||
| 113 | #undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ | |
| 114 | #define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ | |
| 115 | #define CFG_BASE_BAUD 691200 | |
| 116 | #undef CONFIG_UART1_CONSOLE /* define for uart1 as console */ | |
| 117 | ||
| 118 | /* The following table includes the supported baudrates */ | |
| 119 | #define CFG_BAUDRATE_TABLE \ | |
| 8bde7f77 WD |
120 | { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ |
| 121 | 57600, 115200, 230400, 460800, 921600 } | |
| c93f7096 SR |
122 | |
| 123 | #define CFG_LOAD_ADDR 0x100000 /* default load address */ | |
| 124 | #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
| 125 | ||
| 126 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
| 127 | ||
| 128 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ | |
| 129 | ||
| 53cf9435 SR |
130 | #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ |
| 131 | ||
| 132 | #define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ | |
| 133 | ||
| c93f7096 SR |
134 | /*----------------------------------------------------------------------- |
| 135 | * NAND-FLASH stuff | |
| 136 | *----------------------------------------------------------------------- | |
| 137 | */ | |
| 138 | #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ | |
| 139 | #define SECTORSIZE 512 | |
| 140 | ||
| 141 | #define ADDR_COLUMN 1 | |
| 142 | #define ADDR_PAGE 2 | |
| 143 | #define ADDR_COLUMN_PAGE 3 | |
| 144 | ||
| 145 | #define NAND_ChipID_UNKNOWN 0x00 | |
| 146 | #define NAND_MAX_FLOORS 1 | |
| 147 | #define NAND_MAX_CHIPS 1 | |
| 148 | ||
| 149 | #define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ | |
| 150 | #define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ | |
| 151 | #define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ | |
| 152 | #define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ | |
| 153 | ||
| 154 | #define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0) | |
| 155 | #define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0) | |
| 156 | #define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0) | |
| 157 | #define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0) | |
| 158 | #define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0) | |
| 159 | #define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0) | |
| 160 | #define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY)) | |
| 161 | ||
| 162 | #define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) | |
| 163 | #define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) | |
| 164 | #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) | |
| 165 | #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) | |
| 166 | ||
| 167 | /*----------------------------------------------------------------------- | |
| 168 | * PCI stuff | |
| 169 | *----------------------------------------------------------------------- | |
| 170 | */ | |
| 171 | #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ | |
| 172 | #define PCI_HOST_FORCE 1 /* configure as pci host */ | |
| 173 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ | |
| 174 | ||
| 175 | #define CONFIG_PCI /* include pci support */ | |
| 176 | #define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */ | |
| 177 | #undef CONFIG_PCI_PNP /* do pci plug-and-play */ | |
| 8bde7f77 | 178 | /* resource configuration */ |
| c93f7096 SR |
179 | |
| 180 | #undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ | |
| 181 | ||
| 182 | #define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ | |
| 183 | #define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ | |
| 184 | #define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ | |
| 185 | #define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ | |
| 186 | #define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ | |
| 187 | #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ | |
| 188 | #define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ | |
| 189 | #define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ | |
| 190 | #define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ | |
| 191 | ||
| 192 | /*----------------------------------------------------------------------- | |
| 193 | * Start addresses for the final memory configuration | |
| 194 | * (Set up by the startup code) | |
| 195 | * Please note that CFG_SDRAM_BASE _must_ start at 0 | |
| 196 | */ | |
| 197 | #define CFG_SDRAM_BASE 0x00000000 | |
| 198 | #define CFG_FLASH_BASE 0xFFFC0000 | |
| 199 | #define CFG_MONITOR_BASE CFG_FLASH_BASE | |
| 200 | #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ | |
| 201 | #define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ | |
| 202 | ||
| 203 | /* | |
| 204 | * For booting Linux, the board info and command line data | |
| 205 | * have to be in the first 8 MB of memory, since this is | |
| 206 | * the maximum mapped by the Linux kernel during initialization. | |
| 207 | */ | |
| 208 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
| 209 | /*----------------------------------------------------------------------- | |
| 210 | * FLASH organization | |
| 211 | */ | |
| 212 | #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
| 213 | #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ | |
| 214 | ||
| 215 | #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ | |
| 216 | #define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ | |
| 217 | ||
| 218 | #define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ | |
| 219 | #define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ | |
| 220 | #define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ | |
| 221 | /* | |
| 222 | * The following defines are added for buggy IOP480 byte interface. | |
| 223 | * All other boards should use the standard values (CPCI405 etc.) | |
| 224 | */ | |
| 225 | #define CFG_FLASH_READ0 0x0000 /* 0 is standard */ | |
| 226 | #define CFG_FLASH_READ1 0x0001 /* 1 is standard */ | |
| 227 | #define CFG_FLASH_READ2 0x0002 /* 2 is standard */ | |
| 228 | ||
| 229 | #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ | |
| 230 | ||
| 231 | #if 0 /* test-only */ | |
| 232 | #define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ | |
| 233 | #define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ | |
| 234 | #endif | |
| 235 | ||
| 236 | /*----------------------------------------------------------------------- | |
| 237 | * Environment Variable setup | |
| 238 | */ | |
| 239 | #define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ | |
| 240 | #define CFG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ | |
| 241 | #define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ | |
| 8bde7f77 | 242 | /* total size of a CAT24WC16 is 2048 bytes */ |
| c93f7096 SR |
243 | |
| 244 | #define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ | |
| 245 | #define CFG_NVRAM_SIZE 242 /* NVRAM size */ | |
| 246 | ||
| 247 | /*----------------------------------------------------------------------- | |
| 248 | * I2C EEPROM (CAT24WC16) for environment | |
| 249 | */ | |
| 250 | #define CONFIG_HARD_I2C /* I2c with hardware support */ | |
| 251 | #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ | |
| 252 | #define CFG_I2C_SLAVE 0x7F | |
| 253 | ||
| 254 | #define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ | |
| 255 | #define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ | |
| 256 | /* mask of address bits that overflow into the "EEPROM chip address" */ | |
| 257 | #define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 | |
| 258 | #define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ | |
| 259 | /* 16 byte page write mode using*/ | |
| 260 | /* last 4 bits of the address */ | |
| 261 | #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ | |
| 262 | #define CFG_EEPROM_PAGE_WRITE_ENABLE | |
| 263 | ||
| 264 | /*----------------------------------------------------------------------- | |
| 265 | * Cache Configuration | |
| 266 | */ | |
| 267 | #define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */ | |
| 8bde7f77 | 268 | /* have only 8kB, 16kB is save here */ |
| c93f7096 SR |
269 | #define CFG_CACHELINE_SIZE 32 /* ... */ |
| 270 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
| 271 | #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ | |
| 272 | #endif | |
| 273 | ||
| 274 | /* | |
| 275 | * Init Memory Controller: | |
| 276 | * | |
| 277 | * BR0/1 and OR0/1 (FLASH) | |
| 278 | */ | |
| 279 | ||
| 280 | #define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ | |
| 281 | ||
| 282 | /*----------------------------------------------------------------------- | |
| 283 | * External Bus Controller (EBC) Setup | |
| 284 | */ | |
| 285 | ||
| 286 | /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ | |
| 287 | #define CFG_EBC_PB0AP 0x92015480 | |
| 7a8e9bed | 288 | /*#define CFG_EBC_PB0AP 0x08055880 /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */ |
| c93f7096 SR |
289 | #define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ |
| 290 | ||
| 291 | /* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */ | |
| 292 | #define CFG_EBC_PB1AP 0x92015480 | |
| 293 | #define CFG_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */ | |
| 294 | ||
| 295 | /* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */ | |
| 296 | #define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ | |
| 297 | #define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ | |
| 298 | ||
| 299 | /* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */ | |
| 300 | #define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ | |
| 301 | #define CFG_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ | |
| 302 | ||
| 303 | #define CAN_BA 0xF0000000 /* CAN Base Address */ | |
| 304 | #define DUART0_BA 0xF0000400 /* DUART Base Address */ | |
| 305 | #define DUART1_BA 0xF0000408 /* DUART Base Address */ | |
| 306 | #define DUART2_BA 0xF0000410 /* DUART Base Address */ | |
| 307 | #define DUART3_BA 0xF0000418 /* DUART Base Address */ | |
| 308 | #define RTC_BA 0xF0000500 /* RTC Base Address */ | |
| 309 | #define CFG_NAND_BASE 0xF4000000 | |
| 310 | ||
| 311 | /*----------------------------------------------------------------------- | |
| 312 | * FPGA stuff | |
| 313 | */ | |
| 314 | #define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ | |
| 315 | #define CFG_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/ | |
| 316 | ||
| 317 | /* FPGA program pin configuration */ | |
| 318 | #define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ | |
| 319 | #define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ | |
| 320 | #define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ | |
| 321 | #define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ | |
| 322 | #define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ | |
| 323 | ||
| 324 | /*----------------------------------------------------------------------- | |
| 325 | * Definitions for initial stack pointer and data area (in data cache) | |
| 326 | */ | |
| 327 | /* use on chip memory ( OCM ) for temperary stack until sdram is tested */ | |
| 328 | #define CFG_TEMP_STACK_OCM 1 | |
| 329 | ||
| 330 | /* On Chip Memory location */ | |
| 331 | #define CFG_OCM_DATA_ADDR 0xF8000000 | |
| 332 | #define CFG_OCM_DATA_SIZE 0x1000 | |
| 333 | #define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ | |
| 334 | #define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ | |
| 335 | ||
| 336 | #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ | |
| 337 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
| 338 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
| 339 | ||
| 340 | /*----------------------------------------------------------------------- | |
| 341 | * Definitions for GPIO setup (PPC405EP specific) | |
| 342 | * | |
| 343 | * GPIO0[0] - External Bus Controller BLAST output | |
| 344 | * GPIO0[1-9] - Instruction trace outputs -> GPIO | |
| 345 | * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs | |
| 346 | * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO | |
| 347 | * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs | |
| 348 | * GPIO0[24-27] - UART0 control signal inputs/outputs | |
| 349 | * GPIO0[28-29] - UART1 data signal input/output | |
| 350 | * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs | |
| 351 | */ | |
| 352 | #define CFG_GPIO0_OSRH 0x40000550 | |
| 353 | #define CFG_GPIO0_OSRL 0x00000110 | |
| 354 | #define CFG_GPIO0_ISR1H 0x00000000 | |
| 355 | #define CFG_GPIO0_ISR1L 0x15555445 | |
| 356 | #define CFG_GPIO0_TSRH 0x00000000 | |
| 357 | #define CFG_GPIO0_TSRL 0x00000000 | |
| 358 | #define CFG_GPIO0_TCR 0xF7FE0014 | |
| 359 | ||
| 360 | #define CFG_DUART_RST (0x80000000 >> 14) | |
| 361 | ||
| 362 | /* | |
| 363 | * Internal Definitions | |
| 364 | * | |
| 365 | * Boot Flags | |
| 366 | */ | |
| 367 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
| 368 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
| 369 | ||
| 370 | /* | |
| 371 | * Default speed selection (cpu_plb_opb_ebc) in mhz. | |
| 372 | * This value will be set if iic boot eprom is disabled. | |
| 373 | */ | |
| 374 | #if 0 | |
| 375 | #define PLLMR0_DEFAULT PLLMR0_266_133_66_33 | |
| 376 | #define PLLMR1_DEFAULT PLLMR1_266_133_66_33 | |
| 377 | #endif | |
| 378 | #if 1 | |
| 379 | #define PLLMR0_DEFAULT PLLMR0_200_100_50_33 | |
| 380 | #define PLLMR1_DEFAULT PLLMR1_200_100_50_33 | |
| 381 | #endif | |
| 382 | #if 0 | |
| 383 | #define PLLMR0_DEFAULT PLLMR0_133_66_66_33 | |
| 384 | #define PLLMR1_DEFAULT PLLMR1_133_66_66_33 | |
| 385 | #endif | |
| 386 | ||
| 387 | #endif /* __CONFIG_H */ |