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Commit | Line | Data |
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2d24a3a7 | 1 | /* |
5797b821 | 2 | * Copyright (C) 2004-2005 Arabella Software Ltd. |
2d24a3a7 WD |
3 | * Yuli Barcohen <yuli@arabellasw.com> |
4 | * | |
5 | * Support for Analogue&Micro Adder boards family. | |
6 | * Tested on AdderII and Adder87x. | |
7 | * | |
1a459660 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
2d24a3a7 WD |
9 | */ |
10 | #ifndef __CONFIG_H | |
11 | #define __CONFIG_H | |
12 | ||
13 | #if !defined(CONFIG_MPC875) && !defined(CONFIG_MPC852T) | |
14 | #define CONFIG_MPC875 | |
15 | #endif | |
16 | ||
17 | #define CONFIG_ADDER /* Analogue&Micro Adder board */ | |
18 | ||
2ae18241 WD |
19 | #define CONFIG_SYS_TEXT_BASE 0xFE000000 |
20 | ||
2d24a3a7 WD |
21 | #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
22 | #define CONFIG_BAUDRATE 38400 | |
23 | ||
5797b821 WD |
24 | #define CONFIG_ETHER_ON_FEC1 |
25 | #define CONFIG_ETHER_ON_FEC2 | |
a6f5f317 BD |
26 | #define CONFIG_HAS_ETH0 |
27 | #define CONFIG_HAS_ETH1 | |
5797b821 WD |
28 | |
29 | #if defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2) | |
6d0f6bcf | 30 | #define CONFIG_SYS_DISCOVER_PHY |
0f3ba7e9 | 31 | #define CONFIG_MII_INIT 1 |
2d24a3a7 | 32 | #define FEC_ENET |
5797b821 | 33 | #endif /* CONFIG_ETHER_ON_FEC || CONFIG_ETHER_ON_FEC2 */ |
2d24a3a7 | 34 | |
66ca92a5 WD |
35 | #define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */ |
36 | #define CONFIG_8xx_CPUCLK_DEFAULT 50000000 | |
6d0f6bcf | 37 | #define CONFIG_SYS_8xx_CPUCLK_MIN 40000000 |
66ca92a5 | 38 | #ifdef CONFIG_MPC852T |
6d0f6bcf | 39 | #define CONFIG_SYS_8xx_CPUCLK_MAX 50000000 |
66ca92a5 | 40 | #else |
6d0f6bcf | 41 | #define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 |
66ca92a5 | 42 | #endif /* CONFIG_MPC852T */ |
2d24a3a7 | 43 | |
2d24a3a7 | 44 | |
11799434 JL |
45 | /* |
46 | * BOOTP options | |
47 | */ | |
48 | #define CONFIG_BOOTP_BOOTFILESIZE | |
49 | #define CONFIG_BOOTP_BOOTPATH | |
50 | #define CONFIG_BOOTP_GATEWAY | |
51 | #define CONFIG_BOOTP_HOSTNAME | |
52 | ||
53 | ||
498ff9a2 JL |
54 | /* |
55 | * Command line configuration. | |
56 | */ | |
57 | #include <config_cmd_default.h> | |
58 | ||
5728be38 WD |
59 | #define CONFIG_CMD_DHCP |
60 | #define CONFIG_CMD_IMMAP | |
61 | #define CONFIG_CMD_MII | |
62 | #define CONFIG_CMD_PING | |
498ff9a2 | 63 | |
2d24a3a7 WD |
64 | |
65 | #define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds */ | |
66 | #define CONFIG_BOOTCOMMAND "bootm fe040000" /* Autoboot command */ | |
5797b821 | 67 | #define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw mtdparts=1M(ROM)ro,-(root)" |
2d24a3a7 WD |
68 | |
69 | #define CONFIG_BZIP2 /* Include support for bzip2 compressed images */ | |
70 | #undef CONFIG_WATCHDOG /* Disable platform specific watchdog */ | |
71 | ||
72 | /*----------------------------------------------------------------------- | |
73 | * Miscellaneous configurable options | |
74 | */ | |
6d0f6bcf JCPV |
75 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ |
76 | #define CONFIG_SYS_HUSH_PARSER | |
6d0f6bcf JCPV |
77 | #define CONFIG_SYS_LONGHELP /* #undef to save memory */ |
78 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
79 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ | |
80 | #define CONFIG_SYS_MAXARGS 16 /* Max number of command args */ | |
81 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
2d24a3a7 | 82 | |
6d0f6bcf | 83 | #define CONFIG_SYS_LOAD_ADDR 0x400000 /* Default load address */ |
2d24a3a7 | 84 | |
6d0f6bcf | 85 | #define CONFIG_SYS_HZ 1000 /* Decrementer freq: 1 ms ticks */ |
2d24a3a7 | 86 | |
2d24a3a7 | 87 | /*----------------------------------------------------------------------- |
6d0f6bcf | 88 | * RAM configuration (note that CONFIG_SYS_SDRAM_BASE must be zero) |
2d24a3a7 | 89 | */ |
6d0f6bcf JCPV |
90 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
91 | #define CONFIG_SYS_SDRAM_MAX_SIZE 0x01000000 /* Up to 16 Mbyte */ | |
2d24a3a7 | 92 | |
6d0f6bcf | 93 | #define CONFIG_SYS_MAMR 0x00002114 |
2d24a3a7 | 94 | |
66ca92a5 | 95 | /* |
5797b821 | 96 | * 4096 Up to 4096 SDRAM rows |
66ca92a5 | 97 | * 1000 factor s -> ms |
5797b821 | 98 | * 32 PTP (pre-divider from MPTPR) |
66ca92a5 WD |
99 | * 4 Number of refresh cycles per period |
100 | * 64 Refresh cycle in ms per number of rows | |
101 | */ | |
6d0f6bcf | 102 | #define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) |
66ca92a5 | 103 | |
6d0f6bcf JCPV |
104 | #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ |
105 | #define CONFIG_SYS_MEMTEST_END 0x00500000 /* 1 ... 5 MB in SDRAM */ | |
2d24a3a7 | 106 | |
6d0f6bcf | 107 | #define CONFIG_SYS_RESET_ADDRESS 0x09900000 |
2d24a3a7 WD |
108 | |
109 | /*----------------------------------------------------------------------- | |
110 | * For booting Linux, the board info and command line data | |
111 | * have to be in the first 8 MB of memory, since this is | |
112 | * the maximum mapped by the Linux kernel during initialization. | |
113 | */ | |
6d0f6bcf | 114 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
2d24a3a7 | 115 | |
14d0a02a | 116 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf | 117 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 KB for Monitor */ |
2d24a3a7 | 118 | #ifdef CONFIG_BZIP2 |
6d0f6bcf | 119 | #define CONFIG_SYS_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */ |
2d24a3a7 | 120 | #else |
6d0f6bcf | 121 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */ |
2d24a3a7 WD |
122 | #endif /* CONFIG_BZIP2 */ |
123 | ||
124 | /*----------------------------------------------------------------------- | |
125 | * Flash organisation | |
126 | */ | |
6d0f6bcf JCPV |
127 | #define CONFIG_SYS_FLASH_BASE 0xFE000000 |
128 | #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ | |
00b1883a | 129 | #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ |
6d0f6bcf JCPV |
130 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */ |
131 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max num of sects on one chip */ | |
2d24a3a7 WD |
132 | |
133 | /* Environment is in flash */ | |
5a1aceb0 | 134 | #define CONFIG_ENV_IS_IN_FLASH |
0e8d1586 | 135 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */ |
6d0f6bcf | 136 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
2d24a3a7 | 137 | |
5797b821 WD |
138 | #define CONFIG_ENV_OVERWRITE |
139 | ||
6d0f6bcf JCPV |
140 | #define CONFIG_SYS_OR0_PRELIM 0xFF000774 |
141 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_MS_GPCM | BR_V) | |
2d24a3a7 | 142 | |
6d0f6bcf | 143 | #define CONFIG_SYS_DIRECT_FLASH_TFTP |
26238132 | 144 | |
2d24a3a7 WD |
145 | /*----------------------------------------------------------------------- |
146 | * Internal Memory Map Register | |
147 | */ | |
6d0f6bcf | 148 | #define CONFIG_SYS_IMMR 0xFF000000 |
2d24a3a7 WD |
149 | |
150 | /*----------------------------------------------------------------------- | |
151 | * Definitions for initial stack pointer and data area (in DPRAM) | |
152 | */ | |
6d0f6bcf | 153 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
553f0982 | 154 | #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ |
25ddd1fb | 155 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 156 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
2d24a3a7 WD |
157 | |
158 | /*----------------------------------------------------------------------- | |
159 | * Configuration registers | |
160 | */ | |
161 | #ifdef CONFIG_WATCHDOG | |
6d0f6bcf | 162 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \ |
2d24a3a7 WD |
163 | SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | \ |
164 | SYPCR_SWP) | |
165 | #else | |
6d0f6bcf | 166 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \ |
2d24a3a7 WD |
167 | SYPCR_SWF | SYPCR_SWP) |
168 | #endif /* CONFIG_WATCHDOG */ | |
169 | ||
6d0f6bcf | 170 | #define CONFIG_SYS_SIUMCR (SIUMCR_MLRC01 | SIUMCR_DBGC11) |
2d24a3a7 WD |
171 | |
172 | /* TBSCR - Time Base Status and Control Register */ | |
6d0f6bcf | 173 | #define CONFIG_SYS_TBSCR (TBSCR_TBF | TBSCR_TBE) |
2d24a3a7 WD |
174 | |
175 | /* PISCR - Periodic Interrupt Status and Control */ | |
6d0f6bcf | 176 | #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) |
2d24a3a7 WD |
177 | |
178 | /* PLPRCR - PLL, Low-Power, and Reset Control Register */ | |
6d0f6bcf | 179 | /* #define CONFIG_SYS_PLPRCR PLPRCR_TEXPS */ |
2d24a3a7 WD |
180 | |
181 | /* SCCR - System Clock and reset Control Register */ | |
53677ef1 | 182 | #define SCCR_MASK SCCR_EBDF11 |
6d0f6bcf | 183 | #define CONFIG_SYS_SCCR SCCR_RTSEL |
2d24a3a7 | 184 | |
6d0f6bcf | 185 | #define CONFIG_SYS_DER 0 |
2d24a3a7 WD |
186 | |
187 | /*----------------------------------------------------------------------- | |
188 | * Cache Configuration | |
189 | */ | |
6d0f6bcf | 190 | #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx chips */ |
2d24a3a7 | 191 | |
a6f5f317 BD |
192 | /* pass open firmware flat tree */ |
193 | #define CONFIG_OF_LIBFDT 1 | |
194 | #define CONFIG_OF_BOARD_SETUP 1 | |
195 | ||
2d24a3a7 | 196 | #endif /* __CONFIG_H */ |