[people/ms/u-boot.git] / include / configs / BMW.h

/*
 * (C) Copyright 2001
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 *
 * Configuration settings for the CU824 board.
 *
 */

/* ------------------------------------------------------------------------- */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC824X		1
#define CONFIG_MPC8245		1
#define CONFIG_BMW		1

#define	CONFIG_MISC_INIT_F	1	/* Use misc_init_f()			*/

#define CONFIG_BCM570x		1	/* Use Broadcom BCM570x Ethernet Driver */
#define	CONFIG_TIGON3		1

#define CONFIG_CONS_INDEX	1
#define CONFIG_BAUDRATE		9600
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

#define CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz	*/

#define CONFIG_BOOTCOMMAND	"bootm FF820000"	/* autoboot command	*/
#define CONFIG_BOOTDELAY	5

#define CONFIG_SYS_MAX_DOC_DEVICE      1 /* Only use Onboard TSOP-16MB device */
#define DOC_PASSIVE_PROBE       1
#define CONFIG_SYS_DOC_SUPPORT_2000    1
#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM 1
#define CONFIG_SYS_DOC_SHORT_TIMEOUT    1


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_DATE
#define CONFIG_CMD_DOC
#define CONFIG_CMD_ELF


/* CONFIG_CMD_DOC required legacy NAND support */
#define CONFIG_NAND_LEGACY

#if 0
#define CONFIG_PCI		1
#define CONFIG_PCI_PNP		1	/* PCI plug-and-play */
#endif

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define CONFIG_SYS_PROMPT	"=>"	        /* Monitor Command Prompt	*/
#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/

/* Print Buffer Size
 */
#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)

#define CONFIG_SYS_MAXARGS	8		/* Max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
#define CONFIG_SYS_LOAD_ADDR	0x00100000	/* Default load address		*/

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE	    0x00000000

#define CONFIG_SYS_FLASH_BASE0_PRELIM      0xFFF00000      /* FLASH bank on RCS#0 */
#define CONFIG_SYS_FLASH_BASE1_PRELIM      0xFF800000      /* FLASH bank on RCS#1 */
#define CONFIG_SYS_FLASH_BASE  CONFIG_SYS_MONITOR_BASE
#define CONFIG_SYS_FLASH_BANKS		{ CONFIG_SYS_FLASH_BASE0_PRELIM , CONFIG_SYS_FLASH_BASE1_PRELIM }

/* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the
 * reset vector is actually located at FFB00100, but the 8245
 * takes care of us.
 */
#define CONFIG_SYS_RESET_ADDRESS   0xFFF00100

#define CONFIG_SYS_EUMB_ADDR	    0xFC000000

#define CONFIG_SYS_MONITOR_BASE    TEXT_BASE

#define CONFIG_SYS_MONITOR_LEN	    (256 << 10) /* Reserve 256 kB for Monitor	*/
#define CONFIG_SYS_MALLOC_LEN	    (2048 << 10) /* Reserve 2MB for malloc()	*/

#define CONFIG_SYS_MEMTEST_START   0x00004000	/* memtest works on		*/
#define CONFIG_SYS_MEMTEST_END	    0x04000000	/* 0 ... 32 MB in DRAM		*/

	/* Maximum amount of RAM.
	 */
#define CONFIG_SYS_MAX_RAM_SIZE    0x04000000	/* 0 .. 64 MB of (S)DRAM */


#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
#undef CONFIG_SYS_RAMBOOT
#else
#define CONFIG_SYS_RAMBOOT
#endif


/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area
 */
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MONITOR_LEN
#define CONFIG_SYS_INIT_RAM_END   0x2F00  /* End of used area in DPRAM  */
#define CONFIG_SYS_GBL_DATA_SIZE  128  /* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET  CONFIG_SYS_GBL_DATA_OFFSET

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 * For the detail description refer to the MPC8240 user's manual.
 */

#define CONFIG_SYS_CLK_FREQ  33000000	/* external frequency to pll */
#define CONFIG_SYS_HZ		     1000

#define CONFIG_SYS_ETH_DEV_FN	     0x7800
#define CONFIG_SYS_ETH_IOBASE	     0x00104000

	/* Bit-field values for MCCR1.
	 */
#define CONFIG_SYS_ROMNAL	    0xf
#define CONFIG_SYS_ROMFAL	    0x1f
#define CONFIG_SYS_DBUS_SIZE       0x3

	/* Bit-field values for MCCR2.
	 */
#define CONFIG_SYS_TSWAIT	    0x5		    /* Transaction Start Wait States timer */
#define CONFIG_SYS_REFINT	    0x400	    /* Refresh interval	FIXME: was 0t430		*/

	/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
	 */
#define CONFIG_SYS_BSTOPRE	    0		/* FIXME: was 192 */

	/* Bit-field values for MCCR3.
	 */
#define CONFIG_SYS_REFREC	    2	    /* Refresh to activate interval */

	/* Bit-field values for MCCR4.
	 */
#define CONFIG_SYS_PRETOACT	    2	    /* Precharge to activate interval FIXME: was 2	*/
#define CONFIG_SYS_ACTTOPRE	    5	    /* Activate to Precharge interval FIXME: was 5	*/
#define CONFIG_SYS_SDMODE_CAS_LAT  3	    /* SDMODE CAS latancy */
#define CONFIG_SYS_SDMODE_WRAP	    0	    /* SDMODE wrap type	*/
#define CONFIG_SYS_SDMODE_BURSTLEN 3	    /* SDMODE Burst length */
#define CONFIG_SYS_ACTORW	    0xa		/* FIXME was 2 */
#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1

#define CONFIG_SYS_PGMAX           0x0 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/

#define CONFIG_SYS_SDRAM_DSCD	0x20	/* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */

/* Memory bank settings.
 * Only bits 20-29 are actually used from these vales to set the
 * start/end addresses. The upper two bits will always be 0, and the lower
 * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
 * address. Refer to the MPC8240 book.
 */

#define CONFIG_SYS_BANK0_START	    0x00000000
#define CONFIG_SYS_BANK0_END	    (CONFIG_SYS_MAX_RAM_SIZE - 1)
#define CONFIG_SYS_BANK0_ENABLE    1
#define CONFIG_SYS_BANK1_START	    0x3ff00000
#define CONFIG_SYS_BANK1_END	    0x3fffffff
#define CONFIG_SYS_BANK1_ENABLE    0
#define CONFIG_SYS_BANK2_START	    0x3ff00000
#define CONFIG_SYS_BANK2_END	    0x3fffffff
#define CONFIG_SYS_BANK2_ENABLE    0
#define CONFIG_SYS_BANK3_START	    0x3ff00000
#define CONFIG_SYS_BANK3_END	    0x3fffffff
#define CONFIG_SYS_BANK3_ENABLE    0
#define CONFIG_SYS_BANK4_START	    0x3ff00000
#define CONFIG_SYS_BANK4_END	    0x3fffffff
#define CONFIG_SYS_BANK4_ENABLE    0
#define CONFIG_SYS_BANK5_START	    0x3ff00000
#define CONFIG_SYS_BANK5_END	    0x3fffffff
#define CONFIG_SYS_BANK5_ENABLE    0
#define CONFIG_SYS_BANK6_START	    0x3ff00000
#define CONFIG_SYS_BANK6_END	    0x3fffffff
#define CONFIG_SYS_BANK6_ENABLE    0
#define CONFIG_SYS_BANK7_START	    0x3ff00000
#define CONFIG_SYS_BANK7_END	    0x3fffffff
#define CONFIG_SYS_BANK7_ENABLE    0

#define CONFIG_SYS_ODCR	    0xff

#define CONFIG_PCI              1 /* Include PCI support */
#undef CONFIG_PCI_PNP

/* PCI Memory space(s) */
#define PCI_MEM_SPACE1_START	0x80000000
#define PCI_MEM_SPACE2_START	0xfd000000

/* ROM Spaces */
#include "../board/bmw/bmw.h"

/* BAT configuration */
#define CONFIG_SYS_IBAT0L  (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U  (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)

#define CONFIG_SYS_IBAT1L  (0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT1U  (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)

#define CONFIG_SYS_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)

#define CONFIG_SYS_IBAT3L  (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT3U  (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)

#define CONFIG_SYS_DBAT0L  CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U  CONFIG_SYS_IBAT0U
#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
#define CONFIG_SYS_DBAT2L  CONFIG_SYS_IBAT2L
#define CONFIG_SYS_DBAT2U  CONFIG_SYS_IBAT2U
#define CONFIG_SYS_DBAT3L  CONFIG_SYS_IBAT3L
#define CONFIG_SYS_DBAT3U  CONFIG_SYS_IBAT3U

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	    (8 << 20)	/* Initial Memory map for Linux */

/*
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	0	/* Max number of flash banks	    */
#define CONFIG_SYS_MAX_FLASH_SECT	64	/* Max number of sectors per  flash */

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */

/*
 * Warining: environment is not EMBEDDED in the U-Boot code.
 * It's stored in flash separately.
 */
#define CONFIG_ENV_IS_IN_NVRAM      1
#define CONFIG_ENV_OVERWRITE     1
#define CONFIG_SYS_NVRAM_ACCESS_ROUTINE 1
#define CONFIG_ENV_ADDR		0x7c004000 /* right at the start of NVRAM  */
#define CONFIG_ENV_SIZE		0x1ff0	/* Size of the Environment - 8K	   */
#define CONFIG_ENV_OFFSET		0	/* starting right at the beginning */

/*
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	32
#if defined(CONFIG_CMD_KGDB)
#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value   */
#endif

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM		0x02	/* Software reboot		    */


#endif	/* __CONFIG_H */
Commit	Line	Data
c609719b WD	1	/*
	2	* (C) Copyright 2001
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	*
	26	* Configuration settings for the CU824 board.
	27	*
	28	*/
	29
	30	/* ------------------------------------------------------------------------- */
	31
	32	/*
	33	* board/config.h - configuration options, board specific
	34	*/
	35
	36	#ifndef __CONFIG_H
	37	#define __CONFIG_H
	38
	39	/*
	40	* High Level Configuration Options
	41	* (easy to change)
	42	*/
	43
	44	#define CONFIG_MPC824X 1
	45	#define CONFIG_MPC8245 1
	46	#define CONFIG_BMW 1
	47
c837dcb1 WD	48	#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
	49
	50	#define CONFIG_BCM570x 1 /* Use Broadcom BCM570x Ethernet Driver */
c609719b WD	51	#define CONFIG_TIGON3 1
	52
	53	#define CONFIG_CONS_INDEX 1
	54	#define CONFIG_BAUDRATE 9600
6d0f6bcf	55	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
c609719b WD	56
	57	#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
	58
	59	#define CONFIG_BOOTCOMMAND "bootm FF820000" /* autoboot command */
	60	#define CONFIG_BOOTDELAY 5
	61
6d0f6bcf	62	#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Only use Onboard TSOP-16MB device */
c609719b	63	#define DOC_PASSIVE_PROBE 1
6d0f6bcf JCPV	64	#define CONFIG_SYS_DOC_SUPPORT_2000 1
	65	#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM 1
	66	#define CONFIG_SYS_DOC_SHORT_TIMEOUT 1
de8b2a6e JL	67
de8b2a6e JL	68
11799434 JL	69	/*
	70	* BOOTP options
	71	*/
	72	#define CONFIG_BOOTP_BOOTFILESIZE
	73	#define CONFIG_BOOTP_BOOTPATH
	74	#define CONFIG_BOOTP_GATEWAY
	75	#define CONFIG_BOOTP_HOSTNAME
	76
	77
de8b2a6e JL	78	/*
	79	* Command line configuration.
	80	*/
	81	#include <config_cmd_default.h>
	82
	83	#define CONFIG_CMD_DATE
	84	#define CONFIG_CMD_DOC
	85	#define CONFIG_CMD_ELF
	86
addb2e16	87
11799434	88	/* CONFIG_CMD_DOC required legacy NAND support */
cc4a0cee	89	#define CONFIG_NAND_LEGACY
addb2e16	90
c609719b	91	#if 0
c609719b WD	92	#define CONFIG_PCI 1
	93	#define CONFIG_PCI_PNP 1 /* PCI plug-and-play */
	94	#endif
	95
c609719b WD	96	/*
	97	* Miscellaneous configurable options
	98	*/
6d0f6bcf JCPV	99	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	100	#define CONFIG_SYS_PROMPT "=>" /* Monitor Command Prompt */
	101	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
c609719b WD	102
	103	/* Print Buffer Size
	104	*/
6d0f6bcf	105	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
c609719b	106
6d0f6bcf JCPV	107	#define CONFIG_SYS_MAXARGS 8 /* Max number of command args */
	108	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
	109	#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */
c609719b WD	110
	111	/*-----------------------------------------------------------------------
	112	* Start addresses for the final memory configuration
	113	* (Set up by the startup code)
6d0f6bcf	114	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
c609719b	115	*/
6d0f6bcf	116	#define CONFIG_SYS_SDRAM_BASE 0x00000000
c609719b	117
6d0f6bcf JCPV	118	#define CONFIG_SYS_FLASH_BASE0_PRELIM 0xFFF00000 /* FLASH bank on RCS#0 */
	119	#define CONFIG_SYS_FLASH_BASE1_PRELIM 0xFF800000 /* FLASH bank on RCS#1 */
	120	#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE
	121	#define CONFIG_SYS_FLASH_BANKS { CONFIG_SYS_FLASH_BASE0_PRELIM , CONFIG_SYS_FLASH_BASE1_PRELIM }
c609719b WD	122
	123	/* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the
	124	* reset vector is actually located at FFB00100, but the 8245
	125	* takes care of us.
	126	*/
6d0f6bcf	127	#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
c609719b	128
6d0f6bcf	129	#define CONFIG_SYS_EUMB_ADDR 0xFC000000
c609719b	130
6d0f6bcf	131	#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
c609719b	132
6d0f6bcf JCPV	133	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
6d0f6bcf JCPV	134	#define CONFIG_SYS_MALLOC_LEN (2048 << 10) /* Reserve 2MB for malloc() */
c609719b	135
6d0f6bcf JCPV	136	#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */
6d0f6bcf JCPV	137	#define CONFIG_SYS_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */
c609719b WD	138
	139	/* Maximum amount of RAM.
	140	*/
6d0f6bcf	141	#define CONFIG_SYS_MAX_RAM_SIZE 0x04000000 /* 0 .. 64 MB of (S)DRAM */
c609719b WD	142
c609719b WD	143
6d0f6bcf JCPV	144	#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
6d0f6bcf JCPV	145	#undef CONFIG_SYS_RAMBOOT
c609719b	146	#else
6d0f6bcf	147	#define CONFIG_SYS_RAMBOOT
c609719b WD	148	#endif
	149
	150
	151	/*-----------------------------------------------------------------------
	152	* Definitions for initial stack pointer and data area
	153	*/
6d0f6bcf JCPV	154	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MONITOR_LEN
	155	#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
	156	#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	157	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
	158	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
c609719b WD	159
	160	/*
	161	* Low Level Configuration Settings
	162	* (address mappings, register initial values, etc.)
	163	* You should know what you are doing if you make changes here.
	164	* For the detail description refer to the MPC8240 user's manual.
	165	*/
	166
	167	#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
6d0f6bcf	168	#define CONFIG_SYS_HZ 1000
c609719b	169
6d0f6bcf JCPV	170	#define CONFIG_SYS_ETH_DEV_FN 0x7800
6d0f6bcf JCPV	171	#define CONFIG_SYS_ETH_IOBASE 0x00104000
c609719b WD	172
	173	/* Bit-field values for MCCR1.
	174	*/
6d0f6bcf JCPV	175	#define CONFIG_SYS_ROMNAL 0xf
	176	#define CONFIG_SYS_ROMFAL 0x1f
	177	#define CONFIG_SYS_DBUS_SIZE 0x3
c609719b WD	178
	179	/* Bit-field values for MCCR2.
	180	*/
6d0f6bcf JCPV	181	#define CONFIG_SYS_TSWAIT 0x5 /* Transaction Start Wait States timer */
6d0f6bcf JCPV	182	#define CONFIG_SYS_REFINT 0x400 /* Refresh interval FIXME: was 0t430 */
c609719b WD	183
	184	/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
	185	*/
6d0f6bcf	186	#define CONFIG_SYS_BSTOPRE 0 /* FIXME: was 192 */
c609719b WD	187
	188	/* Bit-field values for MCCR3.
	189	*/
6d0f6bcf	190	#define CONFIG_SYS_REFREC 2 /* Refresh to activate interval */
c609719b WD	191
	192	/* Bit-field values for MCCR4.
	193	*/
6d0f6bcf JCPV	194	#define CONFIG_SYS_PRETOACT 2 /* Precharge to activate interval FIXME: was 2 */
	195	#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval FIXME: was 5 */
	196	#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */
	197	#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
	198	#define CONFIG_SYS_SDMODE_BURSTLEN 3 /* SDMODE Burst length */
	199	#define CONFIG_SYS_ACTORW 0xa /* FIXME was 2 */
	200	#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
c609719b	201
6d0f6bcf	202	#define CONFIG_SYS_PGMAX 0x0 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/
c609719b	203
6d0f6bcf	204	#define CONFIG_SYS_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */
c609719b WD	205
	206	/* Memory bank settings.
	207	* Only bits 20-29 are actually used from these vales to set the
	208	* start/end addresses. The upper two bits will always be 0, and the lower
	209	* 20 bits will be 0x00000 for a start address, or 0xfffff for an end
	210	* address. Refer to the MPC8240 book.
	211	*/
	212
6d0f6bcf JCPV	213	#define CONFIG_SYS_BANK0_START 0x00000000
	214	#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
	215	#define CONFIG_SYS_BANK0_ENABLE 1
	216	#define CONFIG_SYS_BANK1_START 0x3ff00000
	217	#define CONFIG_SYS_BANK1_END 0x3fffffff
	218	#define CONFIG_SYS_BANK1_ENABLE 0
	219	#define CONFIG_SYS_BANK2_START 0x3ff00000
	220	#define CONFIG_SYS_BANK2_END 0x3fffffff
	221	#define CONFIG_SYS_BANK2_ENABLE 0
	222	#define CONFIG_SYS_BANK3_START 0x3ff00000
	223	#define CONFIG_SYS_BANK3_END 0x3fffffff
	224	#define CONFIG_SYS_BANK3_ENABLE 0
	225	#define CONFIG_SYS_BANK4_START 0x3ff00000
	226	#define CONFIG_SYS_BANK4_END 0x3fffffff
	227	#define CONFIG_SYS_BANK4_ENABLE 0
	228	#define CONFIG_SYS_BANK5_START 0x3ff00000
	229	#define CONFIG_SYS_BANK5_END 0x3fffffff
	230	#define CONFIG_SYS_BANK5_ENABLE 0
	231	#define CONFIG_SYS_BANK6_START 0x3ff00000
	232	#define CONFIG_SYS_BANK6_END 0x3fffffff
	233	#define CONFIG_SYS_BANK6_ENABLE 0
	234	#define CONFIG_SYS_BANK7_START 0x3ff00000
	235	#define CONFIG_SYS_BANK7_END 0x3fffffff
	236	#define CONFIG_SYS_BANK7_ENABLE 0
	237
	238	#define CONFIG_SYS_ODCR 0xff
c609719b WD	239
	240	#define CONFIG_PCI 1 /* Include PCI support */
	241	#undef CONFIG_PCI_PNP
	242
	243	/* PCI Memory space(s) */
	244	#define PCI_MEM_SPACE1_START 0x80000000
	245	#define PCI_MEM_SPACE2_START 0xfd000000
	246
	247	/* ROM Spaces */
	248	#include "../board/bmw/bmw.h"
	249
	250	/* BAT configuration */
6d0f6bcf JCPV	251	#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \| BATL_PP_10 \| BATL_MEMCOHERENCE)
6d0f6bcf JCPV	252	#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \| BATU_BL_256M \| BATU_VS \| BATU_VP)
c609719b	253
6d0f6bcf JCPV	254	#define CONFIG_SYS_IBAT1L (0x70000000 \| BATL_PP_10 \| BATL_CACHEINHIBIT)
6d0f6bcf JCPV	255	#define CONFIG_SYS_IBAT1U (0x70000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP)
c609719b	256
6d0f6bcf JCPV	257	#define CONFIG_SYS_IBAT2L (0x80000000 \| BATL_PP_10 \| BATL_CACHEINHIBIT)
6d0f6bcf JCPV	258	#define CONFIG_SYS_IBAT2U (0x80000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP)
c609719b	259
6d0f6bcf JCPV	260	#define CONFIG_SYS_IBAT3L (0xF0000000 \| BATL_PP_10 \| BATL_CACHEINHIBIT)
6d0f6bcf JCPV	261	#define CONFIG_SYS_IBAT3U (0xF0000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP)
c609719b	262
6d0f6bcf JCPV	263	#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
	264	#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
	265	#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
	266	#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
	267	#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
	268	#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
	269	#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
	270	#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
c609719b WD	271
	272	/*
	273	* For booting Linux, the board info and command line data
	274	* have to be in the first 8 MB of memory, since this is
	275	* the maximum mapped by the Linux kernel during initialization.
	276	*/
6d0f6bcf	277	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
c609719b WD	278
	279	/*
	280	* FLASH organization
	281	*/
6d0f6bcf JCPV	282	#define CONFIG_SYS_MAX_FLASH_BANKS 0 /* Max number of flash banks */
6d0f6bcf JCPV	283	#define CONFIG_SYS_MAX_FLASH_SECT 64 /* Max number of sectors per flash */
c609719b	284
6d0f6bcf JCPV	285	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	286	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
c609719b WD	287
	288	/*
	289	* Warining: environment is not EMBEDDED in the U-Boot code.
	290	* It's stored in flash separately.
	291	*/
9314cee6	292	#define CONFIG_ENV_IS_IN_NVRAM 1
c609719b	293	#define CONFIG_ENV_OVERWRITE 1
6d0f6bcf	294	#define CONFIG_SYS_NVRAM_ACCESS_ROUTINE 1
0e8d1586 JCPV	295	#define CONFIG_ENV_ADDR 0x7c004000 /* right at the start of NVRAM */
	296	#define CONFIG_ENV_SIZE 0x1ff0 /* Size of the Environment - 8K */
	297	#define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */
c609719b WD	298
	299	/*
	300	* Cache Configuration
	301	*/
6d0f6bcf	302	#define CONFIG_SYS_CACHELINE_SIZE 32
de8b2a6e	303	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	304	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
c609719b WD	305	#endif
	306
	307	/*
	308	* Internal Definitions
	309	*
	310	* Boot Flags
	311	*/
	312	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	313	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	314
	315
	316	#endif /* __CONFIG_H */