projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 41d91011 PK |
1 | /* |
| 2 | * Copyright 2013 Freescale Semiconductor, Inc. | |
| 3 | * | |
| 1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 41d91011 PK |
5 | */ |
| 6 | ||
| 7 | /* | |
| 8 | * BSC9132 QDS board configuration file | |
| 9 | */ | |
| 10 | ||
| 11 | #ifndef __CONFIG_H | |
| 12 | #define __CONFIG_H | |
| 13 | ||
| 41d91011 PK |
14 | #define CONFIG_MISC_INIT_R |
| 15 | ||
| 16 | #ifdef CONFIG_SDCARD | |
| 17 | #define CONFIG_RAMBOOT_SDCARD | |
| 18 | #define CONFIG_SYS_RAMBOOT | |
| 19 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
| 20 | #define CONFIG_SYS_TEXT_BASE 0x11000000 | |
| e222b1f3 | 21 | #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc |
| 41d91011 | 22 | #endif |
| 41d91011 PK |
23 | #ifdef CONFIG_SPIFLASH |
| 24 | #define CONFIG_RAMBOOT_SPIFLASH | |
| 25 | #define CONFIG_SYS_RAMBOOT | |
| 26 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
| 27 | #define CONFIG_SYS_TEXT_BASE 0x11000000 | |
| e222b1f3 | 28 | #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc |
| 41d91011 | 29 | #endif |
| bea3cbb0 AB |
30 | #ifdef CONFIG_NAND_SECBOOT |
| 31 | #define CONFIG_RAMBOOT_NAND | |
| 32 | #define CONFIG_SYS_RAMBOOT | |
| 33 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
| 34 | #define CONFIG_SYS_TEXT_BASE 0x11000000 | |
| 35 | #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc | |
| 36 | #endif | |
| 41d91011 | 37 | |
| 83e0c2bb | 38 | #ifdef CONFIG_NAND |
| 83e0c2bb | 39 | #define CONFIG_SPL_INIT_MINIMAL |
| fbe76ae4 | 40 | #define CONFIG_SPL_NAND_BOOT |
| 83e0c2bb PK |
41 | #define CONFIG_SPL_FLUSH_IMAGE |
| 42 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
| 43 | ||
| 44 | #define CONFIG_SYS_TEXT_BASE 0x00201000 | |
| 45 | #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 | |
| 46 | #define CONFIG_SPL_MAX_SIZE 8192 | |
| 47 | #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 | |
| 48 | #define CONFIG_SPL_RELOC_STACK 0x00100000 | |
| e222b1f3 | 49 | #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) |
| 83e0c2bb PK |
50 | #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) |
| 51 | #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 | |
| 52 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 | |
| 53 | #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" | |
| 54 | #endif | |
| 55 | ||
| 41d91011 | 56 | #ifndef CONFIG_SYS_TEXT_BASE |
| e222b1f3 | 57 | #define CONFIG_SYS_TEXT_BASE 0x8ff40000 |
| 41d91011 PK |
58 | #endif |
| 59 | ||
| 60 | #ifndef CONFIG_RESET_VECTOR_ADDRESS | |
| 61 | #define CONFIG_RESET_VECTOR_ADDRESS 0x8ffffffc | |
| 62 | #endif | |
| 63 | ||
| 83e0c2bb PK |
64 | #ifdef CONFIG_SPL_BUILD |
| 65 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE | |
| 66 | #else | |
| 67 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ | |
| 41d91011 PK |
68 | #endif |
| 69 | ||
| 41d91011 | 70 | /* High Level Configuration Options */ |
| 41d91011 PK |
71 | #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ |
| 72 | ||
| 41d91011 | 73 | #if defined(CONFIG_PCI) |
| b38eaec5 | 74 | #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ |
| 41d91011 | 75 | #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ |
| 842033e6 | 76 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ |
| 41d91011 PK |
77 | #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ |
| 78 | #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ | |
| 79 | ||
| 41d91011 PK |
80 | /* |
| 81 | * PCI Windows | |
| 82 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
| 83 | */ | |
| 84 | /* controller 1, Slot 1, tgtid 1, Base address a000 */ | |
| 85 | #define CONFIG_SYS_PCIE1_NAME "PCIe Slot" | |
| 86 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 | |
| 87 | #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 | |
| 88 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 | |
| 89 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ | |
| 90 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xC0010000 | |
| 91 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
| 92 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ | |
| 93 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xC0010000 | |
| 94 | ||
| 41d91011 | 95 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
| 41d91011 PK |
96 | #endif |
| 97 | ||
| 41d91011 PK |
98 | #define CONFIG_ENV_OVERWRITE |
| 99 | #define CONFIG_TSEC_ENET /* ethernet */ | |
| 100 | ||
| 101 | #if defined(CONFIG_SYS_CLK_100_DDR_100) | |
| 102 | #define CONFIG_SYS_CLK_FREQ 100000000 | |
| 103 | #define CONFIG_DDR_CLK_FREQ 100000000 | |
| 104 | #elif defined(CONFIG_SYS_CLK_100_DDR_133) | |
| 105 | #define CONFIG_SYS_CLK_FREQ 100000000 | |
| 106 | #define CONFIG_DDR_CLK_FREQ 133000000 | |
| 107 | #endif | |
| 108 | ||
| 109 | #define CONFIG_MP | |
| 110 | ||
| 111 | #define CONFIG_HWCONFIG | |
| 112 | /* | |
| 113 | * These can be toggled for performance analysis, otherwise use default. | |
| 114 | */ | |
| 115 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
| 116 | #define CONFIG_BTB /* enable branch predition */ | |
| 117 | ||
| 118 | #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */ | |
| 119 | #define CONFIG_SYS_MEMTEST_END 0x01ffffff | |
| 120 | ||
| 121 | /* DDR Setup */ | |
| 41d91011 PK |
122 | #define CONFIG_SYS_SPD_BUS_NUM 0 |
| 123 | #define SPD_EEPROM_ADDRESS1 0x54 /* I2C access */ | |
| 124 | #define SPD_EEPROM_ADDRESS2 0x56 /* I2C access */ | |
| 125 | #define CONFIG_FSL_DDR_INTERACTIVE | |
| 126 | ||
| 127 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
| 128 | ||
| 129 | #define CONFIG_SYS_SDRAM_SIZE (1024) | |
| 130 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
| 131 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
| 132 | ||
| 133 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
| 134 | ||
| 135 | /* DDR3 Controller Settings */ | |
| 136 | #define CONFIG_CHIP_SELECTS_PER_CTRL 1 | |
| 137 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F | |
| 138 | #define CONFIG_SYS_DDR_CS0_CONFIG_1333 0x80004302 | |
| 139 | #define CONFIG_SYS_DDR_CS0_CONFIG_800 0x80014302 | |
| 140 | #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 | |
| 141 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef | |
| 142 | #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 | |
| 143 | #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 | |
| 144 | #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 | |
| 145 | #define CONFIG_SYS_DDR1_CS0_BNDS 0x0040007F | |
| 146 | ||
| 147 | #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 | |
| 148 | #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 | |
| 149 | #define CONFIG_SYS_DDR_RCW_1 0x00000000 | |
| 150 | #define CONFIG_SYS_DDR_RCW_2 0x00000000 | |
| 151 | #define CONFIG_SYS_DDR_CONTROL_800 0x470C0000 | |
| 152 | #define CONFIG_SYS_DDR_CONTROL_2_800 0x04401050 | |
| 153 | #define CONFIG_SYS_DDR_TIMING_4_800 0x00220001 | |
| 154 | #define CONFIG_SYS_DDR_TIMING_5_800 0x03402400 | |
| 155 | ||
| 156 | #define CONFIG_SYS_DDR_CONTROL_1333 0x470C0008 | |
| 157 | #define CONFIG_SYS_DDR_CONTROL_2_1333 0x24401010 | |
| 158 | #define CONFIG_SYS_DDR_TIMING_4_1333 0x00000001 | |
| 159 | #define CONFIG_SYS_DDR_TIMING_5_1333 0x03401400 | |
| 160 | ||
| 161 | #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 | |
| 162 | #define CONFIG_SYS_DDR_TIMING_0_800 0x00330004 | |
| 163 | #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6B4846 | |
| 164 | #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA8C8CF | |
| 165 | #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 | |
| 166 | #define CONFIG_SYS_DDR_MODE_1_800 0x40461520 | |
| 167 | #define CONFIG_SYS_DDR_MODE_2_800 0x8000c000 | |
| 168 | #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300000 | |
| 169 | #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8655A608 | |
| 170 | ||
| 171 | #define CONFIG_SYS_DDR_TIMING_3_1333 0x01061000 | |
| 172 | #define CONFIG_SYS_DDR_TIMING_0_1333 0x00440104 | |
| 173 | #define CONFIG_SYS_DDR_TIMING_1_1333 0x98913A45 | |
| 174 | #define CONFIG_SYS_DDR_TIMING_2_1333 0x0FB8B114 | |
| 175 | #define CONFIG_SYS_DDR_CLK_CTRL_1333 0x02800000 | |
| 176 | #define CONFIG_SYS_DDR_MODE_1_1333 0x00061A50 | |
| 177 | #define CONFIG_SYS_DDR_MODE_2_1333 0x00100000 | |
| 178 | #define CONFIG_SYS_DDR_INTERVAL_1333 0x144E0513 | |
| 179 | #define CONFIG_SYS_DDR_WRLVL_CONTROL_1333 0x8655F607 | |
| 180 | ||
| 181 | /*FIXME: the following params are constant w.r.t diff freq | |
| 182 | combinations. this should be removed later | |
| 183 | */ | |
| 184 | #if CONFIG_DDR_CLK_FREQ == 100000000 | |
| 185 | #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800 | |
| 186 | #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800 | |
| 187 | #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800 | |
| 188 | #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800 | |
| 189 | #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800 | |
| 190 | #elif CONFIG_DDR_CLK_FREQ == 133000000 | |
| 191 | #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_1333 | |
| 192 | #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_1333 | |
| 193 | #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_1333 | |
| 194 | #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_1333 | |
| 195 | #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_1333 | |
| 196 | #else | |
| 197 | #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800 | |
| 198 | #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800 | |
| 199 | #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800 | |
| 200 | #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800 | |
| 201 | #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800 | |
| 202 | #endif | |
| 203 | ||
| 41d91011 PK |
204 | /* relocated CCSRBAR */ |
| 205 | #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT | |
| 206 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT | |
| 207 | ||
| 208 | #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR | |
| 209 | ||
| 64501c66 PJ |
210 | /* DSP CCSRBAR */ |
| 211 | #define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT | |
| 212 | #define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT | |
| 213 | ||
| 41d91011 PK |
214 | /* |
| 215 | * IFC Definitions | |
| 216 | */ | |
| 217 | /* NOR Flash on IFC */ | |
| 83e0c2bb | 218 | |
| 41d91011 PK |
219 | #define CONFIG_SYS_FLASH_BASE 0x88000000 |
| 220 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* Max number of sector: 32M */ | |
| 221 | ||
| 222 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE | |
| 223 | ||
| 224 | #define CONFIG_SYS_NOR_CSPR 0x88000101 | |
| 225 | #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) | |
| 226 | #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(5) | |
| 227 | /* NOR Flash Timing Params */ | |
| 228 | ||
| 229 | #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) \ | |
| 230 | | FTIM0_NOR_TEADC(0x03) \ | |
| 231 | | FTIM0_NOR_TAVDS(0x00) \ | |
| 232 | | FTIM0_NOR_TEAHC(0x0f)) | |
| 233 | #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1d) \ | |
| 234 | | FTIM1_NOR_TRAD_NOR(0x09) \ | |
| 235 | | FTIM1_NOR_TSEQRAD_NOR(0x09)) | |
| 236 | #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) \ | |
| 237 | | FTIM2_NOR_TCH(0x4) \ | |
| 238 | | FTIM2_NOR_TWPH(0x7) \ | |
| 239 | | FTIM2_NOR_TWP(0x1e)) | |
| 240 | #define CONFIG_SYS_NOR_FTIM3 0x0 | |
| 241 | ||
| 242 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} | |
| 243 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
| 244 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
| 245 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
| 246 | ||
| 247 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
| 248 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
| 249 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
| 250 | ||
| 251 | /* CFI for NOR Flash */ | |
| 252 | #define CONFIG_FLASH_CFI_DRIVER | |
| 253 | #define CONFIG_SYS_FLASH_CFI | |
| 254 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
| 255 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
| 256 | ||
| 257 | /* NAND Flash on IFC */ | |
| 258 | #define CONFIG_SYS_NAND_BASE 0xff800000 | |
| 259 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE | |
| 260 | ||
| 261 | #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | |
| 262 | | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ | |
| 263 | | CSPR_MSEL_NAND /* MSEL = NAND */ \ | |
| 264 | | CSPR_V) | |
| 265 | #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) | |
| 266 | ||
| 267 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | |
| 268 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | |
| 269 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | |
| 270 | | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \ | |
| 271 | | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ | |
| 272 | | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ | |
| 273 | | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ | |
| 274 | ||
| 275 | /* NAND Flash Timing Params */ | |
| 276 | #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \ | |
| 277 | | FTIM0_NAND_TWP(0x05) \ | |
| 278 | | FTIM0_NAND_TWCHT(0x02) \ | |
| 279 | | FTIM0_NAND_TWH(0x04)) | |
| 280 | #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1c) \ | |
| 281 | | FTIM1_NAND_TWBE(0x1e) \ | |
| 282 | | FTIM1_NAND_TRR(0x07) \ | |
| 283 | | FTIM1_NAND_TRP(0x05)) | |
| 284 | #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \ | |
| 285 | | FTIM2_NAND_TREH(0x04) \ | |
| 286 | | FTIM2_NAND_TWHRE(0x11)) | |
| 287 | #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) | |
| 288 | ||
| 289 | #define CONFIG_SYS_NAND_DDR_LAW 11 | |
| 290 | ||
| 291 | /* NAND */ | |
| 292 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } | |
| 293 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
| 41d91011 PK |
294 | |
| 295 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) | |
| 296 | ||
| 83e0c2bb | 297 | #ifndef CONFIG_SPL_BUILD |
| 41d91011 | 298 | #define CONFIG_FSL_QIXIS |
| 83e0c2bb | 299 | #endif |
| 41d91011 PK |
300 | #ifdef CONFIG_FSL_QIXIS |
| 301 | #define CONFIG_SYS_FPGA_BASE 0xffb00000 | |
| 302 | #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 | |
| 303 | #define QIXIS_BASE CONFIG_SYS_FPGA_BASE | |
| 304 | #define QIXIS_LBMAP_SWITCH 9 | |
| 305 | #define QIXIS_LBMAP_MASK 0x07 | |
| 306 | #define QIXIS_LBMAP_SHIFT 0 | |
| 307 | #define QIXIS_LBMAP_DFLTBANK 0x00 | |
| 308 | #define QIXIS_LBMAP_ALTBANK 0x04 | |
| 309 | #define QIXIS_RST_CTL_RESET 0x83 | |
| 310 | #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 | |
| 311 | #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 | |
| 312 | #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 | |
| 313 | ||
| 314 | #define CONFIG_SYS_FPGA_BASE_PHYS CONFIG_SYS_FPGA_BASE | |
| 315 | ||
| 316 | #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_FPGA_BASE) \ | |
| 317 | | CSPR_PORT_SIZE_8 \ | |
| 318 | | CSPR_MSEL_GPCM \ | |
| 319 | | CSPR_V) | |
| 320 | #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) | |
| 321 | #define CONFIG_SYS_CSOR2 0x0 | |
| 322 | /* CPLD Timing parameters for IFC CS3 */ | |
| 323 | #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ | |
| 324 | FTIM0_GPCM_TEADC(0x0e) | \ | |
| 325 | FTIM0_GPCM_TEAHC(0x0e)) | |
| 326 | #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ | |
| 327 | FTIM1_GPCM_TRAD(0x1f)) | |
| 328 | #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ | |
| de519163 | 329 | FTIM2_GPCM_TCH(0x8) | \ |
| 41d91011 PK |
330 | FTIM2_GPCM_TWP(0x1f)) |
| 331 | #define CONFIG_SYS_CS2_FTIM3 0x0 | |
| 332 | #endif | |
| 333 | ||
| 334 | /* Set up IFC registers for boot location NOR/NAND */ | |
| 3051f3f9 | 335 | #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) |
| 83e0c2bb PK |
336 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR |
| 337 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK | |
| 338 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR | |
| 339 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
| 340 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
| 341 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
| 342 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
| 343 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR | |
| 344 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK | |
| 345 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR | |
| 346 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
| 347 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
| 348 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
| 349 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
| 350 | #else | |
| 41d91011 PK |
351 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR |
| 352 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK | |
| 353 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR | |
| 354 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
| 355 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
| 356 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
| 357 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
| 358 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR | |
| 359 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK | |
| 360 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR | |
| 361 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
| 362 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
| 363 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
| 364 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
| 83e0c2bb | 365 | #endif |
| 41d91011 | 366 | |
| 41d91011 PK |
367 | #define CONFIG_BOARD_EARLY_INIT_R |
| 368 | ||
| 369 | #define CONFIG_SYS_INIT_RAM_LOCK | |
| 370 | #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ | |
| b39d1213 | 371 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ |
| 41d91011 | 372 | |
| b39d1213 | 373 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ |
| 41d91011 PK |
374 | - GENERATED_GBL_DATA_SIZE) |
| 375 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
| 376 | ||
| 9307cbab | 377 | #define CONFIG_SYS_MONITOR_LEN (768 * 1024) |
| 41d91011 PK |
378 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ |
| 379 | ||
| 380 | /* Serial Port */ | |
| 381 | #define CONFIG_CONS_INDEX 1 | |
| 382 | #undef CONFIG_SERIAL_SOFTWARE_FIFO | |
| 41d91011 PK |
383 | #define CONFIG_SYS_NS16550_SERIAL |
| 384 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
| 385 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
| 83e0c2bb PK |
386 | #ifdef CONFIG_SPL_BUILD |
| 387 | #define CONFIG_NS16550_MIN_FUNCTIONS | |
| 388 | #endif | |
| 41d91011 | 389 | |
| 41d91011 PK |
390 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
| 391 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
| 392 | ||
| 393 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) | |
| 394 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) | |
| 395 | #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR + 0x4700) | |
| 396 | #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR + 0x4800) | |
| 397 | ||
| 00f792e0 HS |
398 | #define CONFIG_SYS_I2C |
| 399 | #define CONFIG_SYS_I2C_FSL | |
| 400 | #define CONFIG_SYS_FSL_I2C_SPEED 400800 /* I2C speed and slave address*/ | |
| 401 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
| 402 | #define CONFIG_SYS_FSL_I2C2_SPEED 400800 /* I2C speed and slave address*/ | |
| 403 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
| 404 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
| 405 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
| 41d91011 PK |
406 | |
| 407 | /* I2C EEPROM */ | |
| 408 | #define CONFIG_ID_EEPROM | |
| 409 | #ifdef CONFIG_ID_EEPROM | |
| 410 | #define CONFIG_SYS_I2C_EEPROM_NXID | |
| 411 | #endif | |
| 412 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | |
| 413 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
| 414 | #define CONFIG_SYS_EEPROM_BUS_NUM 0 | |
| 415 | ||
| 416 | /* enable read and write access to EEPROM */ | |
| 41d91011 PK |
417 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
| 418 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
| 419 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 | |
| 420 | ||
| 421 | /* I2C FPGA */ | |
| 422 | #define CONFIG_I2C_FPGA | |
| 423 | #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 | |
| 424 | ||
| 425 | #define CONFIG_RTC_DS3231 | |
| 426 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
| 427 | ||
| 428 | /* | |
| 429 | * SPI interface will not be available in case of NAND boot SPI CS0 will be | |
| 430 | * used for SLIC | |
| 431 | */ | |
| 432 | /* eSPI - Enhanced SPI */ | |
| 41d91011 | 433 | #ifdef CONFIG_FSL_ESPI |
| 41d91011 PK |
434 | #define CONFIG_SF_DEFAULT_SPEED 10000000 |
| 435 | #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 | |
| 436 | #endif | |
| 437 | ||
| 438 | #if defined(CONFIG_TSEC_ENET) | |
| 439 | ||
| 440 | #define CONFIG_MII /* MII PHY management */ | |
| 441 | #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ | |
| 442 | #define CONFIG_TSEC1 1 | |
| 443 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
| 444 | #define CONFIG_TSEC2 1 | |
| 445 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
| 446 | ||
| 447 | #define TSEC1_PHY_ADDR 0 | |
| 448 | #define TSEC2_PHY_ADDR 1 | |
| 449 | ||
| 450 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 451 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 452 | ||
| 453 | #define TSEC1_PHYIDX 0 | |
| 454 | #define TSEC2_PHYIDX 0 | |
| 455 | ||
| 456 | #define CONFIG_ETHPRIME "eTSEC1" | |
| 457 | ||
| 41d91011 PK |
458 | /* TBI PHY configuration for SGMII mode */ |
| 459 | #define CONFIG_TSEC_TBICR_SETTINGS ( \ | |
| 460 | TBICR_PHY_RESET \ | |
| 461 | | TBICR_ANEG_ENABLE \ | |
| 462 | | TBICR_FULL_DUPLEX \ | |
| 463 | | TBICR_SPEED1_SET \ | |
| 464 | ) | |
| 465 | ||
| 466 | #endif /* CONFIG_TSEC_ENET */ | |
| 467 | ||
| 41d91011 | 468 | #ifdef CONFIG_MMC |
| 41d91011 | 469 | #define CONFIG_FSL_ESDHC |
| 41d91011 PK |
470 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR |
| 471 | #endif | |
| 472 | ||
| 8850c5d5 | 473 | #ifdef CONFIG_USB_EHCI_HCD |
| 41d91011 PK |
474 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET |
| 475 | #define CONFIG_USB_EHCI_FSL | |
| 41d91011 PK |
476 | #define CONFIG_HAS_FSL_DR_USB |
| 477 | #endif | |
| 478 | ||
| 479 | /* | |
| 480 | * Environment | |
| 481 | */ | |
| 41d91011 | 482 | #if defined(CONFIG_RAMBOOT_SDCARD) |
| e222b1f3 | 483 | #define CONFIG_FSL_FIXED_MMC_LOCATION |
| 41d91011 PK |
484 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
| 485 | #define CONFIG_ENV_SIZE 0x2000 | |
| 486 | #elif defined(CONFIG_RAMBOOT_SPIFLASH) | |
| 41d91011 PK |
487 | #define CONFIG_ENV_SPI_BUS 0 |
| 488 | #define CONFIG_ENV_SPI_CS 0 | |
| 489 | #define CONFIG_ENV_SPI_MAX_HZ 10000000 | |
| 490 | #define CONFIG_ENV_SPI_MODE 0 | |
| 491 | #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ | |
| 492 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
| 493 | #define CONFIG_ENV_SIZE 0x2000 | |
| bea3cbb0 | 494 | #elif defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) |
| 83e0c2bb | 495 | #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE |
| e222b1f3 | 496 | #define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) |
| 83e0c2bb PK |
497 | #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) |
| 498 | #elif defined(CONFIG_SYS_RAMBOOT) | |
| 41d91011 PK |
499 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
| 500 | #define CONFIG_ENV_SIZE 0x2000 | |
| 41d91011 | 501 | #else |
| 41d91011 | 502 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) |
| 41d91011 | 503 | #define CONFIG_ENV_SIZE 0x2000 |
| e222b1f3 | 504 | #define CONFIG_ENV_SECT_SIZE 0x20000 |
| 41d91011 PK |
505 | #endif |
| 506 | ||
| 507 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ | |
| 508 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ | |
| 509 | ||
| 41d91011 PK |
510 | /* |
| 511 | * Miscellaneous configurable options | |
| 512 | */ | |
| 513 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
| 514 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ | |
| 515 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
| 516 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
| 41d91011 | 517 | |
| 41d91011 PK |
518 | /* |
| 519 | * For booting Linux, the board info and command line data | |
| 520 | * have to be in the first 64 MB of memory, since this is | |
| 521 | * the maximum mapped by the Linux kernel during initialization. | |
| 522 | */ | |
| 523 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ | |
| 524 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
| 525 | ||
| 526 | #if defined(CONFIG_CMD_KGDB) | |
| 527 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
| 41d91011 PK |
528 | #endif |
| 529 | ||
| 42a9e2fe AK |
530 | /* |
| 531 | * Dynamic MTD Partition support with mtdparts | |
| 532 | */ | |
| e856bdcf | 533 | #ifdef CONFIG_MTD_NOR_FLASH |
| 42a9e2fe AK |
534 | #define CONFIG_MTD_DEVICE |
| 535 | #define CONFIG_MTD_PARTITIONS | |
| 42a9e2fe | 536 | #define CONFIG_FLASH_CFI_MTD |
| 42a9e2fe | 537 | #endif |
| 41d91011 PK |
538 | /* |
| 539 | * Environment Configuration | |
| 540 | */ | |
| 541 | ||
| 542 | #if defined(CONFIG_TSEC_ENET) | |
| 543 | #define CONFIG_HAS_ETH0 | |
| 544 | #define CONFIG_HAS_ETH1 | |
| 545 | #endif | |
| 546 | ||
| 547 | #define CONFIG_HOSTNAME BSC9132qds | |
| 548 | #define CONFIG_ROOTPATH "/opt/nfsroot" | |
| 549 | #define CONFIG_BOOTFILE "uImage" | |
| 550 | #define CONFIG_UBOOTPATH "u-boot.bin" | |
| 551 | ||
| 41d91011 PK |
552 | #ifdef CONFIG_SDCARD |
| 553 | #define CONFIG_DEF_HWCONFIG "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" | |
| 554 | #else | |
| 555 | #define CONFIG_DEF_HWCONFIG "hwconfig=sim;usb1:dr_mode=host,phy_type=ulpi\0" | |
| 556 | #endif | |
| 557 | ||
| 558 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 559 | "netdev=eth0\0" \ | |
| 560 | "uboot=" CONFIG_UBOOTPATH "\0" \ | |
| 561 | "loadaddr=1000000\0" \ | |
| 562 | "bootfile=uImage\0" \ | |
| 563 | "consoledev=ttyS0\0" \ | |
| 564 | "ramdiskaddr=2000000\0" \ | |
| 565 | "ramdiskfile=rootfs.ext2.gz.uboot\0" \ | |
| b24a4f62 | 566 | "fdtaddr=1e00000\0" \ |
| 41d91011 PK |
567 | "fdtfile=bsc9132qds.dtb\0" \ |
| 568 | "bdev=sda1\0" \ | |
| 569 | CONFIG_DEF_HWCONFIG\ | |
| 570 | "othbootargs=mem=880M ramdisk_size=600000 " \ | |
| 571 | "default_hugepagesz=256m hugepagesz=256m hugepages=1 " \ | |
| 572 | "isolcpus=0\0" \ | |
| 573 | "usbext2boot=setenv bootargs root=/dev/ram rw " \ | |
| 574 | "console=$consoledev,$baudrate $othbootargs; " \ | |
| 575 | "usb start;" \ | |
| 576 | "ext2load usb 0:4 $loadaddr $bootfile;" \ | |
| 577 | "ext2load usb 0:4 $fdtaddr $fdtfile;" \ | |
| 578 | "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ | |
| 579 | "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ | |
| 580 | "debug_halt_off=mw ff7e0e30 0xf0000000;" | |
| 581 | ||
| 582 | #define CONFIG_NFSBOOTCOMMAND \ | |
| 583 | "setenv bootargs root=/dev/nfs rw " \ | |
| 584 | "nfsroot=$serverip:$rootpath " \ | |
| 585 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
| 586 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 587 | "tftp $loadaddr $bootfile;" \ | |
| 588 | "tftp $fdtaddr $fdtfile;" \ | |
| 589 | "bootm $loadaddr - $fdtaddr" | |
| 590 | ||
| 591 | #define CONFIG_HDBOOT \ | |
| 592 | "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ | |
| 593 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 594 | "usb start;" \ | |
| 595 | "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ | |
| 596 | "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ | |
| 597 | "bootm $loadaddr - $fdtaddr" | |
| 598 | ||
| 599 | #define CONFIG_RAMBOOTCOMMAND \ | |
| 600 | "setenv bootargs root=/dev/ram rw " \ | |
| 601 | "console=$consoledev,$baudrate $othbootargs; " \ | |
| 602 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
| 603 | "tftp $loadaddr $bootfile;" \ | |
| 604 | "tftp $fdtaddr $fdtfile;" \ | |
| 605 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
| 606 | ||
| 607 | #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND | |
| 608 | ||
| f978f7c2 AB |
609 | #include <asm/fsl_secure_boot.h> |
| 610 | ||
| 41d91011 | 611 | #endif /* __CONFIG_H */ |