[people/ms/u-boot.git] / include / configs / CPCI405.h

/*
 * (C) Copyright 2001
 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
#define CONFIG_CPCI405		1	/* ...on a CPCI405 board	*/

#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/

#define CONFIG_SYS_CLK_FREQ	33000000 /* external frequency to pll	*/

#define CONFIG_BAUDRATE		9600
#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/

#undef	CONFIG_BOOTARGS
#undef	CONFIG_BOOTCOMMAND

#define CONFIG_PREBOOT                  /* enable preboot variable      */

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#define CONFIG_MII		1	/* MII PHY management		*/
#define CONFIG_PHY_ADDR		0	/* PHY address			*/
#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
#define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */

#define CONFIG_NET_MULTI	1
#undef  CONFIG_HAS_ETH1

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PCI
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_IDE
#define CONFIG_CMD_FAT
#define CONFIG_CMD_ELF
#define CONFIG_CMD_MII
#define CONFIG_CMD_EEPROM


#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION

#define CONFIG_SUPPORT_VFAT

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory		*/
#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/

#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
#ifdef	CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2	"> "
#endif

#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/

#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/

#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
#define CFG_BASE_BAUD	    691200

/* The following table includes the supported baudrates */
#define CFG_BAUDRATE_TABLE	\
	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
	 57600, 115200, 230400, 460800, 921600 }

#define CFG_LOAD_ADDR	0x100000	/* default load address */
#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */

#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */

#define CONFIG_LOOPW            1       /* enable loopw command         */

#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
#define PCI_HOST_FORCE  1               /* configure as pci host        */
#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */

#define CONFIG_PCI			/* include pci support	        */
#define CONFIG_PCI_HOST	PCI_HOST_AUTO   /* select pci host function     */
#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
					/* resource configuration       */

#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */

#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/

#define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/

#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
#define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A    */
#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
#define CFG_PCI_PTM1LA  (bd->bi_memstart) /* point to sdram               */
#define CFG_PCI_PTM1MS  (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */

/*-----------------------------------------------------------------------
 * IDE/ATA stuff
 *-----------------------------------------------------------------------
 */
#undef	CONFIG_IDE_8xx_DIRECT		    /* no pcmcia interface required */
#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
#undef	CONFIG_IDE_RESET		/* no reset for ide supported	*/

#define CFG_IDE_MAXBUS		1		/* max. 1 IDE busses	*/
#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */

#define CFG_ATA_BASE_ADDR	0xF0100000
#define CFG_ATA_IDE0_OFFSET	0x0000

#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
#define CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
#define CFG_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define CFG_SDRAM_BASE		0x00000000
#define CFG_FLASH_BASE		0xFFFD0000
#define CFG_MONITOR_BASE	CFG_FLASH_BASE
#define CFG_MONITOR_LEN		(192 * 1024)	/* Reserve 196 kB for Monitor	*/
#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
/*
 * The following defines are added for buggy IOP480 byte interface.
 * All other boards should use the standard values (CPCI405 etc.)
 */
#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/

#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */

#define CFG_NVRAM_BASE_ADDR	0xf0200000		/* NVRAM base address	*/
#define CFG_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
#define CFG_VXWORKS_MAC_PTR     (CFG_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/

#if 1 /* Use NVRAM for environment variables */
/*-----------------------------------------------------------------------
 * NVRAM organization
 */
#define CONFIG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
#define CONFIG_ENV_SIZE		0x1000		/* Size of Environment vars	*/
#define CONFIG_ENV_ADDR		\
	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CONFIG_ENV_SIZE)	/* Env	*/

#else /* Use EEPROM for environment variables */

#define CONFIG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
#define CONFIG_ENV_OFFSET          0x000   /* environment starts at the beginning of the EEPROM */
#define CONFIG_ENV_SIZE            0x400   /* 1024 bytes may be used for env vars */
				   /* total size of a CAT24WC08 is 1024 bytes */
#endif

/*-----------------------------------------------------------------------
 * I2C EEPROM (CAT24WC08) for environment
 */
#define CONFIG_HARD_I2C			/* I2c with hardware support */
#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
#define CFG_I2C_SLAVE		0x7F

#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
/* mask of address bits that overflow into the "EEPROM chip address"	*/
#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
					/* 16 byte page write mode using*/
					/* last 4 bits of the address	*/
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0xFF800000	/* FLASH bank #0	*/
#define FLASH_BASE1_PRELIM	0xFFC00000	/* FLASH bank #1	*/

/*-----------------------------------------------------------------------
 * External Bus Controller (EBC) Setup
 */

/* Memory Bank 0 (Flash Bank 0) initialization					*/
#define CFG_EBC_PB0AP		0x92015480
#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */

/* Memory Bank 1 (Flash Bank 1) initialization					*/
#define CFG_EBC_PB1AP		0x92015480
#define CFG_EBC_PB1CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */

/* Memory Bank 2 (CAN0, 1, 2, Codeswitch) initialization			*/
#define CFG_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/

/* Memory Bank 3 (CompactFlash IDE) initialization				*/
#define CFG_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CFG_EBC_PB3CR		0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */

/* Memory Bank 4 (NVRAM) initialization						*/
#define CFG_EBC_PB4AP		0x01005280  /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1	*/
#define CFG_EBC_PB4CR		0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit	*/

/* Memory Bank 5 (Quart) initialization						*/
#define CFG_EBC_PB5AP		0x04005B80  /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
#define CFG_EBC_PB5CR		0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit	*/

/*-----------------------------------------------------------------------
 * FPGA stuff
 */

/* FPGA program pin configuration */
#define CFG_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
#define CFG_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
#define CFG_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
#define CFG_FPGA_INIT		0x00400000  /* FPGA init pin (ppc input)     */
#define CFG_FPGA_DONE		0x00800000  /* FPGA done pin (ppc input)     */

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in data cache)
 */
#if 1 /* test-only */
#define CFG_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */

#define CFG_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
#else
#define CFG_INIT_RAM_ADDR	0x00df0000 /* inside of SDRAM			*/
#endif
#define CFG_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET


/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

#endif	/* __CONFIG_H */
Commit	Line	Data
c609719b WD	1	/*
	2	* (C) Copyright 2001
	3	* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* board/config.h - configuration options, board specific
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	/*
	32	* High Level Configuration Options
	33	* (easy to change)
	34	*/
	35
	36	#define CONFIG_405GP 1 /* This is a PPC405 CPU */
c837dcb1	37	#define CONFIG_4xx 1 /* ...member of PPC4xx family */
c609719b WD	38	#define CONFIG_CPCI405 1 /* ...on a CPCI405 board */
c609719b WD	39
c837dcb1	40	#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
c609719b	41
c837dcb1	42	#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
c609719b WD	43
	44	#define CONFIG_BAUDRATE 9600
	45	#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
	46
c609719b	47	#undef CONFIG_BOOTARGS
a20b27a3 SR	48	#undef CONFIG_BOOTCOMMAND
	49
	50	#define CONFIG_PREBOOT /* enable preboot variable */
c609719b WD	51
	52	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	53	#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
	54
	55	#define CONFIG_MII 1 /* MII PHY management */
c837dcb1	56	#define CONFIG_PHY_ADDR 0 /* PHY address */
a20b27a3	57	#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
6f35c531 MF	58	#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
	59
	60	#define CONFIG_NET_MULTI 1
	61	#undef CONFIG_HAS_ETH1
c609719b	62
5d2ebe1b JL	63	/*
	64	* BOOTP options
	65	*/
	66	#define CONFIG_BOOTP_SUBNETMASK
	67	#define CONFIG_BOOTP_GATEWAY
	68	#define CONFIG_BOOTP_HOSTNAME
	69	#define CONFIG_BOOTP_BOOTPATH
	70	#define CONFIG_BOOTP_DNS
	71	#define CONFIG_BOOTP_DNS2
	72	#define CONFIG_BOOTP_SEND_HOSTNAME
	73
9919f13c	74
49cf7e8e JL	75	/*
	76	* Command line configuration.
	77	*/
	78	#include <config_cmd_default.h>
	79
	80	#define CONFIG_CMD_DHCP
	81	#define CONFIG_CMD_PCI
	82	#define CONFIG_CMD_IRQ
	83	#define CONFIG_CMD_IDE
	84	#define CONFIG_CMD_FAT
	85	#define CONFIG_CMD_ELF
	86	#define CONFIG_CMD_MII
	87	#define CONFIG_CMD_EEPROM
	88
c609719b WD	89
	90	#define CONFIG_MAC_PARTITION
	91	#define CONFIG_DOS_PARTITION
	92
a20b27a3 SR	93	#define CONFIG_SUPPORT_VFAT
a20b27a3 SR	94
c837dcb1	95	#undef CONFIG_WATCHDOG /* watchdog disabled */
c609719b	96
c837dcb1	97	#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
c609719b WD	98
	99	/*
	100	* Miscellaneous configurable options
	101	*/
	102	#define CFG_LONGHELP /* undef to save memory */
	103	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	104
	105	#undef CFG_HUSH_PARSER /* use "hush" command parser */
	106	#ifdef CFG_HUSH_PARSER
c837dcb1	107	#define CFG_PROMPT_HUSH_PS2 "> "
c609719b WD	108	#endif
c609719b WD	109
49cf7e8e	110	#if defined(CONFIG_CMD_KGDB)
c837dcb1	111	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
c609719b	112	#else
c837dcb1	113	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
c609719b WD	114	#endif
	115	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	116	#define CFG_MAXARGS 16 /* max number of command args */
	117	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	118
c837dcb1	119	#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
c609719b	120
c837dcb1	121	#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
c609719b WD	122
	123	#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
	124	#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
	125
c837dcb1 WD	126	#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
	127	#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
	128	#define CFG_BASE_BAUD 691200
c609719b WD	129
c609719b WD	130	/* The following table includes the supported baudrates */
c837dcb1	131	#define CFG_BAUDRATE_TABLE \
8bde7f77 WD	132	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
8bde7f77 WD	133	57600, 115200, 230400, 460800, 921600 }
c609719b WD	134
	135	#define CFG_LOAD_ADDR 0x100000 /* default load address */
	136	#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
	137
c837dcb1	138	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
c609719b	139
a20b27a3 SR	140	#define CONFIG_LOOPW 1 /* enable loopw command */
a20b27a3 SR	141
c609719b WD	142	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
	143
	144	/*-----------------------------------------------------------------------
	145	* PCI stuff
	146	*-----------------------------------------------------------------------
	147	*/
a20b27a3 SR	148	#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
	149	#define PCI_HOST_FORCE 1 /* configure as pci host */
	150	#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
	151
	152	#define CONFIG_PCI /* include pci support */
	153	#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
	154	#define CONFIG_PCI_PNP /* do pci plug-and-play */
	155	/* resource configuration */
	156
	157	#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
	158
	159	#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
	160
	161	#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
	162
	163	#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
	164	#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
	165	#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */
	166	#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
2076d0a1 SR	167	#define CFG_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
2076d0a1 SR	168	#define CFG_PCI_PTM1MS (~(bd->bi_memsize - 1) \| 1) /* memsize, enable hard-wired to 1 */
a20b27a3 SR	169	#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
	170	#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
	171	#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
	172	#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
c609719b WD	173
	174	/*-----------------------------------------------------------------------
	175	* IDE/ATA stuff
	176	*-----------------------------------------------------------------------
	177	*/
c837dcb1 WD	178	#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
	179	#undef CONFIG_IDE_LED /* no led for ide supported */
	180	#undef CONFIG_IDE_RESET /* no reset for ide supported */
c609719b	181
c837dcb1 WD	182	#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
c837dcb1 WD	183	#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS1) / max. 1 drives per IDE bus */
c609719b	184
c837dcb1 WD	185	#define CFG_ATA_BASE_ADDR 0xF0100000
c837dcb1 WD	186	#define CFG_ATA_IDE0_OFFSET 0x0000
c609719b WD	187
c609719b WD	188	#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
c837dcb1	189	#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
c609719b WD	190	#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
	191
	192	/*-----------------------------------------------------------------------
	193	* Start addresses for the final memory configuration
	194	* (Set up by the startup code)
	195	* Please note that CFG_SDRAM_BASE _must_ start at 0
	196	*/
	197	#define CFG_SDRAM_BASE 0x00000000
	198	#define CFG_FLASH_BASE 0xFFFD0000
	199	#define CFG_MONITOR_BASE CFG_FLASH_BASE
	200	#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */
	201	#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
	202
	203	/*
	204	* For booting Linux, the board info and command line data
	205	* have to be in the first 8 MB of memory, since this is
	206	* the maximum mapped by the Linux kernel during initialization.
	207	*/
	208	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	209	/*-----------------------------------------------------------------------
	210	* FLASH organization
	211	*/
	212	#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
	213	#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
	214
	215	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	216	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
	217
c837dcb1 WD	218	#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
	219	#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
	220	#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
c609719b WD	221	/*
	222	* The following defines are added for buggy IOP480 byte interface.
	223	* All other boards should use the standard values (CPCI405 etc.)
	224	*/
c837dcb1 WD	225	#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
	226	#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
	227	#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
c609719b	228
c837dcb1	229	#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
c609719b	230
a20b27a3 SR	231	#define CFG_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */
	232	#define CFG_NVRAM_SIZE (321024) / NVRAM size */
	233	#define CFG_VXWORKS_MAC_PTR (CFG_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
	234
c609719b WD	235	#if 1 /* Use NVRAM for environment variables */
	236	/*-----------------------------------------------------------------------
	237	* NVRAM organization
	238	*/
9314cee6	239	#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
0e8d1586 JCPV	240	#define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */
	241	#define CONFIG_ENV_ADDR \
	242	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */
c609719b WD	243
	244	#else /* Use EEPROM for environment variables */
	245
bb1f8b4f	246	#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
0e8d1586 JCPV	247	#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
0e8d1586 JCPV	248	#define CONFIG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars */
8bde7f77	249	/* total size of a CAT24WC08 is 1024 bytes */
c609719b WD	250	#endif
	251
	252	/*-----------------------------------------------------------------------
	253	* I2C EEPROM (CAT24WC08) for environment
	254	*/
	255	#define CONFIG_HARD_I2C /* I2c with hardware support */
	256	#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
	257	#define CFG_I2C_SLAVE 0x7F
	258
	259	#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
c837dcb1 WD	260	#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
c837dcb1 WD	261	/* mask of address bits that overflow into the "EEPROM chip address" */
c609719b WD	262	#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
	263	#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
	264	/* 16 byte page write mode using*/
c837dcb1	265	/* last 4 bits of the address */
c609719b WD	266	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
	267	#define CFG_EEPROM_PAGE_WRITE_ENABLE
	268
c609719b WD	269	/*
	270	* Init Memory Controller:
	271	*
	272	* BR0/1 and OR0/1 (FLASH)
	273	*/
	274
	275	#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
	276	#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */
	277
	278	/*-----------------------------------------------------------------------
	279	* External Bus Controller (EBC) Setup
	280	*/
	281
c837dcb1 WD	282	/* Memory Bank 0 (Flash Bank 0) initialization */
	283	#define CFG_EBC_PB0AP 0x92015480
	284	#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
c609719b	285
c837dcb1 WD	286	/* Memory Bank 1 (Flash Bank 1) initialization */
	287	#define CFG_EBC_PB1AP 0x92015480
	288	#define CFG_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
c609719b	289
c837dcb1 WD	290	/* Memory Bank 2 (CAN0, 1, 2, Codeswitch) initialization */
	291	#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
	292	#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
c609719b	293
c837dcb1 WD	294	/* Memory Bank 3 (CompactFlash IDE) initialization */
	295	#define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
	296	#define CFG_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
c609719b	297
c837dcb1 WD	298	/* Memory Bank 4 (NVRAM) initialization */
	299	#define CFG_EBC_PB4AP 0x01005280 /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1 */
	300	#define CFG_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
c609719b	301
c837dcb1 WD	302	/* Memory Bank 5 (Quart) initialization */
	303	#define CFG_EBC_PB5AP 0x04005B80 /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
	304	#define CFG_EBC_PB5CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
c609719b WD	305
	306	/*-----------------------------------------------------------------------
	307	* FPGA stuff
	308	*/
	309
	310	/* FPGA program pin configuration */
c837dcb1 WD	311	#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
	312	#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
	313	#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
	314	#define CFG_FPGA_INIT 0x00400000 /* FPGA init pin (ppc input) */
	315	#define CFG_FPGA_DONE 0x00800000 /* FPGA done pin (ppc input) */
c609719b WD	316
	317	/*-----------------------------------------------------------------------
	318	* Definitions for initial stack pointer and data area (in data cache)
	319	*/
	320	#if 1 /* test-only */
c837dcb1	321	#define CFG_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
c609719b	322
c837dcb1	323	#define CFG_INIT_RAM_ADDR 0x40000000 /* use data cache */
c609719b	324	#else
c837dcb1	325	#define CFG_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */
c609719b	326	#endif
c837dcb1	327	#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
c609719b WD	328	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
c609719b WD	329	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
c837dcb1	330	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
c609719b WD	331
	332
	333	/*
	334	* Internal Definitions
	335	*
	336	* Boot Flags
	337	*/
	338	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	339	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	340
	341	#endif /* __CONFIG_H */