[people/ms/u-boot.git] / include / configs / CPCI4052.h

/*
 * (C) Copyright 2001-2004
 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
#define CONFIG_CPCI405		1	/* ...on a CPCI405 board	*/
#define CONFIG_CPCI405_VER2	1	/* ...version 2			*/

#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/

#define CONFIG_SYS_CLK_FREQ	33330000 /* external frequency to pll	*/

#define CONFIG_BAUDRATE		9600
#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/

#undef	CONFIG_BOOTARGS
#undef	CONFIG_BOOTCOMMAND

#define CONFIG_PREBOOT                  /* enable preboot variable      */

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#define CONFIG_MII		1	/* MII PHY management		*/
#define CONFIG_PHY_ADDR		0	/* PHY address			*/
#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */

#define CONFIG_RTC_M48T35A	1		/* ST Electronics M48 timekeeper */

#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
				 CONFIG_BOOTP_DNS | \
				 CONFIG_BOOTP_DNS2 | \
				 CONFIG_BOOTP_SEND_HOSTNAME )

#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
				CFG_CMD_DHCP	| \
				CFG_CMD_PCI	| \
				CFG_CMD_IRQ	| \
				CFG_CMD_IDE	| \
				CFG_CMD_FAT	| \
				CFG_CMD_ELF	| \
				CFG_CMD_DATE	| \
				CFG_CMD_JFFS2	| \
				CFG_CMD_I2C	| \
				CFG_CMD_MII	| \
				CFG_CMD_PING	| \
				CFG_CMD_BSP	| \
				CFG_CMD_EEPROM	)

#if 0 /* test-only */
#define CONFIG_NETCONSOLE
#define CONFIG_NET_MULTI

#ifdef CONFIG_NET_MULTI
#define CONFIG_PHY1_ADDR	1	/* PHY address: for NetConsole	*/
#endif
#endif

#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION

#define CONFIG_SUPPORT_VFAT

#if 0 /* test-only */
#define CONFIG_AUTO_UPDATE      1       /* autoupdate via compactflash  */
#endif

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

#define CFG_NAND_LEGACY

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory		*/
#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/

#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
#ifdef	CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2	"> "
#endif

#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/

#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/

#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */

#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
#define CFG_BASE_BAUD	    691200

/* The following table includes the supported baudrates */
#define CFG_BAUDRATE_TABLE	\
	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
	 57600, 115200, 230400, 460800, 921600 }

#define CFG_LOAD_ADDR	0x100000	/* default load address */
#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */

#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */

#define CONFIG_LOOPW            1       /* enable loopw command         */

#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */

#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */

#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
#define PCI_HOST_FORCE  1               /* configure as pci host        */
#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */

#define CONFIG_PCI			/* include pci support	        */
#define CONFIG_PCI_HOST	PCI_HOST_AUTO   /* select pci host function     */
#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
					/* resource configuration       */

#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */

#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/

#define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/

#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
#define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A    */
#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
#define CFG_PCI_PTM1LA  (bd->bi_memstart) /* point to sdram               */
#define CFG_PCI_PTM1MS  (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */

/*-----------------------------------------------------------------------
 * IDE/ATA stuff
 *-----------------------------------------------------------------------
 */
#undef	CONFIG_IDE_8xx_DIRECT		    /* no pcmcia interface required */
#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
#define CONFIG_IDE_RESET	1	/* reset for ide supported	*/

#define CFG_IDE_MAXBUS		1		/* max. 1 IDE busses	*/
#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */

#define CFG_ATA_BASE_ADDR	0xF0100000
#define CFG_ATA_IDE0_OFFSET	0x0000

#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
#define CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
#define CFG_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define CFG_SDRAM_BASE		0x00000000
#define CFG_FLASH_BASE		0xFFFC0000
#define CFG_MONITOR_BASE	CFG_FLASH_BASE
#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
/*
 * The following defines are added for buggy IOP480 byte interface.
 * All other boards should use the standard values (CPCI405 etc.)
 */
#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/

#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */


/*
 * JFFS2 partitions
 */

/* No command line, one static partition, use whole device */
#undef CONFIG_JFFS2_CMDLINE
#define CONFIG_JFFS2_DEV		"nor0"
#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
#define CONFIG_JFFS2_PART_OFFSET	0x00000000

/* mtdparts command line support */

/* Use first bank for JFFS2, second bank contains U-Boot.
 *
 * Note: fake mtd_id's used, no linux mtd map file.
 */
/*
#define CONFIG_JFFS2_CMDLINE
#define MTDIDS_DEFAULT		"nor0=cpci4052-0"
#define MTDPARTS_DEFAULT	"mtdparts=cpci4052-0:-(jffs2)"
*/

#if 0 /* Use NVRAM for environment variables */
/*-----------------------------------------------------------------------
 * NVRAM organization
 */
#define CFG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
#define CFG_ENV_SIZE		0x0ff8		/* Size of Environment vars	*/
#define CFG_ENV_ADDR		\
	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-(CFG_ENV_SIZE+8))	/* Env	*/

#else /* Use EEPROM for environment variables */

#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
#define CFG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
#define CFG_ENV_SIZE		0x800	/* 2048 bytes may be used for env vars*/
				   /* total size of a CAT24WC16 is 2048 bytes */
#endif

#define CFG_NVRAM_BASE_ADDR	0xf0200000		/* NVRAM base address	*/
#define CFG_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
#define CFG_VXWORKS_MAC_PTR     (CFG_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/

/*-----------------------------------------------------------------------
 * I2C EEPROM (CAT24WC16) for environment
 */
#define CONFIG_HARD_I2C			/* I2c with hardware support */
#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
#define CFG_I2C_SLAVE		0x7F

#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
/* mask of address bits that overflow into the "EEPROM chip address"	*/
#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
					/* 16 byte page write mode using*/
					/* last 4 bits of the address	*/
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_DCACHE_SIZE		16384	/* For AMCC 405 CPUs, older 405 ppc's	*/
					/* have only 8kB, 16kB is save here	*/
#define CFG_CACHELINE_SIZE	32	/* ...			*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
#endif

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0xFF800000	/* FLASH bank #0	*/
#define FLASH_BASE1_PRELIM	0xFFC00000	/* FLASH bank #1	*/

/*-----------------------------------------------------------------------
 * External Bus Controller (EBC) Setup
 */

/* Memory Bank 0 (Flash Bank 0) initialization					*/
#define CFG_EBC_PB0AP		0x92015480
#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */

/* Memory Bank 1 (Flash Bank 1) initialization					*/
#define CFG_EBC_PB1AP		0x92015480
#define CFG_EBC_PB1CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */

/* Memory Bank 2 (CAN0, 1) initialization					*/
#define CFG_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
#define CFG_LED_ADDR		0xF0000380

/* Memory Bank 3 (CompactFlash IDE) initialization				*/
#define CFG_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CFG_EBC_PB3CR		0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */

/* Memory Bank 4 (NVRAM/RTC) initialization					*/
/*#define CFG_EBC_PB4AP		  0x01805280  / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1	   */
#define CFG_EBC_PB4AP		0x01805680  /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1	*/
#define CFG_EBC_PB4CR		0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit	*/

/* Memory Bank 5 (optional Quart) initialization				*/
#define CFG_EBC_PB5AP		0x04005B80  /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
#define CFG_EBC_PB5CR		0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit	*/

/* Memory Bank 6 (FPGA internal) initialization					*/
#define CFG_EBC_PB6AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CFG_EBC_PB6CR		0xF041A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
#define CFG_FPGA_BASE_ADDR	0xF0400000

/*-----------------------------------------------------------------------
 * FPGA stuff
 */
/* FPGA internal regs */
#define CFG_FPGA_MODE		0x00
#define CFG_FPGA_STATUS		0x02
#define CFG_FPGA_TS		0x04
#define CFG_FPGA_TS_LOW		0x06
#define CFG_FPGA_TS_CAP0	0x10
#define CFG_FPGA_TS_CAP0_LOW	0x12
#define CFG_FPGA_TS_CAP1	0x14
#define CFG_FPGA_TS_CAP1_LOW	0x16
#define CFG_FPGA_TS_CAP2	0x18
#define CFG_FPGA_TS_CAP2_LOW	0x1a
#define CFG_FPGA_TS_CAP3	0x1c
#define CFG_FPGA_TS_CAP3_LOW	0x1e

/* FPGA Mode Reg */
#define CFG_FPGA_MODE_CF_RESET	    0x0001
#define CFG_FPGA_MODE_DUART_RESET   0x0002
#define CFG_FPGA_MODE_ENABLE_OUTPUT 0x0004     /* only set on CPCI-405 Ver 3 */
#define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100
#define CFG_FPGA_MODE_TS_IRQ_CLEAR  0x1000
#define CFG_FPGA_MODE_TS_CLEAR	    0x2000

/* FPGA Status Reg */
#define CFG_FPGA_STATUS_DIP0	0x0001
#define CFG_FPGA_STATUS_DIP1	0x0002
#define CFG_FPGA_STATUS_DIP2	0x0004
#define CFG_FPGA_STATUS_FLASH	0x0008
#define CFG_FPGA_STATUS_TS_IRQ	0x1000

#define CFG_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
#define CFG_FPGA_MAX_SIZE	32*1024	    /* 32kByte is enough for XC2S15  */

/* FPGA program pin configuration */
#define CFG_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
#define CFG_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
#define CFG_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
#define CFG_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input)     */
#define CFG_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input)     */

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in data cache)
 */
#define CFG_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */

#define CFG_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
#define CFG_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET


/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

#endif	/* __CONFIG_H */
Commit	Line	Data
c609719b	1	/*
a20b27a3	2	* (C) Copyright 2001-2004
c609719b WD	3	* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* board/config.h - configuration options, board specific
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	/*
	32	* High Level Configuration Options
	33	* (easy to change)
	34	*/
	35
	36	#define CONFIG_405GP 1 /* This is a PPC405 CPU */
c837dcb1	37	#define CONFIG_4xx 1 /* ...member of PPC4xx family */
c609719b	38	#define CONFIG_CPCI405 1 /* ...on a CPCI405 board */
c837dcb1	39	#define CONFIG_CPCI405_VER2 1 /* ...version 2 */
c609719b	40
c837dcb1	41	#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
c609719b	42
a20b27a3	43	#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
c609719b WD	44
	45	#define CONFIG_BAUDRATE 9600
	46	#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
	47
c609719b	48	#undef CONFIG_BOOTARGS
a20b27a3 SR	49	#undef CONFIG_BOOTCOMMAND
	50
	51	#define CONFIG_PREBOOT /* enable preboot variable */
c609719b WD	52
	53	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	54	#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
	55
	56	#define CONFIG_MII 1 /* MII PHY management */
c837dcb1	57	#define CONFIG_PHY_ADDR 0 /* PHY address */
a20b27a3	58	#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
c609719b WD	59
	60	#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
	61
c837dcb1	62	#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT \| \
fe389a82 SR	63	CONFIG_BOOTP_DNS \| \
	64	CONFIG_BOOTP_DNS2 \| \
	65	CONFIG_BOOTP_SEND_HOSTNAME )
9919f13c	66
c609719b	67	#define CONFIG_COMMANDS ( CONFIG_CMD_DFL \| \
9919f13c	68	CFG_CMD_DHCP \| \
c609719b WD	69	CFG_CMD_PCI \| \
	70	CFG_CMD_IRQ \| \
	71	CFG_CMD_IDE \| \
a20b27a3	72	CFG_CMD_FAT \| \
c609719b WD	73	CFG_CMD_ELF \| \
	74	CFG_CMD_DATE \| \
	75	CFG_CMD_JFFS2 \| \
	76	CFG_CMD_I2C \| \
ad10dd9a	77	CFG_CMD_MII \| \
a0e135b4	78	CFG_CMD_PING \| \
a20b27a3	79	CFG_CMD_BSP \| \
c837dcb1	80	CFG_CMD_EEPROM )
c609719b	81
a20b27a3 SR	82	#if 0 /* test-only */
	83	#define CONFIG_NETCONSOLE
	84	#define CONFIG_NET_MULTI
	85
	86	#ifdef CONFIG_NET_MULTI
	87	#define CONFIG_PHY1_ADDR 1 /* PHY address: for NetConsole */
	88	#endif
	89	#endif
	90
c609719b WD	91	#define CONFIG_MAC_PARTITION
	92	#define CONFIG_DOS_PARTITION
	93
a20b27a3 SR	94	#define CONFIG_SUPPORT_VFAT
	95
	96	#if 0 /* test-only */
	97	#define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */
	98	#endif
	99
c609719b WD	100	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
	101	#include <cmd_confdefs.h>
	102
addb2e16 BS	103	#define CFG_NAND_LEGACY
addb2e16 BS	104
c837dcb1	105	#undef CONFIG_WATCHDOG /* watchdog disabled */
c609719b	106
c837dcb1	107	#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
c609719b WD	108
	109	/*
	110	* Miscellaneous configurable options
	111	*/
	112	#define CFG_LONGHELP /* undef to save memory */
	113	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	114
	115	#undef CFG_HUSH_PARSER /* use "hush" command parser */
	116	#ifdef CFG_HUSH_PARSER
c837dcb1	117	#define CFG_PROMPT_HUSH_PS2 "> "
c609719b WD	118	#endif
	119
	120	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
c837dcb1	121	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
c609719b	122	#else
c837dcb1	123	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
c609719b WD	124	#endif
	125	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	126	#define CFG_MAXARGS 16 /* max number of command args */
	127	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	128
c837dcb1	129	#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
c609719b	130
c837dcb1	131	#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
c609719b	132
a20b27a3 SR	133	#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
a20b27a3 SR	134
c609719b WD	135	#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
	136	#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
	137
c837dcb1 WD	138	#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
	139	#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
	140	#define CFG_BASE_BAUD 691200
c609719b WD	141
c609719b WD	142	/* The following table includes the supported baudrates */
c837dcb1	143	#define CFG_BAUDRATE_TABLE \
8bde7f77 WD	144	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
8bde7f77 WD	145	57600, 115200, 230400, 460800, 921600 }
c609719b WD	146
	147	#define CFG_LOAD_ADDR 0x100000 /* default load address */
	148	#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
	149
c837dcb1	150	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
c609719b	151
a20b27a3 SR	152	#define CONFIG_LOOPW 1 /* enable loopw command */
a20b27a3 SR	153
c609719b WD	154	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
c609719b WD	155
c837dcb1	156	#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
9e7d5ebe	157
c837dcb1	158	#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
53cf9435	159
c609719b WD	160	/*-----------------------------------------------------------------------
	161	* PCI stuff
	162	*-----------------------------------------------------------------------
	163	*/
a20b27a3 SR	164	#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
	165	#define PCI_HOST_FORCE 1 /* configure as pci host */
	166	#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
	167
	168	#define CONFIG_PCI /* include pci support */
	169	#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
	170	#define CONFIG_PCI_PNP /* do pci plug-and-play */
	171	/* resource configuration */
	172
	173	#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
	174
	175	#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
	176
	177	#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
	178
	179	#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
	180	#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
	181	#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */
	182	#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
2076d0a1 SR	183	#define CFG_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
2076d0a1 SR	184	#define CFG_PCI_PTM1MS (~(bd->bi_memsize - 1) \| 1) /* memsize, enable hard-wired to 1 */
a20b27a3 SR	185	#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
	186	#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
	187	#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
	188	#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
c609719b WD	189
	190	/*-----------------------------------------------------------------------
	191	* IDE/ATA stuff
	192	*-----------------------------------------------------------------------
	193	*/
c837dcb1 WD	194	#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
c837dcb1 WD	195	#undef CONFIG_IDE_LED /* no led for ide supported */
c609719b WD	196	#define CONFIG_IDE_RESET 1 /* reset for ide supported */
c609719b WD	197
c837dcb1 WD	198	#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
c837dcb1 WD	199	#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS1) / max. 1 drives per IDE bus */
c609719b	200
c837dcb1 WD	201	#define CFG_ATA_BASE_ADDR 0xF0100000
c837dcb1 WD	202	#define CFG_ATA_IDE0_OFFSET 0x0000
c609719b WD	203
c609719b WD	204	#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
c837dcb1	205	#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
c609719b WD	206	#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
	207
	208	/*-----------------------------------------------------------------------
	209	* Start addresses for the final memory configuration
	210	* (Set up by the startup code)
	211	* Please note that CFG_SDRAM_BASE _must_ start at 0
	212	*/
	213	#define CFG_SDRAM_BASE 0x00000000
	214	#define CFG_FLASH_BASE 0xFFFC0000
	215	#define CFG_MONITOR_BASE CFG_FLASH_BASE
	216	#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
	217	#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
	218
	219	/*
	220	* For booting Linux, the board info and command line data
	221	* have to be in the first 8 MB of memory, since this is
	222	* the maximum mapped by the Linux kernel during initialization.
	223	*/
	224	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	225	/*-----------------------------------------------------------------------
	226	* FLASH organization
	227	*/
	228	#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
	229	#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
	230
	231	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	232	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
	233
c837dcb1 WD	234	#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
	235	#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
	236	#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
c609719b WD	237	/*
	238	* The following defines are added for buggy IOP480 byte interface.
	239	* All other boards should use the standard values (CPCI405 etc.)
	240	*/
c837dcb1 WD	241	#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
	242	#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
	243	#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
c609719b	244
c837dcb1	245	#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
c609719b	246
700a0c64 WD	247
	248	/*
	249	* JFFS2 partitions
	250	*/
	251
	252	/* No command line, one static partition, use whole device */
	253	#undef CONFIG_JFFS2_CMDLINE
	254	#define CONFIG_JFFS2_DEV "nor0"
	255	#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
	256	#define CONFIG_JFFS2_PART_OFFSET 0x00000000
	257
	258	/* mtdparts command line support */
	259
	260	/* Use first bank for JFFS2, second bank contains U-Boot.
	261	*
	262	* Note: fake mtd_id's used, no linux mtd map file.
	263	*/
	264	/*
	265	#define CONFIG_JFFS2_CMDLINE
	266	#define MTDIDS_DEFAULT "nor0=cpci4052-0"
	267	#define MTDPARTS_DEFAULT "mtdparts=cpci4052-0:-(jffs2)"
	268	*/
c609719b WD	269
	270	#if 0 /* Use NVRAM for environment variables */
	271	/*-----------------------------------------------------------------------
	272	* NVRAM organization
	273	*/
	274	#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
	275	#define CFG_ENV_SIZE 0x0ff8 /* Size of Environment vars */
	276	#define CFG_ENV_ADDR \
	277	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-(CFG_ENV_SIZE+8)) /* Env */
	278
	279	#else /* Use EEPROM for environment variables */
	280
c837dcb1 WD	281	#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
	282	#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
	283	#define CFG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/
8bde7f77	284	/* total size of a CAT24WC16 is 2048 bytes */
c609719b WD	285	#endif
	286
	287	#define CFG_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */
	288	#define CFG_NVRAM_SIZE (321024) / NVRAM size */
a20b27a3	289	#define CFG_VXWORKS_MAC_PTR (CFG_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
c609719b WD	290
	291	/*-----------------------------------------------------------------------
	292	* I2C EEPROM (CAT24WC16) for environment
	293	*/
	294	#define CONFIG_HARD_I2C /* I2c with hardware support */
	295	#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
	296	#define CFG_I2C_SLAVE 0x7F
	297
	298	#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
c837dcb1 WD	299	#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
c837dcb1 WD	300	/* mask of address bits that overflow into the "EEPROM chip address" */
c609719b WD	301	#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
	302	#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
	303	/* 16 byte page write mode using*/
c837dcb1	304	/* last 4 bits of the address */
c609719b WD	305	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
	306	#define CFG_EEPROM_PAGE_WRITE_ENABLE
	307
	308	/*-----------------------------------------------------------------------
	309	* Cache Configuration
	310	*/
0c8721a4	311	#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
c837dcb1	312	/* have only 8kB, 16kB is save here */
c609719b WD	313	#define CFG_CACHELINE_SIZE 32 /* ... */
	314	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	315	#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
	316	#endif
	317
	318	/*
	319	* Init Memory Controller:
	320	*
	321	* BR0/1 and OR0/1 (FLASH)
	322	*/
	323
	324	#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
	325	#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */
	326
	327	/*-----------------------------------------------------------------------
	328	* External Bus Controller (EBC) Setup
	329	*/
	330
c837dcb1 WD	331	/* Memory Bank 0 (Flash Bank 0) initialization */
	332	#define CFG_EBC_PB0AP 0x92015480
	333	#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
c609719b	334
c837dcb1 WD	335	/* Memory Bank 1 (Flash Bank 1) initialization */
	336	#define CFG_EBC_PB1AP 0x92015480
	337	#define CFG_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
c609719b	338
c837dcb1 WD	339	/* Memory Bank 2 (CAN0, 1) initialization */
	340	#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
	341	#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
	342	#define CFG_LED_ADDR 0xF0000380
c609719b	343
c837dcb1 WD	344	/* Memory Bank 3 (CompactFlash IDE) initialization */
	345	#define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
	346	#define CFG_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
c609719b	347
c837dcb1 WD	348	/* Memory Bank 4 (NVRAM/RTC) initialization */
	349	/#define CFG_EBC_PB4AP 0x01805280 / TWT=3,WBN=1,WBF=1,TH=1,SOR=1 */
	350	#define CFG_EBC_PB4AP 0x01805680 /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1 */
	351	#define CFG_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
c609719b	352
c837dcb1 WD	353	/* Memory Bank 5 (optional Quart) initialization */
	354	#define CFG_EBC_PB5AP 0x04005B80 /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
	355	#define CFG_EBC_PB5CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
c609719b	356
c837dcb1 WD	357	/* Memory Bank 6 (FPGA internal) initialization */
	358	#define CFG_EBC_PB6AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
	359	#define CFG_EBC_PB6CR 0xF041A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
	360	#define CFG_FPGA_BASE_ADDR 0xF0400000
c609719b WD	361
	362	/*-----------------------------------------------------------------------
	363	* FPGA stuff
	364	*/
	365	/* FPGA internal regs */
c837dcb1 WD	366	#define CFG_FPGA_MODE 0x00
	367	#define CFG_FPGA_STATUS 0x02
	368	#define CFG_FPGA_TS 0x04
	369	#define CFG_FPGA_TS_LOW 0x06
	370	#define CFG_FPGA_TS_CAP0 0x10
	371	#define CFG_FPGA_TS_CAP0_LOW 0x12
	372	#define CFG_FPGA_TS_CAP1 0x14
	373	#define CFG_FPGA_TS_CAP1_LOW 0x16
	374	#define CFG_FPGA_TS_CAP2 0x18
	375	#define CFG_FPGA_TS_CAP2_LOW 0x1a
	376	#define CFG_FPGA_TS_CAP3 0x1c
	377	#define CFG_FPGA_TS_CAP3_LOW 0x1e
c609719b WD	378
c609719b WD	379	/* FPGA Mode Reg */
c837dcb1	380	#define CFG_FPGA_MODE_CF_RESET 0x0001
6f4474e8 SR	381	#define CFG_FPGA_MODE_DUART_RESET 0x0002
6f4474e8 SR	382	#define CFG_FPGA_MODE_ENABLE_OUTPUT 0x0004 /* only set on CPCI-405 Ver 3 */
c609719b WD	383	#define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100
c609719b WD	384	#define CFG_FPGA_MODE_TS_IRQ_CLEAR 0x1000
c837dcb1	385	#define CFG_FPGA_MODE_TS_CLEAR 0x2000
c609719b WD	386
c609719b WD	387	/* FPGA Status Reg */
c837dcb1 WD	388	#define CFG_FPGA_STATUS_DIP0 0x0001
	389	#define CFG_FPGA_STATUS_DIP1 0x0002
	390	#define CFG_FPGA_STATUS_DIP2 0x0004
	391	#define CFG_FPGA_STATUS_FLASH 0x0008
	392	#define CFG_FPGA_STATUS_TS_IRQ 0x1000
c609719b	393
c837dcb1 WD	394	#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
c837dcb1 WD	395	#define CFG_FPGA_MAX_SIZE 321024 / 32kByte is enough for XC2S15 */
c609719b WD	396
c609719b WD	397	/* FPGA program pin configuration */
c837dcb1 WD	398	#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
	399	#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
	400	#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
	401	#define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
	402	#define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
c609719b WD	403
	404	/*-----------------------------------------------------------------------
	405	* Definitions for initial stack pointer and data area (in data cache)
	406	*/
c837dcb1	407	#define CFG_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
c609719b	408
c837dcb1 WD	409	#define CFG_INIT_RAM_ADDR 0x40000000 /* use data cache */
c837dcb1 WD	410	#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
c609719b WD	411	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
c609719b WD	412	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
c837dcb1	413	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
c609719b WD	414
	415
	416	/*
	417	* Internal Definitions
	418	*
	419	* Boot Flags
	420	*/
	421	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	422	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	423
	424	#endif /* __CONFIG_H */