projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| a20b27a3 SR |
1 | /* |
| 2 | * (C) Copyright 2001 | |
| 3 | * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. | |
| 4 | * | |
| 5 | * See file CREDITS for list of people who contributed to this | |
| 6 | * project. | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or | |
| 9 | * modify it under the terms of the GNU General Public License as | |
| 10 | * published by the Free Software Foundation; either version 2 of | |
| 11 | * the License, or (at your option) any later version. | |
| 12 | * | |
| 13 | * This program is distributed in the hope that it will be useful, | |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| bfc81252 | 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| a20b27a3 SR |
16 | * GNU General Public License for more details. |
| 17 | * | |
| 18 | * You should have received a copy of the GNU General Public License | |
| 19 | * along with this program; if not, write to the Free Software | |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 21 | * MA 02111-1307 USA | |
| 22 | */ | |
| 23 | ||
| 24 | /* | |
| 25 | * board/config.h - configuration options, board specific | |
| 26 | */ | |
| 27 | ||
| 28 | /************************************************************************* | |
| 29 | * (c) 2004 esd gmbh Hannover | |
| 30 | * | |
| 31 | * | |
| 32 | * from db64360.h file | |
| 33 | * by Reinhard Arlt reinhard.arlt@esd-electronics.com | |
| 34 | * | |
| 35 | ************************************************************************/ | |
| 36 | ||
| 37 | ||
| 38 | #ifndef __CONFIG_H | |
| 39 | #define __CONFIG_H | |
| 40 | ||
| a20b27a3 SR |
41 | /* This define must be before the core.h include */ |
| 42 | #define CONFIG_CPCI750 1 /* this is an CPCI750 board */ | |
| 43 | ||
| 44 | #ifndef __ASSEMBLY__ | |
| 45 | #include <../board/Marvell/include/core.h> | |
| 46 | #endif | |
| 47 | /*-----------------------------------------------------*/ | |
| 48 | ||
| 49 | #include "../board/esd/cpci750/local.h" | |
| 50 | ||
| 51 | /* | |
| 52 | * High Level Configuration Options | |
| 53 | * (easy to change) | |
| 54 | */ | |
| 55 | ||
| 56 | #define CONFIG_750FX /* we have a 750FX (override local.h) */ | |
| 57 | ||
| 58 | #define CONFIG_CPCI750 1 /* this is an CPCI750 board */ | |
| 59 | ||
| bfc81252 | 60 | #define CONFIG_BAUDRATE 9600 /* console baudrate = 9600 */ |
| a20b27a3 SR |
61 | |
| 62 | #undef CONFIG_ECC /* enable ECC support */ | |
| 63 | ||
| 31d82672 BB |
64 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
| 65 | ||
| a20b27a3 SR |
66 | /* which initialization functions to call for this board */ |
| 67 | #define CONFIG_MISC_INIT_R | |
| 68 | #define CONFIG_BOARD_PRE_INIT | |
| 69 | #define CONFIG_BOARD_EARLY_INIT_F 1 | |
| 70 | ||
| 71 | #define CFG_BOARD_NAME "CPCI750" | |
| 72 | #define CONFIG_IDENT_STRING "Marvell 64360 + IBM750FX" | |
| 73 | ||
| 74 | /*#define CFG_HUSH_PARSER*/ | |
| a7b9fb91 | 75 | #define CFG_HUSH_PARSER |
| a20b27a3 SR |
76 | |
| 77 | #define CFG_PROMPT_HUSH_PS2 "> " | |
| 78 | ||
| 8078f1a5 | 79 | #define CONFIG_AUTO_COMPLETE 1 |
| a7b9fb91 | 80 | |
| a20b27a3 SR |
81 | /* Define which ETH port will be used for connecting the network */ |
| 82 | #define CFG_ETH_PORT ETH_0 | |
| 83 | ||
| 84 | /* | |
| 85 | * The following defines let you select what serial you want to use | |
| 86 | * for your console driver. | |
| 87 | * | |
| 88 | * what to do: | |
| bfc81252 | 89 | * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial |
| a20b27a3 SR |
90 | * cable onto the second DUART channel, change the CFG_DUART port from 1 |
| 91 | * to 0 below. | |
| 92 | * | |
| 93 | * to use the MPSC, #define CONFIG_MPSC. If you have wired up another | |
| 94 | * mpsc channel, change CONFIG_MPSC_PORT to the desired value. | |
| 95 | */ | |
| bfc81252 | 96 | #define CONFIG_MPSC |
| a20b27a3 SR |
97 | #define CONFIG_MPSC_PORT 0 |
| 98 | ||
| 99 | /* to change the default ethernet port, use this define (options: 0, 1, 2) */ | |
| 100 | #define CONFIG_NET_MULTI | |
| bfc81252 | 101 | #define MV_ETH_DEVS 1 |
| a20b27a3 SR |
102 | #define CONFIG_ETHER_PORT 0 |
| 103 | ||
| 104 | #undef CONFIG_ETHER_PORT_MII /* use RMII */ | |
| 105 | ||
| 106 | #define CONFIG_BOOTDELAY 5 /* autoboot disabled */ | |
| 107 | ||
| 108 | #define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ | |
| 109 | ||
| 110 | #define CONFIG_ZERO_BOOTDELAY_CHECK | |
| 111 | ||
| 112 | ||
| 113 | #undef CONFIG_BOOTARGS | |
| 114 | ||
| 115 | /* ----------------------------------------------------------------------------- | |
| 116 | * New bootcommands for Marvell CPCI750 c 2002 Ingo Assmus | |
| 117 | */ | |
| 118 | ||
| 119 | #define CONFIG_IPADDR "192.168.0.185" | |
| 120 | ||
| 121 | #define CONFIG_SERIAL "AA000001" | |
| 122 | #define CONFIG_SERVERIP "10.0.0.79" | |
| bfc81252 | 123 | #define CONFIG_ROOTPATH "/export/nfs_cpci750/%s" |
| a20b27a3 SR |
124 | |
| 125 | #define CONFIG_TESTDRAMDATA y | |
| bfc81252 | 126 | #define CONFIG_TESTDRAMADDRESS n |
| a20b27a3 SR |
127 | #define CONFIG_TESETDRAMWALK n |
| 128 | ||
| 129 | /* ----------------------------------------------------------------------------- */ | |
| 130 | ||
| 131 | ||
| bfc81252 WD |
132 | #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ |
| 133 | #define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */ | |
| a20b27a3 SR |
134 | |
| 135 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
| bfc81252 | 136 | #undef CONFIG_ALTIVEC /* undef to disable */ |
| a20b27a3 | 137 | |
| 5d2ebe1b JL |
138 | /* |
| 139 | * BOOTP options | |
| 140 | */ | |
| 141 | #define CONFIG_BOOTP_SUBNETMASK | |
| 142 | #define CONFIG_BOOTP_GATEWAY | |
| 143 | #define CONFIG_BOOTP_HOSTNAME | |
| 144 | #define CONFIG_BOOTP_BOOTPATH | |
| 145 | #define CONFIG_BOOTP_BOOTFILESIZE | |
| a20b27a3 SR |
146 | |
| 147 | ||
| 49cf7e8e JL |
148 | /* |
| 149 | * Command line configuration. | |
| 150 | */ | |
| 151 | #include <config_cmd_default.h> | |
| 152 | ||
| 5728be38 WD |
153 | #define CONFIG_CMD_ASKENV |
| 154 | #define CONFIG_CMD_I2C | |
| 155 | #define CONFIG_CMD_CACHE | |
| 156 | #define CONFIG_CMD_EEPROM | |
| 157 | #define CONFIG_CMD_PCI | |
| 158 | #define CONFIG_CMD_ELF | |
| 159 | #define CONFIG_CMD_DATE | |
| 160 | #define CONFIG_CMD_NET | |
| 161 | #define CONFIG_CMD_PING | |
| 162 | #define CONFIG_CMD_IDE | |
| 163 | #define CONFIG_CMD_FAT | |
| 164 | #define CONFIG_CMD_EXT2 | |
| a20b27a3 | 165 | |
| a20b27a3 | 166 | |
| 49cf7e8e | 167 | #define CONFIG_DOS_PARTITION |
| a20b27a3 | 168 | |
| a7b9fb91 SR |
169 | #define CONFIG_USE_CPCIDVI |
| 170 | ||
| bfc81252 | 171 | #ifdef CONFIG_USE_CPCIDVI |
| a7b9fb91 SR |
172 | #define CONFIG_VIDEO |
| 173 | #define CONFIG_VIDEO_CT69000 | |
| 174 | #define CONFIG_CFB_CONSOLE | |
| 175 | #define CONFIG_VIDEO_SW_CURSOR | |
| 176 | #define CONFIG_VIDEO_LOGO | |
| 177 | #define CONFIG_I8042_KBD | |
| 178 | #define CFG_ISA_IO 0 | |
| 179 | #endif | |
| 180 | ||
| a20b27a3 SR |
181 | /* |
| 182 | * Miscellaneous configurable options | |
| 183 | */ | |
| 184 | #define CFG_I2C_EEPROM_ADDR_LEN 2 | |
| 185 | #define CFG_I2C_MULTI_EEPROMS | |
| bfc81252 | 186 | #define CFG_I2C_SPEED 80000 /* I2C speed default */ |
| a20b27a3 SR |
187 | |
| 188 | #define CFG_GT_DUAL_CPU /* also for JTAG even with one cpu */ | |
| bfc81252 WD |
189 | #define CFG_LONGHELP /* undef to save memory */ |
| 190 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
| 49cf7e8e | 191 | #if defined(CONFIG_CMD_KGDB) |
| bfc81252 | 192 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
| a20b27a3 | 193 | #else |
| bfc81252 | 194 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
| a20b27a3 | 195 | #endif |
| bfc81252 WD |
196 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
| 197 | #define CFG_MAXARGS 16 /* max number of command args */ | |
| a20b27a3 SR |
198 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
| 199 | ||
| 200 | /*#define CFG_MEMTEST_START 0x00400000*/ /* memtest works on */ | |
| 201 | /*#define CFG_MEMTEST_END 0x00C00000*/ /* 4 ... 12 MB in DRAM */ | |
| bfc81252 | 202 | /*#define CFG_MEMTEST_END 0x07c00000*/ /* 4 ... 124 MB in DRAM */ |
| a20b27a3 SR |
203 | |
| 204 | /* | |
| 205 | #define CFG_DRAM_TEST | |
| 206 | * DRAM tests | |
| 207 | * CFG_DRAM_TEST - enables the following tests. | |
| 208 | * | |
| 209 | * CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines | |
| bfc81252 WD |
210 | * Environment variable 'test_dram_data' must be |
| 211 | * set to 'y'. | |
| a20b27a3 | 212 | * CFG_DRAM_TEST_DATA - Enables test to verify that each word is uniquely |
| bfc81252 WD |
213 | * addressable. Environment variable |
| 214 | * 'test_dram_address' must be set to 'y'. | |
| a20b27a3 | 215 | * CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test. |
| bfc81252 WD |
216 | * This test takes about 6 minutes to test 64 MB. |
| 217 | * Environment variable 'test_dram_walk' must be | |
| 218 | * set to 'y'. | |
| a20b27a3 SR |
219 | */ |
| 220 | #define CFG_DRAM_TEST | |
| 221 | #if defined(CFG_DRAM_TEST) | |
| 222 | #define CFG_MEMTEST_START 0x00400000 /* memtest works on */ | |
| 223 | /*#define CFG_MEMTEST_END 0x00C00000*/ /* 4 ... 12 MB in DRAM */ | |
| bfc81252 | 224 | #define CFG_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */ |
| a20b27a3 SR |
225 | #define CFG_DRAM_TEST_DATA |
| 226 | #define CFG_DRAM_TEST_ADDRESS | |
| 227 | #define CFG_DRAM_TEST_WALK | |
| 228 | #endif /* CFG_DRAM_TEST */ | |
| 229 | ||
| 230 | #define CONFIG_DISPLAY_MEMMAP /* at the end of the bootprocess show the memory map */ | |
| 231 | #undef CFG_DISPLAY_DIMM_SPD_CONTENT /* show SPD content during boot */ | |
| 232 | ||
| bfc81252 | 233 | #define CFG_LOAD_ADDR 0x00300000 /* default load address */ |
| a20b27a3 | 234 | |
| bfc81252 WD |
235 | #define CFG_HZ 1000 /* decr freq: 1ms ticks */ |
| 236 | #define CFG_BUS_HZ 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */ | |
| a20b27a3 SR |
237 | #define CFG_BUS_CLK CFG_BUS_HZ |
| 238 | ||
| 239 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } | |
| 240 | ||
| 241 | #define CFG_TCLK 133000000 | |
| 242 | ||
| 243 | /*#define CFG_750FX_HID0 0x8000c084*/ | |
| 244 | #define CFG_750FX_HID0 0x80008484 | |
| 245 | #define CFG_750FX_HID1 0x54800000 | |
| 246 | #define CFG_750FX_HID2 0x00000000 | |
| 247 | ||
| 248 | /* | |
| 249 | * Low Level Configuration Settings | |
| 250 | * (address mappings, register initial values, etc.) | |
| 251 | * You should know what you are doing if you make changes here. | |
| 252 | */ | |
| 253 | ||
| 254 | /*----------------------------------------------------------------------- | |
| 255 | * Definitions for initial stack pointer and data area | |
| 256 | */ | |
| 257 | ||
| 258 | /* | |
| 259 | * When locking data in cache you should point the CFG_INIT_RAM_ADDRESS | |
| 260 | * To an unused memory region. The stack will remain in cache until RAM | |
| 261 | * is initialized | |
| 262 | */ | |
| bfc81252 | 263 | #undef CFG_INIT_RAM_LOCK |
| a20b27a3 SR |
264 | /* #define CFG_INIT_RAM_ADDR 0x40000000*/ /* unused memory region */ |
| 265 | /* #define CFG_INIT_RAM_ADDR 0xfba00000*/ /* unused memory region */ | |
| 266 | #define CFG_INIT_RAM_ADDR 0xf1080000 /* unused memory region */ | |
| 267 | #define CFG_INIT_RAM_END 0x1000 | |
| 268 | #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */ | |
| 269 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
| 270 | ||
| 271 | #define RELOCATE_INTERNAL_RAM_ADDR | |
| 272 | #ifdef RELOCATE_INTERNAL_RAM_ADDR | |
| bfc81252 | 273 | /*#define CFG_INTERNAL_RAM_ADDR 0xfba00000*/ |
| a20b27a3 SR |
274 | #define CFG_INTERNAL_RAM_ADDR 0xf1080000 |
| 275 | #endif | |
| 276 | ||
| 277 | /*----------------------------------------------------------------------- | |
| 278 | * Start addresses for the final memory configuration | |
| 279 | * (Set up by the startup code) | |
| 280 | * Please note that CFG_SDRAM_BASE _must_ start at 0 | |
| 281 | */ | |
| bfc81252 | 282 | #define CFG_SDRAM_BASE 0x00000000 |
| a20b27a3 | 283 | /* Dummies for BAT 4-7 */ |
| bfc81252 WD |
284 | #define CFG_SDRAM1_BASE 0x10000000 /* each 256 MByte */ |
| 285 | #define CFG_SDRAM2_BASE 0x20000000 | |
| 286 | #define CFG_SDRAM3_BASE 0x30000000 | |
| 287 | #define CFG_SDRAM4_BASE 0x40000000 | |
| a20b27a3 | 288 | #define CFG_RESET_ADDRESS 0xfff00100 |
| bfc81252 | 289 | #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
| a20b27a3 | 290 | #define CFG_MONITOR_BASE 0xfff00000 |
| bfc81252 | 291 | #define CFG_MALLOC_LEN (128 << 10) /* Reserve 256 kB for malloc */ |
| a20b27a3 SR |
292 | |
| 293 | /*----------------------------------------------------------------------- | |
| 294 | * FLASH related | |
| 295 | *----------------------------------------------------------------------*/ | |
| 296 | ||
| 00b1883a | 297 | #define CONFIG_FLASH_CFI_DRIVER |
| a20b27a3 | 298 | #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ |
| a20b27a3 SR |
299 | #define CFG_FLASH_PROTECTION 1 /* use hardware protection */ |
| 300 | #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ | |
| bfc81252 | 301 | #define CFG_FLASH_BASE 0xfc000000 /* start of flash banks */ |
| 79830d59 | 302 | #define CFG_MAX_FLASH_BANKS 4 /* max number of memory banks */ |
| bfc81252 WD |
303 | #define CFG_FLASH_INCREMENT 0x01000000 /* size of flash bank */ |
| 304 | #define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ | |
| 305 | #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, \ | |
| 306 | CFG_FLASH_BASE + 1*CFG_FLASH_INCREMENT, \ | |
| 307 | CFG_FLASH_BASE + 2*CFG_FLASH_INCREMENT, \ | |
| 308 | CFG_FLASH_BASE + 3*CFG_FLASH_INCREMENT } | |
| 309 | #define CFG_FLASH_EMPTY_INFO 1 /* show if bank is empty */ | |
| a20b27a3 SR |
310 | |
| 311 | /* areas to map different things with the GT in physical space */ | |
| 312 | #define CFG_DRAM_BANKS 4 | |
| 313 | ||
| 314 | /* What to put in the bats. */ | |
| 315 | #define CFG_MISC_REGION_BASE 0xf0000000 | |
| 316 | ||
| 317 | /* Peripheral Device section */ | |
| 318 | ||
| 319 | /*******************************************************/ | |
| bfc81252 WD |
320 | /* We have on the cpci750 Board : */ |
| 321 | /* GT-Chipset Register Area */ | |
| 322 | /* GT-Chipset internal SRAM 256k */ | |
| 323 | /* SRAM on external device module */ | |
| 324 | /* Real time clock on external device module */ | |
| 325 | /* dobble UART on external device module */ | |
| 326 | /* Data flash on external device module */ | |
| 327 | /* Boot flash on external device module */ | |
| a20b27a3 SR |
328 | /*******************************************************/ |
| 329 | #define CFG_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */ | |
| bfc81252 | 330 | #define CFG_CPCI750_RESET_ADDR 0x14000000 /* After power on Reset the CPCI750 is here */ |
| a20b27a3 | 331 | |
| bfc81252 WD |
332 | #undef MARVEL_STANDARD_CFG |
| 333 | #ifndef MARVEL_STANDARD_CFG | |
| a20b27a3 SR |
334 | /*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ |
| 335 | #define CFG_GT_REGS 0xf1000000 /* GT Registers will be mapped here */ | |
| 336 | /*#define CFG_DEV_BASE 0xfc000000*/ /* GT Devices CS start here */ | |
| 337 | #define CFG_INT_SRAM_BASE 0xf1080000 /* GT offers 256k internal fast SRAM */ | |
| 338 | ||
| 339 | #define CFG_BOOT_SPACE 0xff000000 /* BOOT_CS0 flash 0 */ | |
| 340 | #define CFG_DEV0_SPACE 0xfc000000 /* DEV_CS0 flash 1 */ | |
| 341 | #define CFG_DEV1_SPACE 0xfd000000 /* DEV_CS1 flash 2 */ | |
| 342 | #define CFG_DEV2_SPACE 0xfe000000 /* DEV_CS2 flash 3 */ | |
| 343 | #define CFG_DEV3_SPACE 0xf0000000 /* DEV_CS3 nvram/can */ | |
| 344 | ||
| bfc81252 WD |
345 | #define CFG_BOOT_SIZE _16M /* cpci750 flash 0 */ |
| 346 | #define CFG_DEV0_SIZE _16M /* cpci750 flash 1 */ | |
| 347 | #define CFG_DEV1_SIZE _16M /* cpci750 flash 2 */ | |
| 348 | #define CFG_DEV2_SIZE _16M /* cpci750 flash 3 */ | |
| 349 | #define CFG_DEV3_SIZE _16M /* cpci750 nvram/can */ | |
| a20b27a3 SR |
350 | |
| 351 | /*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ | |
| 352 | #endif | |
| 353 | ||
| 354 | /* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */ | |
| 355 | #define CFG_DEV0_PAR 0x8FDFFFFF /* 16 bit flash */ | |
| 356 | #define CFG_DEV1_PAR 0x8FDFFFFF /* 16 bit flash */ | |
| 357 | #define CFG_DEV2_PAR 0x8FDFFFFF /* 16 bit flash */ | |
| bfc81252 | 358 | #define CFG_DEV3_PAR 0x8FCFFFFF /* nvram/can */ |
| a20b27a3 SR |
359 | #define CFG_BOOT_PAR 0x8FDFFFFF /* 16 bit flash */ |
| 360 | ||
| bfc81252 WD |
361 | /* c 4 a 8 2 4 1 c */ |
| 362 | /* 33 22|2222|22 22|111 1|11 11|1 1 | | */ | |
| efe2a4d5 WD |
363 | /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */ |
| 364 | /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */ | |
| 365 | /* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */ | |
| a20b27a3 SR |
366 | |
| 367 | ||
| 368 | /* MPP Control MV64360 Appendix P P. 632*/ | |
| bfc81252 WD |
369 | #define CFG_MPP_CONTROL_0 0x00002222 /* */ |
| 370 | #define CFG_MPP_CONTROL_1 0x11110000 /* */ | |
| 371 | #define CFG_MPP_CONTROL_2 0x11111111 /* */ | |
| 372 | #define CFG_MPP_CONTROL_3 0x00001111 /* */ | |
| 373 | /* #define CFG_SERIAL_PORT_MUX 0x00000102*/ /* */ | |
| a20b27a3 SR |
374 | |
| 375 | ||
| 376 | #define CFG_GPP_LEVEL_CONTROL 0xffffffff /* 1111 1111 1111 1111 1111 1111 1111 1111*/ | |
| 377 | ||
| 378 | /* setup new config_value for MV64360 DDR-RAM To_do !! */ | |
| 379 | /*# define CFG_SDRAM_CONFIG 0xd8e18200*/ /* 0x448 */ | |
| 380 | /*# define CFG_SDRAM_CONFIG 0xd8e14400*/ /* 0x1400 */ | |
| 381 | /* GB has high prio. | |
| 382 | idma has low prio | |
| 383 | MPSC has low prio | |
| 384 | pci has low prio 1 and 2 | |
| 385 | cpu has high prio | |
| 386 | Data DQS pins == eight (DQS[7:0] foe x8 and x16 devices | |
| 387 | ECC disable | |
| 388 | non registered DRAM */ | |
| 389 | /* 31:26 25:22 21:20 19 18 17 16 */ | |
| bfc81252 | 390 | /* 100001 0000 010 0 0 0 0 */ |
| a20b27a3 SR |
391 | /* refresh_count=0x400 |
| 392 | phisical interleaving disable | |
| 393 | virtual interleaving enable */ | |
| 394 | /* 15 14 13:0 */ | |
| bfc81252 | 395 | /* 0 1 0x400 */ |
| a20b27a3 SR |
396 | # define CFG_SDRAM_CONFIG 0x58200400 /* 0x1400 copied from Dink32 bzw. VxWorks*/ |
| 397 | ||
| 398 | ||
| 399 | /*----------------------------------------------------------------------- | |
| 400 | * PCI stuff | |
| 401 | *----------------------------------------------------------------------- | |
| 402 | */ | |
| 403 | ||
| bfc81252 WD |
404 | #define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ |
| 405 | #define PCI_HOST_FORCE 1 /* configure as pci host */ | |
| 406 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ | |
| a20b27a3 | 407 | |
| bfc81252 WD |
408 | #define CONFIG_PCI /* include pci support */ |
| 409 | #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ | |
| 410 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
| 411 | #define CONFIG_PCI_SCAN_SHOW /* show devices on bus */ | |
| a20b27a3 SR |
412 | |
| 413 | /* PCI MEMORY MAP section */ | |
| 414 | #define CFG_PCI0_MEM_BASE 0x80000000 | |
| 415 | #define CFG_PCI0_MEM_SIZE _128M | |
| 416 | #define CFG_PCI1_MEM_BASE 0x88000000 | |
| 417 | #define CFG_PCI1_MEM_SIZE _128M | |
| 418 | ||
| 419 | #define CFG_PCI0_0_MEM_SPACE (CFG_PCI0_MEM_BASE) | |
| 420 | #define CFG_PCI1_0_MEM_SPACE (CFG_PCI1_MEM_BASE) | |
| 421 | ||
| a20b27a3 SR |
422 | /* PCI I/O MAP section */ |
| 423 | #define CFG_PCI0_IO_BASE 0xfa000000 | |
| 424 | #define CFG_PCI0_IO_SIZE _16M | |
| 425 | #define CFG_PCI1_IO_BASE 0xfb000000 | |
| 426 | #define CFG_PCI1_IO_SIZE _16M | |
| 427 | ||
| 428 | #define CFG_PCI0_IO_SPACE (CFG_PCI0_IO_BASE) | |
| 429 | #define CFG_PCI0_IO_SPACE_PCI 0x00000000 | |
| 430 | #define CFG_PCI1_IO_SPACE (CFG_PCI1_IO_BASE) | |
| 431 | #define CFG_PCI1_IO_SPACE_PCI 0x00000000 | |
| 432 | ||
| a7b9fb91 SR |
433 | #define CFG_ISA_IO_BASE_ADDRESS (CFG_PCI0_IO_BASE) |
| 434 | ||
| a20b27a3 SR |
435 | #if defined (CONFIG_750CX) |
| 436 | #define CFG_PCI_IDSEL 0x0 | |
| 437 | #else | |
| 438 | #define CFG_PCI_IDSEL 0x30 | |
| 439 | #endif | |
| 440 | ||
| 441 | /*----------------------------------------------------------------------- | |
| 442 | * IDE/ATA stuff | |
| 443 | *----------------------------------------------------------------------- | |
| 444 | */ | |
| bfc81252 WD |
445 | #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ |
| 446 | #undef CONFIG_IDE_LED /* no led for ide supported */ | |
| 447 | #define CONFIG_IDE_RESET /* no reset for ide supported */ | |
| 448 | #define CONFIG_IDE_PREINIT /* check for units */ | |
| a20b27a3 | 449 | |
| bfc81252 WD |
450 | #define CFG_IDE_MAXBUS 2 /* max. 1 IDE busses */ |
| 451 | #define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 1 drives per IDE bus */ | |
| a20b27a3 | 452 | |
| bfc81252 WD |
453 | #define CFG_ATA_BASE_ADDR 0 |
| 454 | #define CFG_ATA_IDE0_OFFSET 0 | |
| 455 | #define CFG_ATA_IDE1_OFFSET 0 | |
| a20b27a3 | 456 | |
| bfc81252 WD |
457 | #define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ |
| 458 | #define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ | |
| 459 | #define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ | |
| a20b27a3 SR |
460 | |
| 461 | ||
| 462 | /*---------------------------------------------------------------------- | |
| 463 | * Initial BAT mappings | |
| 464 | */ | |
| 465 | ||
| 466 | /* NOTES: | |
| 467 | * 1) GUARDED and WRITE_THRU not allowed in IBATS | |
| 468 | * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT | |
| 469 | */ | |
| 470 | ||
| 471 | /* SDRAM */ | |
| 472 | #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) | |
| 473 | #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 474 | #define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 475 | #define CFG_DBAT0U CFG_IBAT0U | |
| 476 | ||
| 477 | /* init ram */ | |
| 478 | #define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) | |
| 479 | #define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP) | |
| 480 | #define CFG_DBAT1L CFG_IBAT1L | |
| 481 | #define CFG_DBAT1U CFG_IBAT1U | |
| 482 | ||
| 483 | /* PCI0, PCI1 in one BAT */ | |
| 484 | #define CFG_IBAT2L BATL_NO_ACCESS | |
| 485 | #define CFG_IBAT2U CFG_DBAT2U | |
| 486 | #define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) | |
| 487 | #define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 488 | ||
| 489 | /* GT regs, bootrom, all the devices, PCI I/O */ | |
| 490 | #define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) | |
| 491 | #define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) | |
| 492 | #define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) | |
| 493 | #define CFG_DBAT3U CFG_IBAT3U | |
| 494 | ||
| 495 | /* | |
| 496 | * 750FX IBAT and DBAT pairs (To_do: define regins for I(D)BAT4 - I(D)BAT7) | |
| 497 | * IBAT4 and DBAT4 | |
| 498 | * FIXME: ingo disable BATs for Linux Kernel | |
| 499 | */ | |
| 500 | #undef SETUP_HIGH_BATS_FX750 /* don't initialize BATS 4-7 */ | |
| 501 | /*#define SETUP_HIGH_BATS_FX750*/ /* initialize BATS 4-7 */ | |
| 502 | ||
| 503 | #ifdef SETUP_HIGH_BATS_FX750 | |
| 504 | #define CFG_IBAT4L (CFG_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) | |
| 505 | #define CFG_IBAT4U (CFG_SDRAM1_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 506 | #define CFG_DBAT4L (CFG_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 507 | #define CFG_DBAT4U CFG_IBAT4U | |
| 508 | ||
| 509 | /* IBAT5 and DBAT5 */ | |
| 510 | #define CFG_IBAT5L (CFG_SDRAM2_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) | |
| 511 | #define CFG_IBAT5U (CFG_SDRAM2_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 512 | #define CFG_DBAT5L (CFG_SDRAM2_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 513 | #define CFG_DBAT5U CFG_IBAT5U | |
| 514 | ||
| 515 | /* IBAT6 and DBAT6 */ | |
| 516 | #define CFG_IBAT6L (CFG_SDRAM3_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) | |
| 517 | #define CFG_IBAT6U (CFG_SDRAM3_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 518 | #define CFG_DBAT6L (CFG_SDRAM3_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 519 | #define CFG_DBAT6U CFG_IBAT6U | |
| 520 | ||
| 521 | /* IBAT7 and DBAT7 */ | |
| 522 | #define CFG_IBAT7L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) | |
| 523 | #define CFG_IBAT7U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 524 | #define CFG_DBAT7L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 525 | #define CFG_DBAT7U CFG_IBAT7U | |
| 526 | ||
| 527 | #else /* set em out of range for Linux !!!!!!!!!!! */ | |
| 528 | #define CFG_IBAT4L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) | |
| 529 | #define CFG_IBAT4U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 530 | #define CFG_DBAT4L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 531 | #define CFG_DBAT4U CFG_IBAT4U | |
| 532 | ||
| 533 | /* IBAT5 and DBAT5 */ | |
| 534 | #define CFG_IBAT5L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) | |
| 535 | #define CFG_IBAT5U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 536 | #define CFG_DBAT5L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 537 | #define CFG_DBAT5U CFG_IBAT4U | |
| 538 | ||
| 539 | /* IBAT6 and DBAT6 */ | |
| 540 | #define CFG_IBAT6L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) | |
| 541 | #define CFG_IBAT6U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 542 | #define CFG_DBAT6L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 543 | #define CFG_DBAT6U CFG_IBAT4U | |
| 544 | ||
| 545 | /* IBAT7 and DBAT7 */ | |
| 546 | #define CFG_IBAT7L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) | |
| 547 | #define CFG_IBAT7U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 548 | #define CFG_DBAT7L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 549 | #define CFG_DBAT7U CFG_IBAT4U | |
| 550 | ||
| 551 | #endif | |
| 552 | /* FIXME: ingo end: disable BATs for Linux Kernel */ | |
| 553 | ||
| 554 | /* I2C addresses for the two DIMM SPD chips */ | |
| 555 | #define DIMM0_I2C_ADDR 0x51 | |
| 556 | #define DIMM1_I2C_ADDR 0x52 | |
| 557 | ||
| 558 | /* | |
| 559 | * For booting Linux, the board info and command line data | |
| 560 | * have to be in the first 8 MB of memory, since this is | |
| 561 | * the maximum mapped by the Linux kernel during initialization. | |
| 562 | */ | |
| bfc81252 | 563 | #define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ |
| a20b27a3 SR |
564 | |
| 565 | /*----------------------------------------------------------------------- | |
| 566 | * FLASH organization | |
| 567 | */ | |
| 568 | #define CFG_BOOT_FLASH_WIDTH 2 /* 16 bit */ | |
| 569 | ||
| 570 | #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ | |
| 571 | #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
| 572 | #define CFG_FLASH_LOCK_TOUT 500 /* Timeout for Flash Lock (in ms) */ | |
| 573 | ||
| 574 | #if 0 | |
| 7d9b5bae | 575 | #define CFG_ENV_IS_IN_FLASH |
| bfc81252 | 576 | #define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ |
| a20b27a3 SR |
577 | #define CFG_ENV_SECT_SIZE 0x10000 |
| 578 | #define CFG_ENV_ADDR 0xFFF78000 /* Marvell 8-Bit Bootflash last sector */ | |
| bfc81252 | 579 | /* #define CFG_ENV_ADDR (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE) */ |
| a20b27a3 SR |
580 | #endif |
| 581 | ||
| bb1f8b4f | 582 | #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
| a20b27a3 SR |
583 | #define CFG_EEPROM_PAGE_WRITE_BITS 5 |
| 584 | #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 | |
| bfc81252 | 585 | #define CFG_I2C_EEPROM_ADDR 0x050 |
| a20b27a3 SR |
586 | #define CFG_ENV_OFFSET 0x200 /* environment starts at the beginning of the EEPROM */ |
| 587 | #define CFG_ENV_SIZE 0x600 /* 2048 bytes may be used for env vars*/ | |
| 588 | ||
| 589 | #define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */ | |
| 590 | #define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */ | |
| bfc81252 | 591 | #define CFG_VXWORKS_MAC_PTR (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-0x40) |
| a20b27a3 SR |
592 | |
| 593 | /*----------------------------------------------------------------------- | |
| 594 | * Cache Configuration | |
| 595 | */ | |
| 596 | #define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ | |
| 49cf7e8e | 597 | #if defined(CONFIG_CMD_KGDB) |
| a20b27a3 SR |
598 | #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
| 599 | #endif | |
| 600 | ||
| 601 | /*----------------------------------------------------------------------- | |
| 602 | * L2CR setup -- make sure this is right for your board! | |
| 603 | * look in include/mpc74xx.h for the defines used here | |
| 604 | */ | |
| 605 | ||
| 606 | /*#define CFG_L2*/ | |
| 607 | #undef CFG_L2 | |
| 608 | ||
| 609 | /* #ifdef CONFIG_750CX*/ | |
| 610 | #if defined (CONFIG_750CX) || defined (CONFIG_750FX) | |
| 611 | #define L2_INIT 0 | |
| 612 | #else | |
| bfc81252 | 613 | #define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ |
| a20b27a3 SR |
614 | L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) |
| 615 | #endif | |
| 616 | ||
| 617 | #define L2_ENABLE (L2_INIT | L2CR_L2E) | |
| 618 | ||
| 619 | /* | |
| 620 | * Internal Definitions | |
| 621 | * | |
| 622 | * Boot Flags | |
| 623 | */ | |
| bfc81252 | 624 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
| a20b27a3 SR |
625 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ |
| 626 | ||
| bfc81252 | 627 | #define CFG_BOARD_ASM_INIT 1 |
| a20b27a3 SR |
628 | |
| 629 | #endif /* __CONFIG_H */ |