[people/ms/u-boot.git] / include / configs / CU824.h

/*
 * (C) Copyright 2001-2005
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 *
 * Configuration settings for the CU824 board.
 *
 */

/* ------------------------------------------------------------------------- */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC824X		1
#define CONFIG_MPC8240		1
#define CONFIG_CU824		1


#define CONFIG_CONS_INDEX	1
#define CONFIG_BAUDRATE		9600
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

#define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"

#define CONFIG_BOOTCOMMAND	"bootm FE020000"	/* autoboot command	*/
#define CONFIG_BOOTDELAY	5

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE


#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_BEDBUG
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PCI
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP


/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/

#if 1
#define	CONFIG_SYS_HUSH_PARSER		1	/* use "hush" command parser	*/
#endif
#ifdef	CONFIG_SYS_HUSH_PARSER
#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
#endif

/* Print Buffer Size
 */
#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)

#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
#define CONFIG_SYS_LOAD_ADDR	0x00100000	/* Default load address		*/

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE	    0x00000000
#define CONFIG_SYS_FLASH_BASE	    0xFF000000

#define CONFIG_SYS_RESET_ADDRESS   0xFFF00100

#define CONFIG_SYS_EUMB_ADDR	    0xFCE00000

#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE

#define CONFIG_SYS_MONITOR_LEN	    (256 << 10) /* Reserve 256 kB for Monitor	*/
#define CONFIG_SYS_MALLOC_LEN	    (128 << 10) /* Reserve 128 kB for malloc()	*/

#define CONFIG_SYS_MEMTEST_START   0x00004000	/* memtest works on		*/
#define CONFIG_SYS_MEMTEST_END	    0x02000000	/* 0 ... 32 MB in DRAM		*/

	/* Maximum amount of RAM.
	 */
#define CONFIG_SYS_MAX_RAM_SIZE    0x10000000


#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
#undef CONFIG_SYS_RAMBOOT
#else
#define CONFIG_SYS_RAMBOOT
#endif


/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area
 */

	/* Size in bytes reserved for initial data
	 */
#define CONFIG_SYS_GBL_DATA_SIZE    128

#define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
#define CONFIG_SYS_INIT_RAM_END      0x1000
#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)

/*
 * NS16550 Configuration
 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL

#define CONFIG_SYS_NS16550_REG_SIZE	4

#define CONFIG_SYS_NS16550_CLK		(14745600 / 2)

#define CONFIG_SYS_NS16550_COM1	0xFE800080
#define CONFIG_SYS_NS16550_COM2	0xFE8000C0

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 * For the detail description refer to the MPC8240 user's manual.
 */

#define CONFIG_SYS_CLK_FREQ  33000000
#define CONFIG_SYS_HZ		     1000

	/* Bit-field values for MCCR1.
	 */
#define CONFIG_SYS_ROMNAL	    0
#define CONFIG_SYS_ROMFAL	    7

	/* Bit-field values for MCCR2.
	 */
#define CONFIG_SYS_REFINT	    430	    /* Refresh interval			*/

	/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
	 */
#define CONFIG_SYS_BSTOPRE	    192

	/* Bit-field values for MCCR3.
	 */
#define CONFIG_SYS_REFREC	    2	    /* Refresh to activate interval	*/
#define CONFIG_SYS_RDLAT	    3	    /* Data latancy from read command	*/

	/* Bit-field values for MCCR4.
	 */
#define CONFIG_SYS_PRETOACT	    2	    /* Precharge to activate interval	*/
#define CONFIG_SYS_ACTTOPRE	    5	    /* Activate to Precharge interval	*/
#define CONFIG_SYS_SDMODE_CAS_LAT  2	    /* SDMODE CAS latancy		*/
#define CONFIG_SYS_SDMODE_WRAP	    0	    /* SDMODE wrap type			*/
#define CONFIG_SYS_SDMODE_BURSTLEN 2	    /* SDMODE Burst length		*/
#define CONFIG_SYS_ACTORW	    2
#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1

/* Memory bank settings.
 * Only bits 20-29 are actually used from these vales to set the
 * start/end addresses. The upper two bits will always be 0, and the lower
 * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
 * address. Refer to the MPC8240 book.
 */

#define CONFIG_SYS_BANK0_START	    0x00000000
#define CONFIG_SYS_BANK0_END	    (CONFIG_SYS_MAX_RAM_SIZE - 1)
#define CONFIG_SYS_BANK0_ENABLE    1
#define CONFIG_SYS_BANK1_START	    0x3ff00000
#define CONFIG_SYS_BANK1_END	    0x3fffffff
#define CONFIG_SYS_BANK1_ENABLE    0
#define CONFIG_SYS_BANK2_START	    0x3ff00000
#define CONFIG_SYS_BANK2_END	    0x3fffffff
#define CONFIG_SYS_BANK2_ENABLE    0
#define CONFIG_SYS_BANK3_START	    0x3ff00000
#define CONFIG_SYS_BANK3_END	    0x3fffffff
#define CONFIG_SYS_BANK3_ENABLE    0
#define CONFIG_SYS_BANK4_START	    0x3ff00000
#define CONFIG_SYS_BANK4_END	    0x3fffffff
#define CONFIG_SYS_BANK4_ENABLE    0
#define CONFIG_SYS_BANK5_START	    0x3ff00000
#define CONFIG_SYS_BANK5_END	    0x3fffffff
#define CONFIG_SYS_BANK5_ENABLE    0
#define CONFIG_SYS_BANK6_START	    0x3ff00000
#define CONFIG_SYS_BANK6_END	    0x3fffffff
#define CONFIG_SYS_BANK6_ENABLE    0
#define CONFIG_SYS_BANK7_START	    0x3ff00000
#define CONFIG_SYS_BANK7_END	    0x3fffffff
#define CONFIG_SYS_BANK7_ENABLE    0

#define CONFIG_SYS_ODCR	    0xff

#define CONFIG_SYS_IBAT0L  (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U  (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)

#define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)

#define CONFIG_SYS_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)

#define CONFIG_SYS_IBAT3L  (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT3U  (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP)

#define CONFIG_SYS_DBAT0L  CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U  CONFIG_SYS_IBAT0U
#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
#define CONFIG_SYS_DBAT2L  CONFIG_SYS_IBAT2L
#define CONFIG_SYS_DBAT2U  CONFIG_SYS_IBAT2U
#define CONFIG_SYS_DBAT3L  CONFIG_SYS_IBAT3L
#define CONFIG_SYS_DBAT3U  CONFIG_SYS_IBAT3U

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	    (8 << 20)	/* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* Max number of flash banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	39	/* Max number of sectors in one bank	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

	/* Warining: environment is not EMBEDDED in the U-Boot code.
	 * It's stored in flash separately.
	 */
#define CONFIG_ENV_IS_IN_FLASH	    1
#if 0
#define CONFIG_ENV_ADDR		0xFF008000
#define CONFIG_ENV_SIZE		0x8000	/* Size of the Environment Sector	*/
#else
#define CONFIG_ENV_ADDR		0xFFFC0000
#define CONFIG_ENV_SIZE		0x4000	/* Size of the Environment		*/
#define CONFIG_ENV_OFFSET		0	/* starting right at the beginning	*/
#define CONFIG_ENV_SECT_SIZE	0x40000 /* Size of the Environment Sector	*/
#endif

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	32
#if defined(CONFIG_CMD_KGDB)
#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
#endif

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM		0x02	/* Software reboot			*/

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
#define CONFIG_PCI			/* include pci support			*/
#undef CONFIG_PCI_PNP

#define CONFIG_NET_MULTI		/* Multi ethernet cards support		*/

#define CONFIG_TULIP
#define CONFIG_TULIP_USE_IO

#define CONFIG_SYS_ETH_DEV_FN	     0x7800
#define CONFIG_SYS_ETH_IOBASE	     0x00104000

#define CONFIG_EEPRO100
#define CONFIG_SYS_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
#define PCI_ENET0_IOADDR	0x00104000
#define PCI_ENET0_MEMADDR	0x80000000
#endif	/* __CONFIG_H */
Commit	Line	Data
c609719b	1	/*
414eec35	2	* (C) Copyright 2001-2005
c609719b WD	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	*
	26	* Configuration settings for the CU824 board.
	27	*
	28	*/
	29
	30	/* ------------------------------------------------------------------------- */
	31
	32	/*
	33	* board/config.h - configuration options, board specific
	34	*/
	35
	36	#ifndef __CONFIG_H
	37	#define __CONFIG_H
	38
	39	/*
	40	* High Level Configuration Options
	41	* (easy to change)
	42	*/
	43
	44	#define CONFIG_MPC824X 1
	45	#define CONFIG_MPC8240 1
	46	#define CONFIG_CU824 1
	47
	48
	49	#define CONFIG_CONS_INDEX 1
	50	#define CONFIG_BAUDRATE 9600
6d0f6bcf	51	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
c609719b	52
32bf3d14	53	#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
c609719b WD	54
	55	#define CONFIG_BOOTCOMMAND "bootm FE020000" /* autoboot command */
	56	#define CONFIG_BOOTDELAY 5
	57
5d2ebe1b JL	58	/*
	59	* BOOTP options
	60	*/
	61	#define CONFIG_BOOTP_SUBNETMASK
	62	#define CONFIG_BOOTP_GATEWAY
	63	#define CONFIG_BOOTP_HOSTNAME
	64	#define CONFIG_BOOTP_BOOTPATH
	65	#define CONFIG_BOOTP_BOOTFILESIZE
	66
c609719b	67
414eec35 WD	68	#define CONFIG_TIMESTAMP /* Print image info with timestamp */
414eec35 WD	69
49cf7e8e JL	70
	71	/*
	72	* Command line configuration.
c609719b	73	*/
49cf7e8e JL	74	#include <config_cmd_default.h>
49cf7e8e JL	75
5728be38	76	#define CONFIG_CMD_BEDBUG
49cf7e8e JL	77	#define CONFIG_CMD_DHCP
	78	#define CONFIG_CMD_PCI
	79	#define CONFIG_CMD_NFS
	80	#define CONFIG_CMD_SNTP
c609719b WD	81
	82
	83	/*
	84	* Miscellaneous configurable options
	85	*/
6d0f6bcf JCPV	86	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	87	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
	88	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
c609719b WD	89
c609719b WD	90	#if 1
6d0f6bcf	91	#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
c609719b	92	#endif
6d0f6bcf JCPV	93	#ifdef CONFIG_SYS_HUSH_PARSER
6d0f6bcf JCPV	94	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
c609719b WD	95	#endif
	96
	97	/* Print Buffer Size
	98	*/
6d0f6bcf	99	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
c609719b	100
6d0f6bcf JCPV	101	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	102	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
	103	#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */
c609719b WD	104
	105	/*-----------------------------------------------------------------------
	106	* Start addresses for the final memory configuration
	107	* (Set up by the startup code)
6d0f6bcf	108	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
c609719b	109	*/
6d0f6bcf JCPV	110	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	111	#define CONFIG_SYS_FLASH_BASE 0xFF000000
c609719b	112
6d0f6bcf	113	#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
c609719b	114
6d0f6bcf	115	#define CONFIG_SYS_EUMB_ADDR 0xFCE00000
c609719b	116
14d0a02a	117	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
c609719b	118
6d0f6bcf JCPV	119	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
6d0f6bcf JCPV	120	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
c609719b	121
6d0f6bcf JCPV	122	#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */
6d0f6bcf JCPV	123	#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
c609719b WD	124
	125	/* Maximum amount of RAM.
	126	*/
6d0f6bcf	127	#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000
c609719b WD	128
c609719b WD	129
6d0f6bcf JCPV	130	#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
6d0f6bcf JCPV	131	#undef CONFIG_SYS_RAMBOOT
c609719b	132	#else
6d0f6bcf	133	#define CONFIG_SYS_RAMBOOT
c609719b WD	134	#endif
	135
	136
	137	/*-----------------------------------------------------------------------
	138	* Definitions for initial stack pointer and data area
	139	*/
	140
	141	/* Size in bytes reserved for initial data
	142	*/
6d0f6bcf	143	#define CONFIG_SYS_GBL_DATA_SIZE 128
c609719b	144
6d0f6bcf JCPV	145	#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
	146	#define CONFIG_SYS_INIT_RAM_END 0x1000
	147	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
c609719b WD	148
	149	/*
	150	* NS16550 Configuration
	151	*/
6d0f6bcf JCPV	152	#define CONFIG_SYS_NS16550
6d0f6bcf JCPV	153	#define CONFIG_SYS_NS16550_SERIAL
c609719b	154
6d0f6bcf	155	#define CONFIG_SYS_NS16550_REG_SIZE 4
c609719b	156
6d0f6bcf	157	#define CONFIG_SYS_NS16550_CLK (14745600 / 2)
c609719b	158
6d0f6bcf JCPV	159	#define CONFIG_SYS_NS16550_COM1 0xFE800080
6d0f6bcf JCPV	160	#define CONFIG_SYS_NS16550_COM2 0xFE8000C0
c609719b WD	161
	162	/*
	163	* Low Level Configuration Settings
	164	* (address mappings, register initial values, etc.)
	165	* You should know what you are doing if you make changes here.
	166	* For the detail description refer to the MPC8240 user's manual.
	167	*/
	168
	169	#define CONFIG_SYS_CLK_FREQ 33000000
6d0f6bcf	170	#define CONFIG_SYS_HZ 1000
c609719b WD	171
	172	/* Bit-field values for MCCR1.
	173	*/
6d0f6bcf JCPV	174	#define CONFIG_SYS_ROMNAL 0
6d0f6bcf JCPV	175	#define CONFIG_SYS_ROMFAL 7
c609719b WD	176
	177	/* Bit-field values for MCCR2.
	178	*/
6d0f6bcf	179	#define CONFIG_SYS_REFINT 430 /* Refresh interval */
c609719b WD	180
	181	/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
	182	*/
6d0f6bcf	183	#define CONFIG_SYS_BSTOPRE 192
c609719b WD	184
	185	/* Bit-field values for MCCR3.
	186	*/
6d0f6bcf JCPV	187	#define CONFIG_SYS_REFREC 2 /* Refresh to activate interval */
6d0f6bcf JCPV	188	#define CONFIG_SYS_RDLAT 3 /* Data latancy from read command */
c609719b WD	189
	190	/* Bit-field values for MCCR4.
	191	*/
6d0f6bcf JCPV	192	#define CONFIG_SYS_PRETOACT 2 /* Precharge to activate interval */
	193	#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */
	194	#define CONFIG_SYS_SDMODE_CAS_LAT 2 /* SDMODE CAS latancy */
	195	#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
	196	#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length */
	197	#define CONFIG_SYS_ACTORW 2
	198	#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
c609719b WD	199
	200	/* Memory bank settings.
	201	* Only bits 20-29 are actually used from these vales to set the
	202	* start/end addresses. The upper two bits will always be 0, and the lower
	203	* 20 bits will be 0x00000 for a start address, or 0xfffff for an end
	204	* address. Refer to the MPC8240 book.
	205	*/
	206
6d0f6bcf JCPV	207	#define CONFIG_SYS_BANK0_START 0x00000000
	208	#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
	209	#define CONFIG_SYS_BANK0_ENABLE 1
	210	#define CONFIG_SYS_BANK1_START 0x3ff00000
	211	#define CONFIG_SYS_BANK1_END 0x3fffffff
	212	#define CONFIG_SYS_BANK1_ENABLE 0
	213	#define CONFIG_SYS_BANK2_START 0x3ff00000
	214	#define CONFIG_SYS_BANK2_END 0x3fffffff
	215	#define CONFIG_SYS_BANK2_ENABLE 0
	216	#define CONFIG_SYS_BANK3_START 0x3ff00000
	217	#define CONFIG_SYS_BANK3_END 0x3fffffff
	218	#define CONFIG_SYS_BANK3_ENABLE 0
	219	#define CONFIG_SYS_BANK4_START 0x3ff00000
	220	#define CONFIG_SYS_BANK4_END 0x3fffffff
	221	#define CONFIG_SYS_BANK4_ENABLE 0
	222	#define CONFIG_SYS_BANK5_START 0x3ff00000
	223	#define CONFIG_SYS_BANK5_END 0x3fffffff
	224	#define CONFIG_SYS_BANK5_ENABLE 0
	225	#define CONFIG_SYS_BANK6_START 0x3ff00000
	226	#define CONFIG_SYS_BANK6_END 0x3fffffff
	227	#define CONFIG_SYS_BANK6_ENABLE 0
	228	#define CONFIG_SYS_BANK7_START 0x3ff00000
	229	#define CONFIG_SYS_BANK7_END 0x3fffffff
	230	#define CONFIG_SYS_BANK7_ENABLE 0
	231
	232	#define CONFIG_SYS_ODCR 0xff
	233
	234	#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \| BATL_PP_10 \| BATL_MEMCOHERENCE)
	235	#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	236
	237	#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR \| BATL_PP_10 \| BATL_MEMCOHERENCE)
	238	#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR \| BATU_BL_128K \| BATU_VS \| BATU_VP)
	239
	240	#define CONFIG_SYS_IBAT2L (0x80000000 \| BATL_PP_10 \| BATL_CACHEINHIBIT)
	241	#define CONFIG_SYS_IBAT2U (0x80000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	242
	243	#define CONFIG_SYS_IBAT3L (0xFC000000 \| BATL_PP_10 \| BATL_CACHEINHIBIT)
	244	#define CONFIG_SYS_IBAT3U (0xFC000000 \| BATU_BL_64M \| BATU_VS \| BATU_VP)
	245
	246	#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
	247	#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
	248	#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
	249	#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
	250	#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
	251	#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
	252	#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
	253	#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
c609719b WD	254
	255	/*
	256	* For booting Linux, the board info and command line data
	257	* have to be in the first 8 MB of memory, since this is
	258	* the maximum mapped by the Linux kernel during initialization.
	259	*/
6d0f6bcf	260	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
c609719b WD	261
	262	/*-----------------------------------------------------------------------
	263	* FLASH organization
	264	*/
6d0f6bcf JCPV	265	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* Max number of flash banks */
6d0f6bcf JCPV	266	#define CONFIG_SYS_MAX_FLASH_SECT 39 /* Max number of sectors in one bank */
c609719b	267
6d0f6bcf JCPV	268	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	269	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
c609719b WD	270
	271	/* Warining: environment is not EMBEDDED in the U-Boot code.
	272	* It's stored in flash separately.
	273	*/
5a1aceb0	274	#define CONFIG_ENV_IS_IN_FLASH 1
c609719b	275	#if 0
0e8d1586 JCPV	276	#define CONFIG_ENV_ADDR 0xFF008000
0e8d1586 JCPV	277	#define CONFIG_ENV_SIZE 0x8000 /* Size of the Environment Sector */
c609719b	278	#else
0e8d1586 JCPV	279	#define CONFIG_ENV_ADDR 0xFFFC0000
	280	#define CONFIG_ENV_SIZE 0x4000 /* Size of the Environment */
	281	#define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */
	282	#define CONFIG_ENV_SECT_SIZE 0x40000 /* Size of the Environment Sector */
c609719b WD	283	#endif
	284
	285	/*-----------------------------------------------------------------------
	286	* Cache Configuration
	287	*/
6d0f6bcf	288	#define CONFIG_SYS_CACHELINE_SIZE 32
49cf7e8e	289	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	290	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
c609719b WD	291	#endif
	292
	293	/*
	294	* Internal Definitions
	295	*
	296	* Boot Flags
	297	*/
	298	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	299	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	300
	301	/*-----------------------------------------------------------------------
	302	* PCI stuff
	303	*-----------------------------------------------------------------------
	304	*/
	305	#define CONFIG_PCI /* include pci support */
	306	#undef CONFIG_PCI_PNP
	307
53677ef1	308	#define CONFIG_NET_MULTI /* Multi ethernet cards support */
c609719b WD	309
	310	#define CONFIG_TULIP
	311	#define CONFIG_TULIP_USE_IO
	312
6d0f6bcf JCPV	313	#define CONFIG_SYS_ETH_DEV_FN 0x7800
6d0f6bcf JCPV	314	#define CONFIG_SYS_ETH_IOBASE 0x00104000
c609719b	315
3bac3513	316	#define CONFIG_EEPRO100
6d0f6bcf	317	#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
3bac3513 WD	318	#define PCI_ENET0_IOADDR 0x00104000
3bac3513 WD	319	#define PCI_ENET0_MEMADDR 0x80000000
c609719b	320	#endif /* __CONFIG_H */