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Commit | Line | Data |
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c609719b | 1 | /* |
414eec35 | 2 | * (C) Copyright 2001-2005 |
c609719b WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
c609719b WD |
6 | */ |
7 | ||
8 | /* | |
9 | * | |
10 | * Configuration settings for the CU824 board. | |
11 | * | |
12 | */ | |
13 | ||
14 | /* ------------------------------------------------------------------------- */ | |
15 | ||
16 | /* | |
17 | * board/config.h - configuration options, board specific | |
18 | */ | |
19 | ||
20 | #ifndef __CONFIG_H | |
21 | #define __CONFIG_H | |
22 | ||
23 | /* | |
24 | * High Level Configuration Options | |
25 | * (easy to change) | |
26 | */ | |
27 | ||
c609719b WD |
28 | #define CONFIG_MPC8240 1 |
29 | #define CONFIG_CU824 1 | |
30 | ||
2ae18241 | 31 | #define CONFIG_SYS_TEXT_BASE 0xFFF00000 |
c609719b WD |
32 | |
33 | #define CONFIG_CONS_INDEX 1 | |
34 | #define CONFIG_BAUDRATE 9600 | |
c609719b | 35 | |
32bf3d14 | 36 | #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" |
c609719b WD |
37 | |
38 | #define CONFIG_BOOTCOMMAND "bootm FE020000" /* autoboot command */ | |
39 | #define CONFIG_BOOTDELAY 5 | |
40 | ||
5d2ebe1b JL |
41 | /* |
42 | * BOOTP options | |
43 | */ | |
44 | #define CONFIG_BOOTP_SUBNETMASK | |
45 | #define CONFIG_BOOTP_GATEWAY | |
46 | #define CONFIG_BOOTP_HOSTNAME | |
47 | #define CONFIG_BOOTP_BOOTPATH | |
48 | #define CONFIG_BOOTP_BOOTFILESIZE | |
49 | ||
c609719b | 50 | |
414eec35 WD |
51 | #define CONFIG_TIMESTAMP /* Print image info with timestamp */ |
52 | ||
49cf7e8e JL |
53 | |
54 | /* | |
55 | * Command line configuration. | |
c609719b | 56 | */ |
49cf7e8e JL |
57 | #include <config_cmd_default.h> |
58 | ||
5728be38 | 59 | #define CONFIG_CMD_BEDBUG |
49cf7e8e JL |
60 | #define CONFIG_CMD_DHCP |
61 | #define CONFIG_CMD_PCI | |
62 | #define CONFIG_CMD_NFS | |
63 | #define CONFIG_CMD_SNTP | |
c609719b WD |
64 | |
65 | ||
66 | /* | |
67 | * Miscellaneous configurable options | |
68 | */ | |
6d0f6bcf | 69 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
6d0f6bcf | 70 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
c609719b WD |
71 | |
72 | #if 1 | |
6d0f6bcf | 73 | #define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ |
c609719b | 74 | #endif |
c609719b WD |
75 | |
76 | /* Print Buffer Size | |
77 | */ | |
6d0f6bcf | 78 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) |
c609719b | 79 | |
6d0f6bcf JCPV |
80 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
81 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
82 | #define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */ | |
c609719b WD |
83 | |
84 | /*----------------------------------------------------------------------- | |
85 | * Start addresses for the final memory configuration | |
86 | * (Set up by the startup code) | |
6d0f6bcf | 87 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
c609719b | 88 | */ |
6d0f6bcf JCPV |
89 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
90 | #define CONFIG_SYS_FLASH_BASE 0xFF000000 | |
c609719b | 91 | |
6d0f6bcf | 92 | #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 |
c609719b | 93 | |
6d0f6bcf | 94 | #define CONFIG_SYS_EUMB_ADDR 0xFCE00000 |
c609719b | 95 | |
14d0a02a | 96 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
c609719b | 97 | |
6d0f6bcf JCPV |
98 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
99 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
c609719b | 100 | |
6d0f6bcf JCPV |
101 | #define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */ |
102 | #define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ | |
c609719b WD |
103 | |
104 | /* Maximum amount of RAM. | |
105 | */ | |
6d0f6bcf | 106 | #define CONFIG_SYS_MAX_RAM_SIZE 0x10000000 |
c609719b WD |
107 | |
108 | ||
6d0f6bcf JCPV |
109 | #if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE |
110 | #undef CONFIG_SYS_RAMBOOT | |
c609719b | 111 | #else |
6d0f6bcf | 112 | #define CONFIG_SYS_RAMBOOT |
c609719b WD |
113 | #endif |
114 | ||
115 | ||
116 | /*----------------------------------------------------------------------- | |
117 | * Definitions for initial stack pointer and data area | |
118 | */ | |
119 | ||
6d0f6bcf | 120 | #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 |
553f0982 | 121 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 |
25ddd1fb | 122 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
c609719b WD |
123 | |
124 | /* | |
125 | * NS16550 Configuration | |
126 | */ | |
6d0f6bcf JCPV |
127 | #define CONFIG_SYS_NS16550 |
128 | #define CONFIG_SYS_NS16550_SERIAL | |
c609719b | 129 | |
6d0f6bcf | 130 | #define CONFIG_SYS_NS16550_REG_SIZE 4 |
c609719b | 131 | |
6d0f6bcf | 132 | #define CONFIG_SYS_NS16550_CLK (14745600 / 2) |
c609719b | 133 | |
6d0f6bcf JCPV |
134 | #define CONFIG_SYS_NS16550_COM1 0xFE800080 |
135 | #define CONFIG_SYS_NS16550_COM2 0xFE8000C0 | |
c609719b WD |
136 | |
137 | /* | |
138 | * Low Level Configuration Settings | |
139 | * (address mappings, register initial values, etc.) | |
140 | * You should know what you are doing if you make changes here. | |
141 | * For the detail description refer to the MPC8240 user's manual. | |
142 | */ | |
143 | ||
144 | #define CONFIG_SYS_CLK_FREQ 33000000 | |
c609719b WD |
145 | |
146 | /* Bit-field values for MCCR1. | |
147 | */ | |
6d0f6bcf JCPV |
148 | #define CONFIG_SYS_ROMNAL 0 |
149 | #define CONFIG_SYS_ROMFAL 7 | |
c609719b WD |
150 | |
151 | /* Bit-field values for MCCR2. | |
152 | */ | |
6d0f6bcf | 153 | #define CONFIG_SYS_REFINT 430 /* Refresh interval */ |
c609719b WD |
154 | |
155 | /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. | |
156 | */ | |
6d0f6bcf | 157 | #define CONFIG_SYS_BSTOPRE 192 |
c609719b WD |
158 | |
159 | /* Bit-field values for MCCR3. | |
160 | */ | |
6d0f6bcf JCPV |
161 | #define CONFIG_SYS_REFREC 2 /* Refresh to activate interval */ |
162 | #define CONFIG_SYS_RDLAT 3 /* Data latancy from read command */ | |
c609719b WD |
163 | |
164 | /* Bit-field values for MCCR4. | |
165 | */ | |
6d0f6bcf JCPV |
166 | #define CONFIG_SYS_PRETOACT 2 /* Precharge to activate interval */ |
167 | #define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */ | |
168 | #define CONFIG_SYS_SDMODE_CAS_LAT 2 /* SDMODE CAS latancy */ | |
169 | #define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */ | |
170 | #define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length */ | |
171 | #define CONFIG_SYS_ACTORW 2 | |
172 | #define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1 | |
c609719b WD |
173 | |
174 | /* Memory bank settings. | |
175 | * Only bits 20-29 are actually used from these vales to set the | |
176 | * start/end addresses. The upper two bits will always be 0, and the lower | |
177 | * 20 bits will be 0x00000 for a start address, or 0xfffff for an end | |
178 | * address. Refer to the MPC8240 book. | |
179 | */ | |
180 | ||
6d0f6bcf JCPV |
181 | #define CONFIG_SYS_BANK0_START 0x00000000 |
182 | #define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1) | |
183 | #define CONFIG_SYS_BANK0_ENABLE 1 | |
184 | #define CONFIG_SYS_BANK1_START 0x3ff00000 | |
185 | #define CONFIG_SYS_BANK1_END 0x3fffffff | |
186 | #define CONFIG_SYS_BANK1_ENABLE 0 | |
187 | #define CONFIG_SYS_BANK2_START 0x3ff00000 | |
188 | #define CONFIG_SYS_BANK2_END 0x3fffffff | |
189 | #define CONFIG_SYS_BANK2_ENABLE 0 | |
190 | #define CONFIG_SYS_BANK3_START 0x3ff00000 | |
191 | #define CONFIG_SYS_BANK3_END 0x3fffffff | |
192 | #define CONFIG_SYS_BANK3_ENABLE 0 | |
193 | #define CONFIG_SYS_BANK4_START 0x3ff00000 | |
194 | #define CONFIG_SYS_BANK4_END 0x3fffffff | |
195 | #define CONFIG_SYS_BANK4_ENABLE 0 | |
196 | #define CONFIG_SYS_BANK5_START 0x3ff00000 | |
197 | #define CONFIG_SYS_BANK5_END 0x3fffffff | |
198 | #define CONFIG_SYS_BANK5_ENABLE 0 | |
199 | #define CONFIG_SYS_BANK6_START 0x3ff00000 | |
200 | #define CONFIG_SYS_BANK6_END 0x3fffffff | |
201 | #define CONFIG_SYS_BANK6_ENABLE 0 | |
202 | #define CONFIG_SYS_BANK7_START 0x3ff00000 | |
203 | #define CONFIG_SYS_BANK7_END 0x3fffffff | |
204 | #define CONFIG_SYS_BANK7_ENABLE 0 | |
205 | ||
206 | #define CONFIG_SYS_ODCR 0xff | |
207 | ||
208 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) | |
209 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
210 | ||
211 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) | |
212 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) | |
213 | ||
214 | #define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) | |
215 | #define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) | |
216 | ||
217 | #define CONFIG_SYS_IBAT3L (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT) | |
218 | #define CONFIG_SYS_IBAT3U (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP) | |
219 | ||
220 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L | |
221 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
222 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L | |
223 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
224 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L | |
225 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
226 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L | |
227 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
c609719b WD |
228 | |
229 | /* | |
230 | * For booting Linux, the board info and command line data | |
231 | * have to be in the first 8 MB of memory, since this is | |
232 | * the maximum mapped by the Linux kernel during initialization. | |
233 | */ | |
6d0f6bcf | 234 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
c609719b WD |
235 | |
236 | /*----------------------------------------------------------------------- | |
237 | * FLASH organization | |
238 | */ | |
6d0f6bcf JCPV |
239 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* Max number of flash banks */ |
240 | #define CONFIG_SYS_MAX_FLASH_SECT 39 /* Max number of sectors in one bank */ | |
c609719b | 241 | |
6d0f6bcf JCPV |
242 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
243 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
c609719b WD |
244 | |
245 | /* Warining: environment is not EMBEDDED in the U-Boot code. | |
246 | * It's stored in flash separately. | |
247 | */ | |
5a1aceb0 | 248 | #define CONFIG_ENV_IS_IN_FLASH 1 |
c609719b | 249 | #if 0 |
0e8d1586 JCPV |
250 | #define CONFIG_ENV_ADDR 0xFF008000 |
251 | #define CONFIG_ENV_SIZE 0x8000 /* Size of the Environment Sector */ | |
c609719b | 252 | #else |
0e8d1586 JCPV |
253 | #define CONFIG_ENV_ADDR 0xFFFC0000 |
254 | #define CONFIG_ENV_SIZE 0x4000 /* Size of the Environment */ | |
255 | #define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */ | |
256 | #define CONFIG_ENV_SECT_SIZE 0x40000 /* Size of the Environment Sector */ | |
c609719b WD |
257 | #endif |
258 | ||
259 | /*----------------------------------------------------------------------- | |
260 | * Cache Configuration | |
261 | */ | |
6d0f6bcf | 262 | #define CONFIG_SYS_CACHELINE_SIZE 32 |
49cf7e8e | 263 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 264 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
c609719b WD |
265 | #endif |
266 | ||
c609719b WD |
267 | /*----------------------------------------------------------------------- |
268 | * PCI stuff | |
269 | *----------------------------------------------------------------------- | |
270 | */ | |
271 | #define CONFIG_PCI /* include pci support */ | |
842033e6 | 272 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ |
c609719b WD |
273 | #undef CONFIG_PCI_PNP |
274 | ||
c609719b WD |
275 | |
276 | #define CONFIG_TULIP | |
277 | #define CONFIG_TULIP_USE_IO | |
278 | ||
6d0f6bcf JCPV |
279 | #define CONFIG_SYS_ETH_DEV_FN 0x7800 |
280 | #define CONFIG_SYS_ETH_IOBASE 0x00104000 | |
c609719b | 281 | |
3bac3513 | 282 | #define CONFIG_EEPRO100 |
6d0f6bcf | 283 | #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ |
3bac3513 WD |
284 | #define PCI_ENET0_IOADDR 0x00104000 |
285 | #define PCI_ENET0_MEMADDR 0x80000000 | |
c609719b | 286 | #endif /* __CONFIG_H */ |