[people/ms/u-boot.git] / include / configs / DASA_SIM.h

/*
 * (C) Copyright 2001
 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_IOP480		1	/* This is a IOP480 CPU		*/
#define CONFIG_DASA_SIM		1	/* ...on a DASA_SIM board	*/

#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/

#define CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */

#define CONFIG_CPUCLOCK		66
#define CONFIG_BUSCLOCK		(CONFIG_CPUCLOCK)

#define CONFIG_BAUDRATE		9600
#define CONFIG_BOOTDELAY	3	/* autoboot after 5 seconds	*/
#define CONFIG_BOOTCOMMAND	"bootm ffe00000" /* autoboot command	*/

#undef	CONFIG_BOOTARGS

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#undef CONFIG_WATCHDOG			/* watchdog disabled		*/

#define CONFIG_IPADDR		10.0.18.222
#define CONFIG_SERVERIP		10.0.18.190

#if 0
#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
				CFG_CMD_DHCP	| \
				CFG_CMD_IRQ	| \
				CFG_CMD_BSP	| \
				CFG_CMD_ASKENV	| \
				CFG_CMD_ELF	)
#else
#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
				CFG_CMD_BSP	)
#endif

#if 0 /* Does not appear to be used?!  If it is used, needs to be fixed */
#define CONFIG_SOFT_I2C			/* Software I2C support enabled */
#endif
#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory		*/
#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/

#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

/* The following table includes the supported baudrates */
#define CFG_BAUDRATE_TABLE	\
	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200 }

#define CFG_LOAD_ADDR	0x100000	/* default load address */

#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */

#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CFG_INIT_RAM_ADDR	0x00df0000 /* inside of SDRAM			*/
#define CFG_INIT_RAM_END	0x0f00	/* End of used area in RAM	       */
#define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define CFG_SDRAM_BASE		0x00000000
#define CFG_FLASH_BASE		0xFFFD0000
#define CFG_MONITOR_BASE	CFG_FLASH_BASE
#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 128 kB for Monitor	*/
#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CFG_FLASH_WORD_SIZE	unsigned char	/* flash word size (width)	*/
#define CFG_FLASH_ADDR0		0x0AA9	/* 1st address for flash config cycles	*/
#define CFG_FLASH_ADDR1		0x0556	/* 2nd address for flash config cycles	*/
/*
 * The following defines are added for buggy IOP480 byte interface.
 * All other boards should use the standard values (CPCI405 etc.)
 */
#define CFG_FLASH_READ0		0x0002	/* 0 is standard			*/
#define CFG_FLASH_READ1		0x0000	/* 1 is standard			*/
#define CFG_FLASH_READ2		0x0004	/* 2 is standard			*/

#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */

#define CFG_ENV_IS_IN_FLASH	1
#define CFG_ENV_OFFSET		0x00010000	/* Offset of Environment Sector */
#define CFG_ENV_SIZE		0x1000	/* Total Size of Environment Sector	*/

#if 0
#define CFG_ENV_SECT_SIZE	0x8000	/* see README - env sector total size	*/
#else
#define CFG_ENV_SECT_SIZE	0x10000 /* see README - env sector total size	*/
#endif

/*-----------------------------------------------------------------------
 * PCI stuff
 */
#define CONFIG_PCI			/* include pci support			*/
#undef CONFIG_PCI_PNP

#define CONFIG_NET_MULTI		/* Multi ethernet cards support		*/

#define CONFIG_TULIP

#define CFG_ETH_DEV_FN	     0x0000
#define CFG_ETH_IOBASE	     0x0fff0000
#define CFG_PCI9054_DEV_FN   0x0800
#define CFG_PCI9054_IOBASE   0x0eff0000

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_DCACHE_SIZE		2048	/* For PLX IOP480			*/
#define CFG_CACHELINE_SIZE	16	/* For AMCC 401/403 CPUs		*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0xFFE00000	/* FLASH bank #0	*/


/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

#endif	/* __CONFIG_H */
Commit	Line	Data
0f8c9768 WD	1	/*
	2	* (C) Copyright 2001
	3	* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
c837dcb1	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
0f8c9768 WD	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* board/config.h - configuration options, board specific
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	/*
	32	* High Level Configuration Options
	33	* (easy to change)
	34	*/
	35
	36	#define CONFIG_IOP480 1 /* This is a IOP480 CPU */
c837dcb1	37	#define CONFIG_DASA_SIM 1 /* ...on a DASA_SIM board */
0f8c9768	38
c837dcb1	39	#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
0f8c9768	40
c837dcb1	41	#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
0f8c9768	42
c837dcb1 WD	43	#define CONFIG_CPUCLOCK 66
c837dcb1 WD	44	#define CONFIG_BUSCLOCK (CONFIG_CPUCLOCK)
0f8c9768	45
c837dcb1	46	#define CONFIG_BAUDRATE 9600
0f8c9768 WD	47	#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
	48	#define CONFIG_BOOTCOMMAND "bootm ffe00000" /* autoboot command */
	49
c837dcb1	50	#undef CONFIG_BOOTARGS
0f8c9768 WD	51
	52	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	53	#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
	54
	55	#undef CONFIG_WATCHDOG /* watchdog disabled */
	56
	57	#define CONFIG_IPADDR 10.0.18.222
	58	#define CONFIG_SERVERIP 10.0.18.190
	59
	60	#if 0
	61	#define CONFIG_COMMANDS ( CONFIG_CMD_DFL \| \
	62	CFG_CMD_DHCP \| \
	63	CFG_CMD_IRQ \| \
	64	CFG_CMD_BSP \| \
	65	CFG_CMD_ASKENV \| \
c837dcb1	66	CFG_CMD_ELF )
0f8c9768 WD	67	#else
0f8c9768 WD	68	#define CONFIG_COMMANDS ( CONFIG_CMD_DFL \| \
c837dcb1	69	CFG_CMD_BSP )
0f8c9768 WD	70	#endif
	71
	72	#if 0 /* Does not appear to be used?! If it is used, needs to be fixed */
	73	#define CONFIG_SOFT_I2C /* Software I2C support enabled */
	74	#endif
c837dcb1	75	#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
0f8c9768 WD	76
	77	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
	78	#include <cmd_confdefs.h>
	79
	80	/*
	81	* Miscellaneous configurable options
	82	*/
	83	#define CFG_LONGHELP /* undef to save memory */
	84	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	85	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
c837dcb1	86	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
0f8c9768	87	#else
c837dcb1	88	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
0f8c9768 WD	89	#endif
	90	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	91	#define CFG_MAXARGS 16 /* max number of command args */
	92	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	93
c837dcb1	94	#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
0f8c9768 WD	95
	96	#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
	97	#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
	98
	99	/* The following table includes the supported baudrates */
c837dcb1	100	#define CFG_BAUDRATE_TABLE \
8bde7f77	101	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200 }
0f8c9768	102
c837dcb1	103	#define CFG_LOAD_ADDR 0x100000 /* default load address */
0f8c9768	104
c837dcb1	105	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
0f8c9768 WD	106
	107	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
	108
	109	/*-----------------------------------------------------------------------
	110	* Definitions for initial stack pointer and data area (in DPRAM)
	111	*/
c837dcb1	112	#define CFG_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */
0f8c9768 WD	113	#define CFG_INIT_RAM_END 0x0f00 /* End of used area in RAM */
	114	#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
	115	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	116	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	117
	118	/*-----------------------------------------------------------------------
	119	* Start addresses for the final memory configuration
	120	* (Set up by the startup code)
	121	* Please note that CFG_SDRAM_BASE _must_ start at 0
	122	*/
	123	#define CFG_SDRAM_BASE 0x00000000
	124	#define CFG_FLASH_BASE 0xFFFD0000
	125	#define CFG_MONITOR_BASE CFG_FLASH_BASE
	126	#define CFG_MONITOR_LEN (192 << 10) /* Reserve 128 kB for Monitor */
	127	#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	128
	129	/*
	130	* For booting Linux, the board info and command line data
	131	* have to be in the first 8 MB of memory, since this is
	132	* the maximum mapped by the Linux kernel during initialization.
	133	*/
c837dcb1	134	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
0f8c9768 WD	135	/*-----------------------------------------------------------------------
	136	* FLASH organization
	137	*/
	138	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
c837dcb1	139	#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
0f8c9768 WD	140
	141	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	142	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
	143
c837dcb1 WD	144	#define CFG_FLASH_WORD_SIZE unsigned char /* flash word size (width) */
	145	#define CFG_FLASH_ADDR0 0x0AA9 /* 1st address for flash config cycles */
	146	#define CFG_FLASH_ADDR1 0x0556 /* 2nd address for flash config cycles */
0f8c9768 WD	147	/*
	148	* The following defines are added for buggy IOP480 byte interface.
	149	* All other boards should use the standard values (CPCI405 etc.)
	150	*/
c837dcb1 WD	151	#define CFG_FLASH_READ0 0x0002 /* 0 is standard */
	152	#define CFG_FLASH_READ1 0x0000 /* 1 is standard */
	153	#define CFG_FLASH_READ2 0x0004 /* 2 is standard */
0f8c9768	154
c837dcb1	155	#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
0f8c9768	156
c837dcb1 WD	157	#define CFG_ENV_IS_IN_FLASH 1
c837dcb1 WD	158	#define CFG_ENV_OFFSET 0x00010000 /* Offset of Environment Sector */
0f8c9768 WD	159	#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
	160
	161	#if 0
	162	#define CFG_ENV_SECT_SIZE 0x8000 /* see README - env sector total size */
	163	#else
c837dcb1	164	#define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */
0f8c9768 WD	165	#endif
	166
	167	/*-----------------------------------------------------------------------
	168	* PCI stuff
	169	*/
	170	#define CONFIG_PCI /* include pci support */
	171	#undef CONFIG_PCI_PNP
	172
c837dcb1	173	#define CONFIG_NET_MULTI /* Multi ethernet cards support */
0f8c9768 WD	174
	175	#define CONFIG_TULIP
	176
c837dcb1 WD	177	#define CFG_ETH_DEV_FN 0x0000
c837dcb1 WD	178	#define CFG_ETH_IOBASE 0x0fff0000
0f8c9768 WD	179	#define CFG_PCI9054_DEV_FN 0x0800
	180	#define CFG_PCI9054_IOBASE 0x0eff0000
	181
	182	/*-----------------------------------------------------------------------
	183	* Cache Configuration
	184	*/
	185	#define CFG_DCACHE_SIZE 2048 /* For PLX IOP480 */
0c8721a4	186	#define CFG_CACHELINE_SIZE 16 /* For AMCC 401/403 CPUs */
0f8c9768 WD	187	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	188	#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
	189	#endif
	190
	191	/*
	192	* Init Memory Controller:
	193	*
	194	* BR0/1 and OR0/1 (FLASH)
	195	*/
	196
	197	#define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */
	198
	199
	200	/*
	201	* Internal Definitions
	202	*
	203	* Boot Flags
	204	*/
	205	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	206	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	207
	208	#endif /* __CONFIG_H */