[people/ms/u-boot.git] / include / configs / DU405.h

/*
 * (C) Copyright 2001
 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
#define CONFIG_DU405		1	/* ...on a DU405 board		*/

#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
#define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */

#define CONFIG_SYS_CLK_FREQ	25000000 /* external frequency to pll	*/

#define CONFIG_BAUDRATE		9600
#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/

#undef	CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND	"bootm fff00000"

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII		1	/* MII PHY management		*/
#define CONFIG_PHY_ADDR		0	/* PHY address			*/
#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
#define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
#define CONFIG_NET_MULTI	1
#undef  CONFIG_HAS_ETH1

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#undef CONFIG_CMD_NFS
#define CONFIG_CMD_IDE
#define CONFIG_CMD_ELF
#define CONFIG_CMD_MII
#define CONFIG_CMD_DATE
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C

#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION

#undef CONFIG_WATCHDOG			/* watchdog disabled		*/

#define CONFIG_RTC_MC146818		/* BQ3285 is MC146818 compatible*/
#define CONFIG_SYS_RTC_REG_BASE_ADDR	 0xF0000080 /* RTC Base Address		*/

#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/

#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_serial_clock()

#define CONFIG_SYS_EXT_SERIAL_CLOCK	11059200  /* use external serial clock	*/

/* The following table includes the supported baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE	\
	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
	 57600, 115200, 230400, 460800, 921600 }

#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */

#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */

#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */

#define CONFIG_SYS_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
#define PCI_HOST_ADAPTER 0		/* configure ar pci adapter	*/
#define PCI_HOST_FORCE	1		/* configure as pci host	*/
#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/

#define CONFIG_PCI			/* include pci support		*/
#define CONFIG_PCI_HOST PCI_HOST_AUTO	/* select pci host function	*/
#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
					/* resource configuration	*/

#define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/

#define CONFIG_PCI_BOOTDELAY	0	/* enable pci bootdelay variable*/

#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0404	/* PCI Device ID: CPCI-ISER4	*/
#define CONFIG_SYS_PCI_PTM1LA	0x00000000	/* point to sdram		*/
#define CONFIG_SYS_PCI_PTM1MS	0xff000001	/* 16MB, enable hard-wired to 1 */
#define CONFIG_SYS_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
#define CONFIG_SYS_PCI_PTM2LA	0xffe00000	/* point to flash		*/
#define CONFIG_SYS_PCI_PTM2MS	0xffe00001	/* 2MB, enable			*/
#define CONFIG_SYS_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/

/*-----------------------------------------------------------------------
 * IDE/ATA stuff
 *-----------------------------------------------------------------------
 */
#undef	CONFIG_IDE_8xx_DIRECT		/* no pcmcia interface required */
#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
#undef	CONFIG_IDE_RESET		/* no reset for ide supported	*/

#define CONFIG_SYS_IDE_MAXBUS		1		/* max. 1 IDE busses	*/
#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */

#define CONFIG_SYS_ATA_BASE_ADDR	0xF0100000
#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000

#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
#define CONFIG_SYS_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
#define CONFIG_SYS_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		0xFFFD0000
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN		(192 * 1024)	/* Reserve 192 kB for Monitor	*/
#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
/*
 * The following defines are added for buggy IOP480 byte interface.
 * All other boards should use the standard values (CPCI405 etc.)
 */
#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/

#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */

/*-----------------------------------------------------------------------
 * I2C EEPROM (CAT24WC08) for environment
 */
#define CONFIG_HARD_I2C			/* I2c with hardware support */
#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE		0x7F

#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
/* mask of address bits that overflow into the "EEPROM chip address"	*/
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
					/* 16 byte page write mode using*/
					/* last 4 bits of the address	*/
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */

#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
#define CONFIG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
#define CONFIG_ENV_SIZE		0x400	/* 1024 bytes may be used for env vars */
				   /* total size of a CAT24WC08 is 1024 bytes */

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0xFF800000	/* FLASH bank #0	*/
#define FLASH_BASE1_PRELIM	0xFFC00000	/* FLASH bank #1	*/

/*-----------------------------------------------------------------------
 * External Bus Controller (EBC) Setup
 */

#define FLASH0_BA	0xFFC00000	    /* FLASH 0 Base Address		*/
#define FLASH1_BA	0xFF800000	    /* FLASH 1 Base Address		*/
#define CAN_BA		0xF0000000	    /* CAN Base Address			*/
#define DUART_BA	0xF0300000	    /* DUART Base Address		*/
#define CF_BA		0xF0100000	    /* CompactFlash Base Address	*/
#define SRAM_BA		0xF0200000	    /* SRAM Base Address		*/
#define DURAG_IO_BA	0xF0400000	    /* DURAG Bus IO Base Address	*/
#define DURAG_MEM_BA	0xF0500000	    /* DURAG Bus Mem Base Address	*/

#define FPGA_MODE_REG	(DUART_BA+0x80)	    /* FPGA Mode Register		*/

/* Memory Bank 0 (Flash Bank 0) initialization					*/
#define CONFIG_SYS_EBC_PB0AP	0x92015480
#define CONFIG_SYS_EBC_PB0CR	FLASH0_BA | 0x5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */

/* Memory Bank 1 (Flash Bank 1) initialization					*/
#define CONFIG_SYS_EBC_PB1AP	0x92015480
#define CONFIG_SYS_EBC_PB1CR	FLASH1_BA | 0x5A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */

/* Memory Bank 2 (CAN0) initialization						*/
#define CONFIG_SYS_EBC_PB2AP	0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CONFIG_SYS_EBC_PB2CR	CAN_BA | 0x18000    /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/

/* Memory Bank 3 (DUART) initialization						*/
#define CONFIG_SYS_EBC_PB3AP	0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CONFIG_SYS_EBC_PB3CR	DUART_BA | 0x18000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit	*/

/* Memory Bank 4 (CompactFlash IDE) initialization				*/
#define CONFIG_SYS_EBC_PB4AP	0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CONFIG_SYS_EBC_PB4CR	CF_BA | 0x1A000	    /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */

/* Memory Bank 5 (SRAM) initialization						*/
#define CONFIG_SYS_EBC_PB5AP	0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CONFIG_SYS_EBC_PB5CR	SRAM_BA | 0x1A000   /* BAS=0xF02,BS=1MB,BU=R/W,BW=16bit */

/* Memory Bank 6 (DURAG Bus IO Space) initialization				*/
#define CONFIG_SYS_EBC_PB6AP	0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CONFIG_SYS_EBC_PB6CR	DURAG_IO_BA | 0x18000 /* BAS=0xF04,BS=1MB,BU=R/W,BW=8bit*/

/* Memory Bank 7 (DURAG Bus Mem Space) initialization				*/
#define CONFIG_SYS_EBC_PB7AP	0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CONFIG_SYS_EBC_PB7CR	DURAG_MEM_BA | 0x18000 /* BAS=0xF05,BS=1MB,BU=R/W,BW=8bit */


/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */

/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
#define CONFIG_SYS_TEMP_STACK_OCM	  1

/* On Chip Memory location */
#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
#define CONFIG_SYS_OCM_DATA_SIZE	0x1000

#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM	*/
#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET


/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

#endif	/* __CONFIG_H */
Commit	Line	Data
c609719b WD	1	/*
	2	* (C) Copyright 2001
	3	* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* board/config.h - configuration options, board specific
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	/*
	32	* High Level Configuration Options
	33	* (easy to change)
	34	*/
c609719b	35	#define CONFIG_405GP 1 /* This is a PPC405 CPU */
c837dcb1 WD	36	#define CONFIG_4xx 1 /* ...member of PPC4xx family */
c837dcb1 WD	37	#define CONFIG_DU405 1 /* ...on a DU405 board */
c609719b	38
c837dcb1	39	#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
82f4c6ac	40	#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
c609719b	41
c837dcb1	42	#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
c609719b WD	43
	44	#define CONFIG_BAUDRATE 9600
	45	#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
	46
	47	#undef CONFIG_BOOTARGS
	48	#define CONFIG_BOOTCOMMAND "bootm fff00000"
	49
	50	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	51	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
c609719b	52
96e21f86	53	#define CONFIG_PPC4xx_EMAC
c609719b	54	#define CONFIG_MII 1 /* MII PHY management */
c837dcb1	55	#define CONFIG_PHY_ADDR 0 /* PHY address */
a20b27a3	56	#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
09db8f4d MF	57	#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
	58	#define CONFIG_NET_MULTI 1
	59	#undef CONFIG_HAS_ETH1
3c3227f3	60
11799434 JL	61	/*
	62	* BOOTP options
	63	*/
	64	#define CONFIG_BOOTP_BOOTFILESIZE
	65	#define CONFIG_BOOTP_BOOTPATH
	66	#define CONFIG_BOOTP_GATEWAY
	67	#define CONFIG_BOOTP_HOSTNAME
	68
	69
3c3227f3 JL	70	/*
	71	* Command line configuration.
	72	*/
	73	#include <config_cmd_default.h>
	74
09db8f4d	75	#undef CONFIG_CMD_NFS
3c3227f3 JL	76	#define CONFIG_CMD_IDE
	77	#define CONFIG_CMD_ELF
	78	#define CONFIG_CMD_MII
	79	#define CONFIG_CMD_DATE
	80	#define CONFIG_CMD_EEPROM
09db8f4d	81	#define CONFIG_CMD_I2C
c609719b WD	82
	83	#define CONFIG_MAC_PARTITION
	84	#define CONFIG_DOS_PARTITION
	85
c609719b WD	86	#undef CONFIG_WATCHDOG /* watchdog disabled */
c609719b WD	87
c837dcb1	88	#define CONFIG_RTC_MC146818 /* BQ3285 is MC146818 compatible*/
6d0f6bcf	89	#define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000080 /* RTC Base Address */
c609719b	90
c837dcb1	91	#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
c609719b WD	92
	93	/*
	94	* Miscellaneous configurable options
	95	*/
6d0f6bcf JCPV	96	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	97	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
3c3227f3	98	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	99	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
c609719b	100	#else
6d0f6bcf	101	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
c609719b	102	#endif
6d0f6bcf JCPV	103	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	104	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	105	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
c609719b	106
6d0f6bcf	107	#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
c609719b	108
6d0f6bcf JCPV	109	#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
6d0f6bcf JCPV	110	#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
c609719b	111
550650dd SR	112	#define CONFIG_CONS_INDEX 1 /* Use UART0 */
	113	#define CONFIG_SYS_NS16550
	114	#define CONFIG_SYS_NS16550_SERIAL
	115	#define CONFIG_SYS_NS16550_REG_SIZE 1
	116	#define CONFIG_SYS_NS16550_CLK get_serial_clock()
	117
6d0f6bcf	118	#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* use external serial clock */
c609719b WD	119
c609719b WD	120	/* The following table includes the supported baudrates */
6d0f6bcf	121	#define CONFIG_SYS_BAUDRATE_TABLE \
8bde7f77 WD	122	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
8bde7f77 WD	123	57600, 115200, 230400, 460800, 921600 }
c609719b	124
6d0f6bcf JCPV	125	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
6d0f6bcf JCPV	126	#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
c609719b	127
6d0f6bcf	128	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
c609719b WD	129
	130	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
	131
6d0f6bcf	132	#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
a20b27a3	133
c609719b WD	134	/*-----------------------------------------------------------------------
	135	* PCI stuff
	136	*-----------------------------------------------------------------------
	137	*/
c837dcb1 WD	138	#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
	139	#define PCI_HOST_FORCE 1 /* configure as pci host */
	140	#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
c609719b	141
c837dcb1 WD	142	#define CONFIG_PCI /* include pci support */
	143	#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
	144	#define CONFIG_PCI_PNP /* do pci plug-and-play */
	145	/* resource configuration */
c609719b	146
c837dcb1	147	#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
ad10dd9a	148
c837dcb1	149	#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
ad10dd9a	150
6d0f6bcf JCPV	151	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
	152	#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0404 /* PCI Device ID: CPCI-ISER4 */
	153	#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
	154	#define CONFIG_SYS_PCI_PTM1MS 0xff000001 /* 16MB, enable hard-wired to 1 */
	155	#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
	156	#define CONFIG_SYS_PCI_PTM2LA 0xffe00000 /* point to flash */
	157	#define CONFIG_SYS_PCI_PTM2MS 0xffe00001 /* 2MB, enable */
	158	#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
c609719b WD	159
	160	/*-----------------------------------------------------------------------
	161	* IDE/ATA stuff
	162	*-----------------------------------------------------------------------
	163	*/
c837dcb1 WD	164	#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
	165	#undef CONFIG_IDE_LED /* no led for ide supported */
	166	#undef CONFIG_IDE_RESET /* no reset for ide supported */
c609719b	167
6d0f6bcf JCPV	168	#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */
6d0f6bcf JCPV	169	#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS1) / max. 1 drives per IDE bus */
c609719b	170
6d0f6bcf JCPV	171	#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000
6d0f6bcf JCPV	172	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
c609719b	173
6d0f6bcf JCPV	174	#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
	175	#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
	176	#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
c609719b WD	177
	178	/*-----------------------------------------------------------------------
	179	* Start addresses for the final memory configuration
	180	* (Set up by the startup code)
6d0f6bcf	181	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
c609719b	182	*/
6d0f6bcf JCPV	183	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	184	#define CONFIG_SYS_FLASH_BASE 0xFFFD0000
	185	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	186	#define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Monitor */
	187	#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
c609719b WD	188
	189	/*
	190	* For booting Linux, the board info and command line data
	191	* have to be in the first 8 MB of memory, since this is
	192	* the maximum mapped by the Linux kernel during initialization.
	193	*/
6d0f6bcf	194	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
c609719b WD	195	/*-----------------------------------------------------------------------
	196	* FLASH organization
	197	*/
6d0f6bcf JCPV	198	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
6d0f6bcf JCPV	199	#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
c609719b	200
6d0f6bcf JCPV	201	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	202	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
c609719b	203
6d0f6bcf JCPV	204	#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
	205	#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
	206	#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
c609719b WD	207	/*
	208	* The following defines are added for buggy IOP480 byte interface.
	209	* All other boards should use the standard values (CPCI405 etc.)
	210	*/
6d0f6bcf JCPV	211	#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
	212	#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
	213	#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
c609719b	214
6d0f6bcf	215	#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
c609719b WD	216
	217	/*-----------------------------------------------------------------------
	218	* I2C EEPROM (CAT24WC08) for environment
	219	*/
	220	#define CONFIG_HARD_I2C /* I2c with hardware support */
d0b0dcaa	221	#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
6d0f6bcf JCPV	222	#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
6d0f6bcf JCPV	223	#define CONFIG_SYS_I2C_SLAVE 0x7F
c609719b	224
6d0f6bcf JCPV	225	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
6d0f6bcf JCPV	226	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
c837dcb1	227	/* mask of address bits that overflow into the "EEPROM chip address" */
6d0f6bcf JCPV	228	#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
6d0f6bcf JCPV	229	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
c609719b	230	/* 16 byte page write mode using*/
c837dcb1	231	/* last 4 bits of the address */
6d0f6bcf	232	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
c609719b	233
bb1f8b4f	234	#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
0e8d1586 JCPV	235	#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
0e8d1586 JCPV	236	#define CONFIG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars */
8bde7f77	237	/* total size of a CAT24WC08 is 1024 bytes */
c609719b	238
c609719b WD	239	/*
	240	* Init Memory Controller:
	241	*
	242	* BR0/1 and OR0/1 (FLASH)
	243	*/
	244
	245	#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
	246	#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */
	247
	248	/*-----------------------------------------------------------------------
	249	* External Bus Controller (EBC) Setup
	250	*/
	251
c837dcb1 WD	252	#define FLASH0_BA 0xFFC00000 /* FLASH 0 Base Address */
	253	#define FLASH1_BA 0xFF800000 /* FLASH 1 Base Address */
	254	#define CAN_BA 0xF0000000 /* CAN Base Address */
	255	#define DUART_BA 0xF0300000 /* DUART Base Address */
	256	#define CF_BA 0xF0100000 /* CompactFlash Base Address */
	257	#define SRAM_BA 0xF0200000 /* SRAM Base Address */
	258	#define DURAG_IO_BA 0xF0400000 /* DURAG Bus IO Base Address */
	259	#define DURAG_MEM_BA 0xF0500000 /* DURAG Bus Mem Base Address */
c609719b	260
c837dcb1	261	#define FPGA_MODE_REG (DUART_BA+0x80) /* FPGA Mode Register */
c609719b	262
c837dcb1	263	/* Memory Bank 0 (Flash Bank 0) initialization */
6d0f6bcf JCPV	264	#define CONFIG_SYS_EBC_PB0AP 0x92015480
6d0f6bcf JCPV	265	#define CONFIG_SYS_EBC_PB0CR FLASH0_BA \| 0x5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
c609719b	266
c837dcb1	267	/* Memory Bank 1 (Flash Bank 1) initialization */
6d0f6bcf JCPV	268	#define CONFIG_SYS_EBC_PB1AP 0x92015480
6d0f6bcf JCPV	269	#define CONFIG_SYS_EBC_PB1CR FLASH1_BA \| 0x5A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
c609719b	270
c837dcb1	271	/* Memory Bank 2 (CAN0) initialization */
6d0f6bcf JCPV	272	#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
6d0f6bcf JCPV	273	#define CONFIG_SYS_EBC_PB2CR CAN_BA \| 0x18000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
c609719b	274
c837dcb1	275	/* Memory Bank 3 (DUART) initialization */
6d0f6bcf JCPV	276	#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
6d0f6bcf JCPV	277	#define CONFIG_SYS_EBC_PB3CR DUART_BA \| 0x18000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
c609719b	278
c837dcb1	279	/* Memory Bank 4 (CompactFlash IDE) initialization */
6d0f6bcf JCPV	280	#define CONFIG_SYS_EBC_PB4AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
6d0f6bcf JCPV	281	#define CONFIG_SYS_EBC_PB4CR CF_BA \| 0x1A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
c609719b	282
c837dcb1	283	/* Memory Bank 5 (SRAM) initialization */
6d0f6bcf JCPV	284	#define CONFIG_SYS_EBC_PB5AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
6d0f6bcf JCPV	285	#define CONFIG_SYS_EBC_PB5CR SRAM_BA \| 0x1A000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=16bit */
c609719b	286
c837dcb1	287	/* Memory Bank 6 (DURAG Bus IO Space) initialization */
6d0f6bcf JCPV	288	#define CONFIG_SYS_EBC_PB6AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
6d0f6bcf JCPV	289	#define CONFIG_SYS_EBC_PB6CR DURAG_IO_BA \| 0x18000 /* BAS=0xF04,BS=1MB,BU=R/W,BW=8bit*/
c609719b	290
c837dcb1	291	/* Memory Bank 7 (DURAG Bus Mem Space) initialization */
6d0f6bcf JCPV	292	#define CONFIG_SYS_EBC_PB7AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
6d0f6bcf JCPV	293	#define CONFIG_SYS_EBC_PB7CR DURAG_MEM_BA \| 0x18000 /* BAS=0xF05,BS=1MB,BU=R/W,BW=8bit */
c609719b WD	294
	295
	296	/*-----------------------------------------------------------------------
	297	* Definitions for initial stack pointer and data area (in DPRAM)
	298	*/
	299
	300	/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
6d0f6bcf	301	#define CONFIG_SYS_TEMP_STACK_OCM 1
c609719b WD	302
c609719b WD	303	/* On Chip Memory location */
6d0f6bcf JCPV	304	#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
	305	#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
	306
	307	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
	308	#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
	309	#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	310	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
	311	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
c609719b WD	312
	313
	314	/*
	315	* Internal Definitions
	316	*
	317	* Boot Flags
	318	*/
	319	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	320	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	321
	322	#endif /* __CONFIG_H */