[people/ms/u-boot.git] / include / configs / ELPPC.h

/*
 * (C) Copyright 2002 ELTEC Elektronik AG
 * Frank Gottschling <fgottschling@eltec.de>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define GTREGREAD(x) 0xffffffff         /* needed for debug */

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define	CONFIG_SYS_TEXT_BASE	0xFFF00000

/* these hardware addresses are pretty bogus, please change them to
   suit your needs */

/* first ethernet */
#define CONFIG_ETHADDR          00:00:5b:ee:de:ad

#define CONFIG_IPADDR           192.168.0.105
#define CONFIG_SERVERIP         192.168.0.100

#define CONFIG_ELPPC            1       /* this is an BAB740/BAB750 board */

#define CONFIG_BAUDRATE         9600    /* console baudrate */

#undef  CONFIG_WATCHDOG

#define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */

#define CONFIG_ZERO_BOOTDELAY_CHECK

#undef  CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND                                  \
    "bootp 1000000; "                                       \
    "setenv bootargs root=ramfs console=ttyS00,9600 "       \
    "ip=${ipaddr}:${serverip}:${rootpath}:${gatewayip}:"    \
    "${netmask}:${hostname}:eth0:none; "                    \
    "bootm"

#define CONFIG_LOADS_ECHO       0       /* echo off for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE           /* allow baudrate changes */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH

#define CONFIG_BOOTP_BOOTFILESIZE


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_PCI
#define CONFIG_CMD_JFFS2


/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP                    /* undef to save memory */
#define CONFIG_SYS_PROMPT              "=> "   /* Monitor Command Prompt */

/*
 * choose between COM1 and COM2 as serial console
 */
#define CONFIG_CONS_INDEX       1

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE              1024        /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE              256         /* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS             16          /* max number of command args    */
#define CONFIG_SYS_BARGSIZE            CONFIG_SYS_CBSIZE  /* Boot Argument Buffer Size    */

#define CONFIG_SYS_MEMTEST_START       0x00000000  /* memtest works on    */
#define CONFIG_SYS_MEMTEST_END         0x04000000  /* 0 ... 64 MB in DRAM    */

#define CONFIG_SYS_LOAD_ADDR           0x1000000   /* default load address    */

#define CONFIG_SYS_HZ                  1000        /* dec. freq: 1 ms ticks */

#define CONFIG_SYS_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
#define CONFIG_SYS_BOARD_ASM_INIT
#define CONFIG_MISC_INIT_R

/*
 * Address mapping scheme for the MPC107 mem controller is mapping B (CHRP)
 */
#undef  CONFIG_SYS_ADDRESS_MAP_A

#define CONFIG_SYS_PCI_MEMORY_BUS      0x00000000
#define CONFIG_SYS_PCI_MEMORY_PHYS     0x00000000
#define CONFIG_SYS_PCI_MEMORY_SIZE     0x40000000

#define CONFIG_SYS_PCI_MEM_BUS         0x80000000
#define CONFIG_SYS_PCI_MEM_PHYS        0x80000000
#define CONFIG_SYS_PCI_MEM_SIZE        0x7d000000

#define CONFIG_SYS_ISA_MEM_BUS         0x00000000
#define CONFIG_SYS_ISA_MEM_PHYS        0xfd000000
#define CONFIG_SYS_ISA_MEM_SIZE        0x01000000

#define CONFIG_SYS_PCI_IO_BUS          0x00800000
#define CONFIG_SYS_PCI_IO_PHYS         0xfe800000
#define CONFIG_SYS_PCI_IO_SIZE         0x00400000

#define CONFIG_SYS_ISA_IO_BUS          0x00000000
#define CONFIG_SYS_ISA_IO_PHYS         0xfe000000
#define CONFIG_SYS_ISA_IO_SIZE         0x00800000

/* driver defines FDC,IDE,... */
#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_ISA_IO_PHYS
#define CONFIG_SYS_ISA_IO              CONFIG_SYS_ISA_IO_PHYS
#define CONFIG_SYS_60X_PCI_IO_OFFSET   CONFIG_SYS_ISA_IO_PHYS

/*
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE          0x00000000

#define CONFIG_SYS_USR_LED_BASE        0x78000000
#define CONFIG_SYS_NVRAM_BASE          0xff000000
#define CONFIG_SYS_UART_BASE           0xff400000
#define CONFIG_SYS_FLASH_BASE          0xfff00000

#define MPC107_EUMB_ADDR        0xfce00000
#define MPC107_EUMB_PI          0xfce41090
#define MPC107_EUMB_GCR         0xfce41020
#define MPC107_EUMB_IACKR       0xfce600a0
#define MPC107_I2C_ADDR         0xfce03000

/*
 * Definitions for initial stack pointer and data area
 */
#define CONFIG_SYS_INIT_RAM_ADDR       0x00fd0000  /* above the memtest region */
#define CONFIG_SYS_INIT_RAM_SIZE        0x4000
#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET

/*
 * Flash mapping/organization on the MPC10x.
 */
#define FLASH_BASE0_PRELIM      0xff800000
#define FLASH_BASE1_PRELIM      0xffc00000

#define CONFIG_SYS_MAX_FLASH_BANKS     2           /* max number of memory banks    */
#define CONFIG_SYS_MAX_FLASH_SECT      67          /* max number of sectors on one chip */

#define CONFIG_SYS_FLASH_ERASE_TOUT    120000      /* Timeout for Flash Erase (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT    500         /* Timeout for Flash Write (in ms) */

/*
 * JFFS2 partitions
 *
 */
/* No command line, one static partition, whole device */
#undef CONFIG_CMD_MTDPARTS
#define CONFIG_JFFS2_DEV		"nor0"
#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
#define CONFIG_JFFS2_PART_OFFSET	0x00000000

/* mtdparts command line support */
/* Note: fake mtd_id used, no linux mtd map file */
/*
#define CONFIG_CMD_MTDPARTS
#define MTDIDS_DEFAULT		"nor0=elppc-0,nor1=elppc-1"
#define MTDPARTS_DEFAULT	"mtdparts=elppc-0:-(jffs2),elppc-1:-(user)"
*/

#define CONFIG_SYS_MONITOR_BASE        CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN         0x40000     /* Reserve 256 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN          0x20000     /* Reserve 128 kB for malloc() */
#undef  CONFIG_SYS_MEMTEST

/*
 * Environment settings
 */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_ENV_IS_IN_NVRAM     1           /* use NVRAM for environment vars */
#define CONFIG_SYS_NVRAM_SIZE          0x800       /* NVRAM size (2kB) */
#define CONFIG_ENV_SIZE            0x400       /* Size of Environment vars (1kB) */
#define CONFIG_ENV_ADDR            0x0
#define CONFIG_ENV_MAP_ADRS        0xff000000
#define CONFIG_SYS_NV_SROM_COPY_ADDR   (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
#define CONFIG_SYS_NVRAM_ACCESS_ROUTINE            /* only byte accsess alowed */
#define CONFIG_SYS_SROM_SIZE           0x100       /* shadow of revision info is in nvram */

/*
 * Serial devices
 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE    1
#define CONFIG_SYS_NS16550_CLK         24000000
#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_UART_BASE + 0)
#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_UART_BASE + 8)

/*
 * PCI stuff
 */
#define CONFIG_PCI                                /* include pci support */
#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
#define CONFIG_PCI_PNP                            /* pci plug-and-play */
#define CONFIG_PCI_HOST         PCI_HOST_AUTO
#undef  CONFIG_PCI_SCAN_SHOW

/*
 * Optional Video console (graphic: SMI LynxEM)
 */
#define CONFIG_VIDEO
#define CONFIG_CFB_CONSOLE
#define VIDEO_KBD_INIT_FCT    (simple_strtol (getenv("console"), NULL, 10))
#define VIDEO_TSTC_FCT        serial_tstc
#define VIDEO_GETC_FCT        serial_getc

#define CONFIG_VIDEO_SMI_LYNXEM
#define CONFIG_VIDEO_LOGO
#define CONFIG_CONSOLE_EXTRA_INFO

/*
 * Initial BATs
 */
#if 1

#define CONFIG_SYS_IBAT0L 0
#define CONFIG_SYS_IBAT0U 0
#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT1U

#define CONFIG_SYS_IBAT1L 0
#define CONFIG_SYS_IBAT1U 0
#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U

#define CONFIG_SYS_IBAT2L 0
#define CONFIG_SYS_IBAT2U 0
#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U

#define CONFIG_SYS_IBAT3L 0
#define CONFIG_SYS_IBAT3U 0
#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U

#else

/* SDRAM */
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_RW)
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT1U

/* address range for flashes */
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_FLASH_BASE | BATL_RW | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_FLASH_BASE | BATU_BL_16M | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U

/* ISA IO space */
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_ISA_IO | BATL_RW | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_ISA_IO | BATU_BL_16M | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U

/* ISA memory space */
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_ISA_MEM | BATL_RW | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_ISA_MEM | BATU_BL_16M | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U

#endif

/*
 * Speed settings are board specific
 */
#define CONFIG_SYS_BUS_CLK	100000000
#define CONFIG_SYS_CPU_CLK	400000000

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ           (8 << 20)           /* Initial Memory map for Linux */

/*
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE        32    /* For all MPC74xx CPUs */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CACHELINE_SHIFT        5    /* log base 2 of the above value */
#endif

/*
 * L2CR setup -- make sure this is right for your board!
 * look in include/74xx_7xx.h for the defines used here
 */

#define CONFIG_SYS_L2

#if 1
#define L2_INIT     0       /* cpu 750 CXe*/
#else
#define L2_INIT     (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
		     L2CR_L2OH_5   | L2CR_L2CTL | L2CR_L2WT)
#endif
#define L2_ENABLE   (L2_INIT | L2CR_L2E)

#define CONFIG_EEPRO100
#define CONFIG_SYS_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
#define CONFIG_EEPRO100_SROM_WRITE

#endif    /* __CONFIG_H */
Commit	Line	Data
e2211743 WD	1	/*
	2	* (C) Copyright 2002 ELTEC Elektronik AG
	3	* Frank Gottschling <fgottschling@eltec.de>
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
e2211743 WD	6	*/
	7
	8	/*
	9	* board/config.h - configuration options, board specific
	10	*/
	11
	12	#ifndef __CONFIG_H
	13	#define __CONFIG_H
	14
e2211743 WD	15	#define GTREGREAD(x) 0xffffffff /* needed for debug */
	16
	17	/*
	18	* High Level Configuration Options
	19	* (easy to change)
	20	*/
	21
2ae18241 WD	22	#define CONFIG_SYS_TEXT_BASE 0xFFF00000
2ae18241 WD	23
e2211743 WD	24	/* these hardware addresses are pretty bogus, please change them to
	25	suit your needs */
	26
	27	/* first ethernet */
	28	#define CONFIG_ETHADDR 00:00:5b:ee:de:ad
	29
	30	#define CONFIG_IPADDR 192.168.0.105
	31	#define CONFIG_SERVERIP 192.168.0.100
	32
	33	#define CONFIG_ELPPC 1 /* this is an BAB740/BAB750 board */
	34
	35	#define CONFIG_BAUDRATE 9600 /* console baudrate */
	36
	37	#undef CONFIG_WATCHDOG
	38
	39	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	40
	41	#define CONFIG_ZERO_BOOTDELAY_CHECK
	42
	43	#undef CONFIG_BOOTARGS
	44	#define CONFIG_BOOTCOMMAND \
	45	"bootp 1000000; " \
	46	"setenv bootargs root=ramfs console=ttyS00,9600 " \
fe126d8b WD	47	"ip=${ipaddr}:${serverip}:${rootpath}:${gatewayip}:" \
fe126d8b WD	48	"${netmask}:${hostname}:eth0:none; " \
e2211743 WD	49	"bootm"
	50
	51	#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
6d0f6bcf	52	#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */
e2211743	53
5d2ebe1b JL	54	/*
	55	* BOOTP options
	56	*/
	57	#define CONFIG_BOOTP_SUBNETMASK
	58	#define CONFIG_BOOTP_GATEWAY
	59	#define CONFIG_BOOTP_HOSTNAME
	60	#define CONFIG_BOOTP_BOOTPATH
	61
	62	#define CONFIG_BOOTP_BOOTFILESIZE
e2211743	63
e2211743	64
dcaa7156 JL	65	/*
	66	* Command line configuration.
	67	*/
	68	#include <config_cmd_default.h>
	69
	70	#define CONFIG_CMD_PCI
	71	#define CONFIG_CMD_JFFS2
	72
e2211743 WD	73
	74	/*
	75	* Miscellaneous configurable options
	76	*/
6d0f6bcf JCPV	77	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	78	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
e2211743 WD	79
	80	/*
	81	* choose between COM1 and COM2 as serial console
	82	*/
	83	#define CONFIG_CONS_INDEX 1
	84
dcaa7156	85	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	86	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
e2211743	87	#else
6d0f6bcf	88	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
e2211743	89	#endif
6d0f6bcf JCPV	90	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	91	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	92	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
e2211743	93
6d0f6bcf JCPV	94	#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
6d0f6bcf JCPV	95	#define CONFIG_SYS_MEMTEST_END 0x04000000 /* 0 ... 64 MB in DRAM */
e2211743	96
6d0f6bcf	97	#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
e2211743	98
6d0f6bcf	99	#define CONFIG_SYS_HZ 1000 /* dec. freq: 1 ms ticks */
e2211743	100
6d0f6bcf	101	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
e2211743 WD	102
	103	/*
	104	* Low Level Configuration Settings
	105	* (address mappings, register initial values, etc.)
	106	* You should know what you are doing if you make changes here.
	107	*/
6d0f6bcf	108	#define CONFIG_SYS_BOARD_ASM_INIT
e2211743 WD	109	#define CONFIG_MISC_INIT_R
	110
	111	/*
	112	* Address mapping scheme for the MPC107 mem controller is mapping B (CHRP)
	113	*/
6d0f6bcf	114	#undef CONFIG_SYS_ADDRESS_MAP_A
e2211743	115
6d0f6bcf JCPV	116	#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000
	117	#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
	118	#define CONFIG_SYS_PCI_MEMORY_SIZE 0x40000000
e2211743	119
6d0f6bcf JCPV	120	#define CONFIG_SYS_PCI_MEM_BUS 0x80000000
	121	#define CONFIG_SYS_PCI_MEM_PHYS 0x80000000
	122	#define CONFIG_SYS_PCI_MEM_SIZE 0x7d000000
e2211743	123
6d0f6bcf JCPV	124	#define CONFIG_SYS_ISA_MEM_BUS 0x00000000
	125	#define CONFIG_SYS_ISA_MEM_PHYS 0xfd000000
	126	#define CONFIG_SYS_ISA_MEM_SIZE 0x01000000
e2211743	127
6d0f6bcf JCPV	128	#define CONFIG_SYS_PCI_IO_BUS 0x00800000
	129	#define CONFIG_SYS_PCI_IO_PHYS 0xfe800000
	130	#define CONFIG_SYS_PCI_IO_SIZE 0x00400000
e2211743	131
6d0f6bcf JCPV	132	#define CONFIG_SYS_ISA_IO_BUS 0x00000000
	133	#define CONFIG_SYS_ISA_IO_PHYS 0xfe000000
	134	#define CONFIG_SYS_ISA_IO_SIZE 0x00800000
e2211743 WD	135
e2211743 WD	136	/* driver defines FDC,IDE,... */
6d0f6bcf JCPV	137	#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_ISA_IO_PHYS
	138	#define CONFIG_SYS_ISA_IO CONFIG_SYS_ISA_IO_PHYS
	139	#define CONFIG_SYS_60X_PCI_IO_OFFSET CONFIG_SYS_ISA_IO_PHYS
e2211743 WD	140
	141	/*
	142	* Start addresses for the final memory configuration
	143	* (Set up by the startup code)
6d0f6bcf	144	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
e2211743	145	*/
6d0f6bcf	146	#define CONFIG_SYS_SDRAM_BASE 0x00000000
e2211743	147
6d0f6bcf JCPV	148	#define CONFIG_SYS_USR_LED_BASE 0x78000000
	149	#define CONFIG_SYS_NVRAM_BASE 0xff000000
	150	#define CONFIG_SYS_UART_BASE 0xff400000
	151	#define CONFIG_SYS_FLASH_BASE 0xfff00000
e2211743 WD	152
	153	#define MPC107_EUMB_ADDR 0xfce00000
	154	#define MPC107_EUMB_PI 0xfce41090
	155	#define MPC107_EUMB_GCR 0xfce41020
	156	#define MPC107_EUMB_IACKR 0xfce600a0
	157	#define MPC107_I2C_ADDR 0xfce03000
	158
	159	/*
	160	* Definitions for initial stack pointer and data area
	161	*/
6d0f6bcf	162	#define CONFIG_SYS_INIT_RAM_ADDR 0x00fd0000 /* above the memtest region */
553f0982	163	#define CONFIG_SYS_INIT_RAM_SIZE 0x4000
25ddd1fb	164	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	165	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
e2211743 WD	166
	167	/*
	168	* Flash mapping/organization on the MPC10x.
	169	*/
	170	#define FLASH_BASE0_PRELIM 0xff800000
	171	#define FLASH_BASE1_PRELIM 0xffc00000
	172
6d0f6bcf JCPV	173	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
6d0f6bcf JCPV	174	#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
e2211743	175
6d0f6bcf JCPV	176	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	177	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
e2211743	178
700a0c64 WD	179	/*
	180	* JFFS2 partitions
	181	*
	182	*/
	183	/* No command line, one static partition, whole device */
68d7d651	184	#undef CONFIG_CMD_MTDPARTS
700a0c64 WD	185	#define CONFIG_JFFS2_DEV "nor0"
	186	#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
	187	#define CONFIG_JFFS2_PART_OFFSET 0x00000000
	188
	189	/* mtdparts command line support */
	190	/* Note: fake mtd_id used, no linux mtd map file */
	191	/*
68d7d651	192	#define CONFIG_CMD_MTDPARTS
700a0c64 WD	193	#define MTDIDS_DEFAULT "nor0=elppc-0,nor1=elppc-1"
	194	#define MTDPARTS_DEFAULT "mtdparts=elppc-0:-(jffs2),elppc-1:-(user)"
	195	*/
e2211743	196
6d0f6bcf JCPV	197	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	198	#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256 kB for Monitor */
	199	#define CONFIG_SYS_MALLOC_LEN 0x20000 /* Reserve 128 kB for malloc() */
	200	#undef CONFIG_SYS_MEMTEST
e2211743 WD	201
	202	/*
	203	* Environment settings
	204	*/
	205	#define CONFIG_ENV_OVERWRITE
9314cee6	206	#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
6d0f6bcf	207	#define CONFIG_SYS_NVRAM_SIZE 0x800 /* NVRAM size (2kB) */
0e8d1586 JCPV	208	#define CONFIG_ENV_SIZE 0x400 /* Size of Environment vars (1kB) */
	209	#define CONFIG_ENV_ADDR 0x0
	210	#define CONFIG_ENV_MAP_ADRS 0xff000000
6d0f6bcf JCPV	211	#define CONFIG_SYS_NV_SROM_COPY_ADDR (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
	212	#define CONFIG_SYS_NVRAM_ACCESS_ROUTINE /* only byte accsess alowed */
	213	#define CONFIG_SYS_SROM_SIZE 0x100 /* shadow of revision info is in nvram */
e2211743 WD	214
	215	/*
	216	* Serial devices
	217	*/
6d0f6bcf JCPV	218	#define CONFIG_SYS_NS16550
	219	#define CONFIG_SYS_NS16550_SERIAL
	220	#define CONFIG_SYS_NS16550_REG_SIZE 1
	221	#define CONFIG_SYS_NS16550_CLK 24000000
	222	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_UART_BASE + 0)
	223	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_UART_BASE + 8)
e2211743 WD	224
	225	/*
	226	* PCI stuff
	227	*/
	228	#define CONFIG_PCI /* include pci support */
842033e6	229	#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
e2211743 WD	230	#define CONFIG_PCI_PNP /* pci plug-and-play */
	231	#define CONFIG_PCI_HOST PCI_HOST_AUTO
	232	#undef CONFIG_PCI_SCAN_SHOW
	233
	234	/*
	235	* Optional Video console (graphic: SMI LynxEM)
	236	*/
	237	#define CONFIG_VIDEO
	238	#define CONFIG_CFB_CONSOLE
	239	#define VIDEO_KBD_INIT_FCT (simple_strtol (getenv("console"), NULL, 10))
	240	#define VIDEO_TSTC_FCT serial_tstc
	241	#define VIDEO_GETC_FCT serial_getc
	242
	243	#define CONFIG_VIDEO_SMI_LYNXEM
	244	#define CONFIG_VIDEO_LOGO
	245	#define CONFIG_CONSOLE_EXTRA_INFO
	246
	247	/*
	248	* Initial BATs
	249	*/
	250	#if 1
	251
6d0f6bcf JCPV	252	#define CONFIG_SYS_IBAT0L 0
	253	#define CONFIG_SYS_IBAT0U 0
	254	#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT1L
	255	#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT1U
e2211743	256
6d0f6bcf JCPV	257	#define CONFIG_SYS_IBAT1L 0
	258	#define CONFIG_SYS_IBAT1U 0
	259	#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
	260	#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
e2211743	261
6d0f6bcf JCPV	262	#define CONFIG_SYS_IBAT2L 0
	263	#define CONFIG_SYS_IBAT2U 0
	264	#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
	265	#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
e2211743	266
6d0f6bcf JCPV	267	#define CONFIG_SYS_IBAT3L 0
	268	#define CONFIG_SYS_IBAT3U 0
	269	#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
	270	#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
e2211743 WD	271
	272	#else
	273
	274	/* SDRAM */
6d0f6bcf JCPV	275	#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \| BATL_RW)
	276	#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	277	#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT1L
	278	#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT1U
e2211743 WD	279
e2211743 WD	280	/* address range for flashes */
6d0f6bcf JCPV	281	#define CONFIG_SYS_IBAT1L (CONFIG_SYS_FLASH_BASE \| BATL_RW \| BATL_CACHEINHIBIT)
	282	#define CONFIG_SYS_IBAT1U (CONFIG_SYS_FLASH_BASE \| BATU_BL_16M \| BATU_VS \| BATU_VP)
	283	#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
	284	#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
e2211743 WD	285
e2211743 WD	286	/* ISA IO space */
6d0f6bcf JCPV	287	#define CONFIG_SYS_IBAT2L (CONFIG_SYS_ISA_IO \| BATL_RW \| BATL_CACHEINHIBIT)
	288	#define CONFIG_SYS_IBAT2U (CONFIG_SYS_ISA_IO \| BATU_BL_16M \| BATU_VS \| BATU_VP)
	289	#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
	290	#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
e2211743 WD	291
e2211743 WD	292	/* ISA memory space */
6d0f6bcf JCPV	293	#define CONFIG_SYS_IBAT3L (CONFIG_SYS_ISA_MEM \| BATL_RW \| BATL_CACHEINHIBIT)
	294	#define CONFIG_SYS_IBAT3U (CONFIG_SYS_ISA_MEM \| BATU_BL_16M \| BATU_VS \| BATU_VP)
	295	#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
	296	#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
e2211743 WD	297
	298	#endif
	299
	300	/*
	301	* Speed settings are board specific
	302	*/
ee80fa7b WD	303	#define CONFIG_SYS_BUS_CLK 100000000
ee80fa7b WD	304	#define CONFIG_SYS_CPU_CLK 400000000
e2211743 WD	305
	306	/*
	307	* For booting Linux, the board info and command line data
	308	* have to be in the first 8 MB of memory, since this is
	309	* the maximum mapped by the Linux kernel during initialization.
	310	*/
6d0f6bcf	311	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
e2211743 WD	312
	313	/*
	314	* Cache Configuration
	315	*/
6d0f6bcf	316	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
dcaa7156	317	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	318	#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
e2211743 WD	319	#endif
	320
	321	/*
	322	* L2CR setup -- make sure this is right for your board!
1d0350ed	323	* look in include/74xx_7xx.h for the defines used here
e2211743 WD	324	*/
e2211743 WD	325
6d0f6bcf	326	#define CONFIG_SYS_L2
e2211743 WD	327
	328	#if 1
	329	#define L2_INIT 0 /* cpu 750 CXe*/
	330	#else
	331	#define L2_INIT (L2CR_L2SIZ_2M \| L2CR_L2CLK_3 \| L2CR_L2RAM_BURST \| \
8bde7f77	332	L2CR_L2OH_5 \| L2CR_L2CTL \| L2CR_L2WT)
e2211743 WD	333	#endif
	334	#define L2_ENABLE (L2_INIT \| L2CR_L2E)
	335
e2211743	336	#define CONFIG_EEPRO100
6d0f6bcf	337	#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
e2211743 WD	338	#define CONFIG_EEPRO100_SROM_WRITE
	339
	340	#endif /* __CONFIG_H */