[people/ms/u-boot.git] / include / configs / FADS823.h

 /*
  * A collection of structures, addresses, and values associated with
  * the Motorola 860T FADS board.  Copied from the MBX stuff.
  * Magnus Damm added defines for 8xxrom and extended bd_info.
  * Helmut Buchsbaum added bitvalues for BCSRx
  *
  * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
  */

/*
 * 1999-nov-26: The FADS is using the following physical memorymap:
 *
 * ff020000 -> ff02ffff : pcmcia     io remapping
 * ff010000 -> ff01ffff : BCSR       connected to CS1, setup by U-Boot
 * ff000000 -> ff00ffff : IMAP       internal in the cpu
 * e0000000 -> f3ffffff : pcmcia     memory remapping by m8xx_pcmcia
 * fe000000 -> fe1fffff : flash      connected to CS0, setup by U-Boot
 * 00000000 -> nnnnnnnn : sdram/dram setup by U-Boot
*/

#define CFG_PCMCIA_IO_ADDR	0xff020000
#define CFG_PCMCIA_IO_SIZE	0x10000
#define CFG_PCMCIA_MEM_ADDR	0xe0000000
#define CFG_PCMCIA_MEM_SIZE	0x10000
#define CFG_IMMR		0xFF000000
#define	CFG_SDRAM_SIZE		(4<<20) /* standard FADS has 4M */
#define	CFG_SDRAM_BASE		0x00000000
#define CFG_FLASH_BASE		0x02800000
#define BCSR_ADDR		((uint) 0xff010000)
#define FLASH_BASE0_PRELIM	0x02800000	/* FLASH bank #0	*/

/* ------------------------------------------------------------------------- */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define	CONFIG_ETHADDR		08:00:22:50:70:63	/* Ethernet address */
#define CONFIG_ENV_OVERWRITE	1	/* Overwrite the environment */

#define CONFIG_VIDEO		1	/* To enable video controller support */
#define CONFIG_HARD_I2C		1	/* To I2C with hardware support */
#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
#define CFG_I2C_SLAVE		0x7F

/*Now included by CFG_CMD_PCMCIA */
/*#define CONFIG_PCMCIA		1	/ * To enable PCMCIA support */

/* Video related */

#define CONFIG_VIDEO_LOGO			1	/* Show the logo */
#define CONFIG_VIDEO_ENCODER_AD7176		1	/* Enable this encoder */
#define CONFIG_VIDEO_ENCODER_AD7176_ADDR	0x54	/* Default on fads */
#define CONFIG_VIDEO_SIZE			(2*1024*1024)
/* #define CONFIG_VIDEO_ADDR (gd->bd->bi_memsize - CONFIG_VIDEO_SIZE) Frame buffer address */

/* Wireless 56Khz 4PPM keyboard on SMCx */

/*#define CONFIG_KEYBOARD		1 */
#define CONFIG_WL_4PPM_KEYBOARD_SMC	0	/* SMC to use (0 indexed) */

/*
 * High Level Configuration Options
 * (easy to change)
 */
#include <mpc8xx_irq.h>

#define CONFIG_MPC823		1
#define CONFIG_MPC823FADS	1
#define CONFIG_FADS		1

#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
#undef	CONFIG_8xx_CONS_SMC2
#undef	CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE		115200

/* Set the CPU speed to 50Mhz on the FADS */

#if 0
#define MPC8XX_FACT	10			/* Multiply by 10		*/
#define MPC8XX_XIN	5000000			/* 5 MHz in	*/
#else
#define MPC8XX_FACT	10			/* Multiply by 10 */
#define MPC8XX_XIN	5000000			/* 5 MHz in */
#define CFG_PLPRCR_MF	(MPC8XX_FACT-1) << 20	/* From 0 to 4095 */
#endif
#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))

#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */

#if 1
#define CONFIG_BOOTDELAY	2	/* autoboot after 2 seconds	*/
#define CONFIG_LOADS_ECHO	0	/* Dont echoes received characters */
#define CONFIG_BOOTARGS		""
#define CONFIG_BOOTCOMMAND							\
"bootp ;" 									\
"setenv bootargs console=tty0 console=ttyS0 " 					\
"root=/dev/nfs nfsroot=$(serverip):$(rootpath) " 				\
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname):eth0:off ;" 	\
"bootm"
#else
#define CONFIG_BOOTDELAY	0	/* autoboot disabled		*/
#endif

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

#define CONFIG_BOOTP_MASK	CONFIG_BOOTP_ALL

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

/*
 * Miscellaneous configurable options
 */
#define	CFG_LONGHELP				/* undef to save memory		*/
#define	CFG_PROMPT		":>"		/* Monitor Command Prompt	*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define	CFG_CBSIZE		1024		/* Console I/O Buffer Size	*/
#else
#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
#endif
#define	CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define	CFG_MAXARGS		16		/* max number of command args	*/
#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x00004000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x01000000	/* 0 ... 16 MB in DRAM	*/

#define CFG_LOAD_ADDR		0x00100000	/* default load address */

#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/

#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CFG_IMMR_SIZE		((uint)(64 * 1024))

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CFG_INIT_RAM_ADDR	CFG_IMMR
#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
#define	CFG_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 * Also NOTE that it doesn't mean SDRAM - it means MEMORY.
 */
#define CFG_FLASH_SIZE		((uint)(8 * 1024 * 1024))	/* max 8Mbyte */
#if 0
#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#else
#define	CFG_MONITOR_LEN		(512 << 10)	/* Reserve 512 kB for Monitor	*/
#endif
#define CFG_MONITOR_BASE	CFG_FLASH_BASE
#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	8	/* max number of sectors on one chip	*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define	CFG_ENV_IS_IN_FLASH	1
#define CFG_ENV_OFFSET		0x00040000	/* Offset of Environment Sector */
#define	CFG_ENV_SIZE		0x40000	/* Total Size of Environment Sector	*/

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control					11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if defined(CONFIG_WATCHDOG)
#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
#else
#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration						11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control					11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CFG_PISCR	(PISCR_PS | PISCR_PITF)

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register	15-30
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer  *
 * interrupt status bit - leave PLL multiplication factor unchanged !
 */
#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | CFG_PLPRCR_MF)

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	SCCR_EBDF11
#define CFG_SCCR       (SCCR_TBS     | \
				SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
				SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
				SCCR_DFALCD00)

 /*-----------------------------------------------------------------------
 *
 *-----------------------------------------------------------------------
 *
 */
#define CFG_DER		0

/* Because of the way the 860 starts up and assigns CS0 the
* entire address space, we have to set the memory controller
* differently.  Normally, you write the option register
* first, and then enable the chip select by writing the
* base register.  For CS0, you must write the base register
* first, followed by the option register.
*/

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */
/* the other CS:s are determined by looking at parameters in BCSRx */

#define BCSR_SIZE		((uint)(64 * 1024))

#define FLASH_BASE1_PRELIM	0x00000000	/* FLASH bank #1	*/

#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
#define CFG_PRELIM_OR_AM	0xFFE00000	/* OR addr mask */

/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0	*/
#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)

#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)   /* 1 Mbyte until detected and only 1 Mbyte is needed*/
#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )

/* BCSRx - Board Control and Status Registers */
#define CFG_OR1_REMAP	CFG_OR0_REMAP
#define CFG_OR1_PRELIM	0xffff8110									/* 64Kbyte address space */
#define CFG_BR1_PRELIM	((BCSR_ADDR) | BR_V )


/*
 * Memory Periodic Timer Prescaler
 */

/* periodic timer for refresh */
#define CFG_MAMR_PTA		97		/* start with divider for 100 MHz	*/

/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/

/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/

/*
 * MAMR settings for SDRAM
 */

/* 8 column SDRAM */
#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
/* 9 column SDRAM */
#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)

#define CFG_MAMR		0x13a01114
/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define	BOOTFLAG_COLD			0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM			0x02		/* Software reboot			*/

/* values according to the manual */

#define	BCSR0			((uint) (BCSR_ADDR + 00))
#define	BCSR1			((uint) (BCSR_ADDR + 0x04))
#define	BCSR2			((uint) (BCSR_ADDR + 0x08))
#define	BCSR3			((uint) (BCSR_ADDR + 0x0c))
#define	BCSR4			((uint) (BCSR_ADDR + 0x10))

/* FADS bitvalues by Helmut Buchsbaum
 * see MPC8xxADS User's Manual for a proper description
 * of the following structures
 */

#define BCSR0_ERB       ((uint)0x80000000)
#define BCSR0_IP        ((uint)0x40000000)
#define BCSR0_BDIS      ((uint)0x10000000)
#define BCSR0_BPS_MASK  ((uint)0x0C000000)
#define BCSR0_ISB_MASK  ((uint)0x01800000)
#define BCSR0_DBGC_MASK ((uint)0x00600000)
#define BCSR0_DBPC_MASK ((uint)0x00180000)
#define BCSR0_EBDF_MASK ((uint)0x00060000)

#define BCSR1_FLASH_EN           ((uint)0x80000000)
#define BCSR1_DRAM_EN            ((uint)0x40000000)
#define BCSR1_ETHEN              ((uint)0x20000000)
#define BCSR1_IRDEN              ((uint)0x10000000)
#define BCSR1_FLASH_CFG_EN       ((uint)0x08000000)
#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
#define BCSR1_BCSR_EN            ((uint)0x02000000)
#define BCSR1_RS232EN_1          ((uint)0x01000000)
#define BCSR1_PCCEN              ((uint)0x00800000)
#define BCSR1_PCCVCC0            ((uint)0x00400000)
#define BCSR1_PCCVPP_MASK        ((uint)0x00300000)
#define BCSR1_DRAM_HALF_WORD     ((uint)0x00080000)
#define BCSR1_RS232EN_2          ((uint)0x00040000)
#define BCSR1_SDRAM_EN           ((uint)0x00020000)
#define BCSR1_PCCVCC1            ((uint)0x00010000)

#define BCSR2_FLASH_PD_MASK      ((uint)0xF0000000)
#define BCSR2_DRAM_PD_MASK       ((uint)0x07800000)
#define BCSR2_DRAM_PD_SHIFT      (23)
#define BCSR2_EXTTOLI_MASK       ((uint)0x00780000)
#define BCSR2_DBREVNR_MASK       ((uint)0x00030000)

#define BCSR3_DBID_MASK          ((ushort)0x3800)
#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
#define BCSR3_BREVNR0            ((ushort)0x0080)
#define BCSR3_FLASH_PD_MASK      ((ushort)0x0070)
#define BCSR3_BREVN1             ((ushort)0x0008)
#define BCSR3_BREVN2_MASK        ((ushort)0x0003)

#define BCSR4_ETHLOOP            ((uint)0x80000000)
#define BCSR4_TFPLDL             ((uint)0x40000000)
#define BCSR4_TPSQEL             ((uint)0x20000000)
#define BCSR4_SIGNAL_LAMP        ((uint)0x10000000)
#ifdef CONFIG_MPC823
#define BCSR4_USB_EN             ((uint)0x08000000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC860SAR
#define BCSR4_UTOPIA_EN          ((uint)0x08000000)
#endif /* CONFIG_MPC860SAR */
#ifdef CONFIG_MPC860T
#define BCSR4_FETH_EN            ((uint)0x08000000)
#endif /* CONFIG_MPC860T */
#ifdef CONFIG_MPC823
#define BCSR4_USB_SPEED          ((uint)0x04000000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC860T
#define BCSR4_FETHCFG0           ((uint)0x04000000)
#endif /* CONFIG_MPC860T */
#ifdef CONFIG_MPC823
#define BCSR4_VCCO               ((uint)0x02000000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC860T
#define BCSR4_FETHFDE            ((uint)0x02000000)
#endif /* CONFIG_MPC860T */
#ifdef CONFIG_MPC823
#define BCSR4_VIDEO_ON           ((uint)0x00800000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC823
#define BCSR4_VDO_EKT_CLK_EN     ((uint)0x00400000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC860T
#define BCSR4_FETHCFG1           ((uint)0x00400000)
#endif /* CONFIG_MPC860T */
#ifdef CONFIG_MPC823
#define BCSR4_VIDEO_RST          ((uint)0x00200000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC860T
#define BCSR4_FETHRST            ((uint)0x00200000)
#endif /* CONFIG_MPC860T */
#ifdef CONFIG_MPC823
#define BCSR4_MODEM_EN           ((uint)0x00100000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC823
#define BCSR4_DATA_VOICE         ((uint)0x00080000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC850
#define BCSR4_DATA_VOICE         ((uint)0x00080000)
#endif /* CONFIG_MPC850 */

#define CONFIG_DRAM_50MHZ		1
#define CONFIG_SDRAM_50MHZ

#ifdef CONFIG_MPC860T

/* Interrupt level assignments.
*/
#define FEC_INTERRUPT	SIU_LEVEL1	/* FEC interrupt */

#endif /* CONFIG_MPC860T */

/* We don't use the 8259.
*/
#define NR_8259_INTS	0

/* Machine type
*/
#define _MACH_8xx (_MACH_fads)

/*
 * MPC8xx CPM Options
 */
#define CONFIG_SCC_ENET 1
#define CONFIG_SCC2_ENET 1
#undef  CONFIG_FEC_ENET
#undef  CONFIG_CPM_IIC
#undef  CONFIG_UCODE_PATCH

#define CONFIG_DISK_SPINUP_TIME 1000000

/* PCMCIA configuration */

#define PCMCIA_MAX_SLOTS    1

#ifdef CONFIG_MPC860
#define PCMCIA_SLOT_A 1
#endif

#endif	/* __CONFIG_H */
Commit	Line	Data
5b1d7137 WD	1	/*
	2	* A collection of structures, addresses, and values associated with
	3	* the Motorola 860T FADS board. Copied from the MBX stuff.
	4	* Magnus Damm added defines for 8xxrom and extended bd_info.
	5	* Helmut Buchsbaum added bitvalues for BCSRx
	6	*
	7	* Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
	8	*/
	9
	10	/*
	11	* 1999-nov-26: The FADS is using the following physical memorymap:
	12	*
	13	* ff020000 -> ff02ffff : pcmcia io remapping
	14	* ff010000 -> ff01ffff : BCSR connected to CS1, setup by U-Boot
	15	* ff000000 -> ff00ffff : IMAP internal in the cpu
	16	* e0000000 -> f3ffffff : pcmcia memory remapping by m8xx_pcmcia
	17	* fe000000 -> fe1fffff : flash connected to CS0, setup by U-Boot
	18	* 00000000 -> nnnnnnnn : sdram/dram setup by U-Boot
	19	*/
	20
	21	#define CFG_PCMCIA_IO_ADDR 0xff020000
	22	#define CFG_PCMCIA_IO_SIZE 0x10000
	23	#define CFG_PCMCIA_MEM_ADDR 0xe0000000
	24	#define CFG_PCMCIA_MEM_SIZE 0x10000
	25	#define CFG_IMMR 0xFF000000
2535d602	26	#define CFG_SDRAM_SIZE (4<<20) /* standard FADS has 4M */
5b1d7137 WD	27	#define CFG_SDRAM_BASE 0x00000000
	28	#define CFG_FLASH_BASE 0x02800000
	29	#define BCSR_ADDR ((uint) 0xff010000)
	30	#define FLASH_BASE0_PRELIM 0x02800000 /* FLASH bank #0 */
	31
	32	/* ------------------------------------------------------------------------- */
	33
	34	/*
	35	* board/config.h - configuration options, board specific
	36	*/
	37
	38	#ifndef __CONFIG_H
	39	#define __CONFIG_H
	40
	41	#define CONFIG_ETHADDR 08:00:22:50:70:63 /* Ethernet address */
	42	#define CONFIG_ENV_OVERWRITE 1 /* Overwrite the environment */
	43
	44	#define CONFIG_VIDEO 1 /* To enable video controller support */
	45	#define CONFIG_HARD_I2C 1 /* To I2C with hardware support */
	46	#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
	47	#define CFG_I2C_SLAVE 0x7F
	48
	49	/Now included by CFG_CMD_PCMCIA /
	50	/#define CONFIG_PCMCIA 1 / To enable PCMCIA support */
	51
	52	/* Video related */
	53
	54	#define CONFIG_VIDEO_LOGO 1 /* Show the logo */
	55	#define CONFIG_VIDEO_ENCODER_AD7176 1 /* Enable this encoder */
	56	#define CONFIG_VIDEO_ENCODER_AD7176_ADDR 0x54 /* Default on fads */
	57	#define CONFIG_VIDEO_SIZE (210241024)
	58	/* #define CONFIG_VIDEO_ADDR (gd->bd->bi_memsize - CONFIG_VIDEO_SIZE) Frame buffer address */
	59
	60	/* Wireless 56Khz 4PPM keyboard on SMCx */
	61
682011ff	62	/#define CONFIG_KEYBOARD 1 /
5b1d7137 WD	63	#define CONFIG_WL_4PPM_KEYBOARD_SMC 0 /* SMC to use (0 indexed) */
	64
	65	/*
	66	* High Level Configuration Options
	67	* (easy to change)
	68	*/
	69	#include <mpc8xx_irq.h>
	70
	71	#define CONFIG_MPC823 1
	72	#define CONFIG_MPC823FADS 1
	73	#define CONFIG_FADS 1
	74
	75	#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
	76	#undef CONFIG_8xx_CONS_SMC2
	77	#undef CONFIG_8xx_CONS_NONE
	78	#define CONFIG_BAUDRATE 115200
	79
	80	/* Set the CPU speed to 50Mhz on the FADS */
	81
	82	#if 0
	83	#define MPC8XX_FACT 10 /* Multiply by 10 */
	84	#define MPC8XX_XIN 5000000 /* 5 MHz in */
	85	#else
	86	#define MPC8XX_FACT 10 /* Multiply by 10 */
	87	#define MPC8XX_XIN 5000000 /* 5 MHz in */
	88	#define CFG_PLPRCR_MF (MPC8XX_FACT-1) << 20 /* From 0 to 4095 */
	89	#endif
	90	#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))
	91
	92	#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
	93
	94	#if 1
	95	#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */
	96	#define CONFIG_LOADS_ECHO 0 /* Dont echoes received characters */
	97	#define CONFIG_BOOTARGS ""
	98	#define CONFIG_BOOTCOMMAND \
	99	"bootp ;" \
	100	"setenv bootargs console=tty0 console=ttyS0 " \
	101	"root=/dev/nfs nfsroot=$(serverip):$(rootpath) " \
	102	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname):eth0:off ;" \
	103	"bootm"
	104	#else
	105	#define CONFIG_BOOTDELAY 0 /* autoboot disabled */
	106	#endif
	107
	108	#undef CONFIG_WATCHDOG /* watchdog disabled */
	109
	110	#define CONFIG_BOOTP_MASK CONFIG_BOOTP_ALL
	111
	112	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
	113	#include <cmd_confdefs.h>
	114
	115	/*
	116	* Miscellaneous configurable options
	117	*/
	118	#define CFG_LONGHELP /* undef to save memory */
	119	#define CFG_PROMPT ":>" /* Monitor Command Prompt */
	120	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	121	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	122	#else
	123	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	124	#endif
	125	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	126	#define CFG_MAXARGS 16 /* max number of command args */
127	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
128
129	#define CFG_MEMTEST_START 0x00004000 /* memtest works on */
130	#define CFG_MEMTEST_END 0x01000000 /* 0 ... 16 MB in DRAM */
131
132	#define CFG_LOAD_ADDR 0x00100000 /* default load address */
133
134	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
135
136	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
137
138	/*
139	* Low Level Configuration Settings
140	* (address mappings, register initial values, etc.)
141	* You should know what you are doing if you make changes here.
142	*/
143	/*-----------------------------------------------------------------------
144	* Internal Memory Mapped Register
145	*/
146	#define CFG_IMMR_SIZE ((uint)(64 * 1024))
147
148	/*-----------------------------------------------------------------------
149	* Definitions for initial stack pointer and data area (in DPRAM)
150	*/
151	#define CFG_INIT_RAM_ADDR CFG_IMMR
152	#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
153	#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
154	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
155	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
156
157	/*-----------------------------------------------------------------------
158	* Start addresses for the final memory configuration
159	* (Set up by the startup code)
160	* Please note that CFG_SDRAM_BASE _must_ start at 0
161	* Also NOTE that it doesn't mean SDRAM - it means MEMORY.
162	*/
163	#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */
164	#if 0
165	#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
166	#else
167	#define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
168	#endif
169	#define CFG_MONITOR_BASE CFG_FLASH_BASE
170	#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
171
172	/*
173	* For booting Linux, the board info and command line data
174	* have to be in the first 8 MB of memory, since this is
175	* the maximum mapped by the Linux kernel during initialization.
176	*/
177	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
178	/*-----------------------------------------------------------------------
179	* FLASH organization
180	*/
181	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
182	#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
183
184	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
185	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
186
187	#define CFG_ENV_IS_IN_FLASH 1
188	#define CFG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */
189	#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
190
191	/*-----------------------------------------------------------------------
192	* Cache Configuration
193	*/
194	#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
195	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
196	#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
197	#endif
198
199	/*-----------------------------------------------------------------------
200	* SYPCR - System Protection Control 11-9
201	* SYPCR can only be written once after reset!
202	*-----------------------------------------------------------------------
203	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
204	*/
205	#if defined(CONFIG_WATCHDOG)
206	#define CFG_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
207	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
208	#else
209	#define CFG_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| SYPCR_SWP)
210	#endif
211
212	/*-----------------------------------------------------------------------
213	* SIUMCR - SIU Module Configuration 11-6
214	*-----------------------------------------------------------------------
215	* PCMCIA config., multi-function pin tri-state
216	*/
217	#define CFG_SIUMCR (SIUMCR_DBGC00 \| SIUMCR_DBPC00 \| SIUMCR_MLRC01)
218
219	/*-----------------------------------------------------------------------
220	* TBSCR - Time Base Status and Control 11-26
221	*-----------------------------------------------------------------------
222	* Clear Reference Interrupt Status, Timebase freezing enabled
223	*/
224	#define CFG_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBE)
225
226	/*-----------------------------------------------------------------------
227	* PISCR - Periodic Interrupt Status and Control 11-31
228	*-----------------------------------------------------------------------
229	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
230	*/
231	#define CFG_PISCR (PISCR_PS \| PISCR_PITF)
232
233	/*-----------------------------------------------------------------------
234	* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
235	*-----------------------------------------------------------------------
236	* Reset PLL lock status sticky bit, timer expired status bit and timer *
237	* interrupt status bit - leave PLL multiplication factor unchanged !
238	*/
239	#define CFG_PLPRCR (PLPRCR_SPLSS \| PLPRCR_TEXPS \| PLPRCR_TMIST \| CFG_PLPRCR_MF)
240
241	/*-----------------------------------------------------------------------
242	* SCCR - System Clock and reset Control Register 15-27
243	*-----------------------------------------------------------------------
244	* Set clock output, timebase and RTC source and divider,
245	* power management and some other internal clocks
246	*/
247	#define SCCR_MASK SCCR_EBDF11
248	#define CFG_SCCR (SCCR_TBS \| \
249	SCCR_COM00 \| SCCR_DFSYNC00 \| SCCR_DFBRG00 \| \
250	SCCR_DFNL000 \| SCCR_DFNH000 \| SCCR_DFLCD000 \| \
251	SCCR_DFALCD00)
252
253	/*-----------------------------------------------------------------------
254	*
255	*-----------------------------------------------------------------------
256	*
257	*/
258	#define CFG_DER 0
259
260	/* Because of the way the 860 starts up and assigns CS0 the
261	* entire address space, we have to set the memory controller
262	* differently. Normally, you write the option register
263	* first, and then enable the chip select by writing the
264	* base register. For CS0, you must write the base register
265	* first, followed by the option register.
266	*/
267
268	/*
269	* Init Memory Controller:
270	*
271	* BR0/1 and OR0/1 (FLASH)
272	*/
273	/* the other CS:s are determined by looking at parameters in BCSRx */
274
275	#define BCSR_SIZE ((uint)(64 * 1024))
276
277	#define FLASH_BASE1_PRELIM 0x00000000 /* FLASH bank #1 */
278
279	#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
280	#define CFG_PRELIM_OR_AM 0xFFE00000 /* OR addr mask */
281
282	/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
283	#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM \| OR_ACS_DIV4 \| OR_BI \| OR_SCY_3_CLK \| OR_TRLX)
284
285	#define CFG_OR0_REMAP (CFG_REMAP_OR_AM \| CFG_OR_TIMING_FLASH)
286	#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM \| CFG_OR_TIMING_FLASH) /* 1 Mbyte until detected and only 1 Mbyte is needed*/
287	#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) \| BR_V )
288
289	/* BCSRx - Board Control and Status Registers */
290	#define CFG_OR1_REMAP CFG_OR0_REMAP
291	#define CFG_OR1_PRELIM 0xffff8110 /* 64Kbyte address space */
292	#define CFG_BR1_PRELIM ((BCSR_ADDR) \| BR_V )
293
294
295	/*
296	* Memory Periodic Timer Prescaler
297	*/
298
299	/* periodic timer for refresh */
300	#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */
301
302	/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
303	#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
304	#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
305
306	/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
307	#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
308	#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
309
310	/*
311	* MAMR settings for SDRAM
312	*/
313
314	/* 8 column SDRAM */
315	#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
316	MAMR_AMA_TYPE_0 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A11 \| \
317	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
318	/* 9 column SDRAM */
319	#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
320	MAMR_AMA_TYPE_1 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A10 \| \
321	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
322
323	#define CFG_MAMR 0x13a01114
324	/*
325	* Internal Definitions
326	*
327	* Boot Flags
328	*/
329	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
330	#define BOOTFLAG_WARM 0x02 /* Software reboot */
331
332	/* values according to the manual */
333
334	#define BCSR0 ((uint) (BCSR_ADDR + 00))
335	#define BCSR1 ((uint) (BCSR_ADDR + 0x04))
336	#define BCSR2 ((uint) (BCSR_ADDR + 0x08))
337	#define BCSR3 ((uint) (BCSR_ADDR + 0x0c))
338	#define BCSR4 ((uint) (BCSR_ADDR + 0x10))
339
340	/* FADS bitvalues by Helmut Buchsbaum
341	* see MPC8xxADS User's Manual for a proper description
342	* of the following structures
343	*/
344
345	#define BCSR0_ERB ((uint)0x80000000)
346	#define BCSR0_IP ((uint)0x40000000)
347	#define BCSR0_BDIS ((uint)0x10000000)
348	#define BCSR0_BPS_MASK ((uint)0x0C000000)
349	#define BCSR0_ISB_MASK ((uint)0x01800000)
350	#define BCSR0_DBGC_MASK ((uint)0x00600000)
351	#define BCSR0_DBPC_MASK ((uint)0x00180000)
352	#define BCSR0_EBDF_MASK ((uint)0x00060000)
353
354	#define BCSR1_FLASH_EN ((uint)0x80000000)
355	#define BCSR1_DRAM_EN ((uint)0x40000000)
356	#define BCSR1_ETHEN ((uint)0x20000000)
357	#define BCSR1_IRDEN ((uint)0x10000000)
358	#define BCSR1_FLASH_CFG_EN ((uint)0x08000000)
359	#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
360	#define BCSR1_BCSR_EN ((uint)0x02000000)
361	#define BCSR1_RS232EN_1 ((uint)0x01000000)
362	#define BCSR1_PCCEN ((uint)0x00800000)
363	#define BCSR1_PCCVCC0 ((uint)0x00400000)
364	#define BCSR1_PCCVPP_MASK ((uint)0x00300000)
365	#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000)
366	#define BCSR1_RS232EN_2 ((uint)0x00040000)
367	#define BCSR1_SDRAM_EN ((uint)0x00020000)
368	#define BCSR1_PCCVCC1 ((uint)0x00010000)
369
370	#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000)
371	#define BCSR2_DRAM_PD_MASK ((uint)0x07800000)
372	#define BCSR2_DRAM_PD_SHIFT (23)
373	#define BCSR2_EXTTOLI_MASK ((uint)0x00780000)
374	#define BCSR2_DBREVNR_MASK ((uint)0x00030000)
375
376	#define BCSR3_DBID_MASK ((ushort)0x3800)
377	#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
378	#define BCSR3_BREVNR0 ((ushort)0x0080)
379	#define BCSR3_FLASH_PD_MASK ((ushort)0x0070)
380	#define BCSR3_BREVN1 ((ushort)0x0008)
381	#define BCSR3_BREVN2_MASK ((ushort)0x0003)
382
383	#define BCSR4_ETHLOOP ((uint)0x80000000)
384	#define BCSR4_TFPLDL ((uint)0x40000000)
385	#define BCSR4_TPSQEL ((uint)0x20000000)
386	#define BCSR4_SIGNAL_LAMP ((uint)0x10000000)
387	#ifdef CONFIG_MPC823
388	#define BCSR4_USB_EN ((uint)0x08000000)
389	#endif /* CONFIG_MPC823 */
390	#ifdef CONFIG_MPC860SAR
391	#define BCSR4_UTOPIA_EN ((uint)0x08000000)
392	#endif /* CONFIG_MPC860SAR */
393	#ifdef CONFIG_MPC860T
394	#define BCSR4_FETH_EN ((uint)0x08000000)
395	#endif /* CONFIG_MPC860T */
396	#ifdef CONFIG_MPC823
397	#define BCSR4_USB_SPEED ((uint)0x04000000)
398	#endif /* CONFIG_MPC823 */
399	#ifdef CONFIG_MPC860T
400	#define BCSR4_FETHCFG0 ((uint)0x04000000)
401	#endif /* CONFIG_MPC860T */
402	#ifdef CONFIG_MPC823
403	#define BCSR4_VCCO ((uint)0x02000000)
404	#endif /* CONFIG_MPC823 */
405	#ifdef CONFIG_MPC860T
406	#define BCSR4_FETHFDE ((uint)0x02000000)
407	#endif /* CONFIG_MPC860T */
408	#ifdef CONFIG_MPC823
409	#define BCSR4_VIDEO_ON ((uint)0x00800000)
410	#endif /* CONFIG_MPC823 */
411	#ifdef CONFIG_MPC823
412	#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000)
413	#endif /* CONFIG_MPC823 */
414	#ifdef CONFIG_MPC860T
415	#define BCSR4_FETHCFG1 ((uint)0x00400000)
416	#endif /* CONFIG_MPC860T */
417	#ifdef CONFIG_MPC823
418	#define BCSR4_VIDEO_RST ((uint)0x00200000)
419	#endif /* CONFIG_MPC823 */
420	#ifdef CONFIG_MPC860T
421	#define BCSR4_FETHRST ((uint)0x00200000)
422	#endif /* CONFIG_MPC860T */
423	#ifdef CONFIG_MPC823
424	#define BCSR4_MODEM_EN ((uint)0x00100000)
425	#endif /* CONFIG_MPC823 */
426	#ifdef CONFIG_MPC823
427	#define BCSR4_DATA_VOICE ((uint)0x00080000)
428	#endif /* CONFIG_MPC823 */
429	#ifdef CONFIG_MPC850
430	#define BCSR4_DATA_VOICE ((uint)0x00080000)
431	#endif /* CONFIG_MPC850 */
432
433	#define CONFIG_DRAM_50MHZ 1
434	#define CONFIG_SDRAM_50MHZ
435
436	#ifdef CONFIG_MPC860T
437
438	/* Interrupt level assignments.
439	*/
440	#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */
441
442	#endif /* CONFIG_MPC860T */
443
444	/* We don't use the 8259.
445	*/
446	#define NR_8259_INTS 0
447
448	/* Machine type
449	*/
450	#define _MACH_8xx (_MACH_fads)
451
452	/*
453	* MPC8xx CPM Options
454	*/
455	#define CONFIG_SCC_ENET 1
456	#define CONFIG_SCC2_ENET 1
457	#undef CONFIG_FEC_ENET
458	#undef CONFIG_CPM_IIC
459	#undef CONFIG_UCODE_PATCH
460
461	#define CONFIG_DISK_SPINUP_TIME 1000000
462
463	/* PCMCIA configuration */
464
465	#define PCMCIA_MAX_SLOTS 1
466
467	#ifdef CONFIG_MPC860
468	#define PCMCIA_SLOT_A 1
469	#endif
470
471	#endif /* __CONFIG_H */