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13fdf8a6 SR |
1 | /* |
2 | * (C) Copyright 2001-2003 | |
3 | * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * board/config.h - configuration options, board specific | |
26 | */ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
31 | /* | |
32 | * High Level Configuration Options | |
33 | * (easy to change) | |
34 | */ | |
35 | ||
36 | #define CONFIG_405EP 1 /* This is a PPC405 CPU */ | |
c837dcb1 | 37 | #define CONFIG_4xx 1 /* ...member of PPC4xx family */ |
a20b27a3 | 38 | #define CONFIG_HUB405 1 /* ...on a HUB405 board */ |
13fdf8a6 | 39 | |
c837dcb1 WD |
40 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ |
41 | #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ | |
13fdf8a6 | 42 | |
a20b27a3 | 43 | #define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ |
13fdf8a6 | 44 | |
47b1e3d7 SR |
45 | #define CONFIG_BOARD_TYPES 1 /* support board types */ |
46 | ||
13fdf8a6 SR |
47 | #define CONFIG_BAUDRATE 9600 |
48 | #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ | |
49 | ||
50 | #undef CONFIG_BOOTARGS | |
a20b27a3 SR |
51 | #undef CONFIG_BOOTCOMMAND |
52 | ||
53 | #define CONFIG_PREBOOT /* enable preboot variable */ | |
54 | ||
6d0f6bcf | 55 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
13fdf8a6 | 56 | |
96e21f86 | 57 | #define CONFIG_PPC4xx_EMAC |
13fdf8a6 | 58 | #define CONFIG_MII 1 /* MII PHY management */ |
c837dcb1 | 59 | #define CONFIG_PHY_ADDR 0 /* PHY address */ |
a20b27a3 SR |
60 | #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ |
61 | ||
62 | #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ | |
13fdf8a6 | 63 | |
6c4f4da9 | 64 | |
11799434 JL |
65 | /* |
66 | * BOOTP options | |
67 | */ | |
68 | #define CONFIG_BOOTP_BOOTFILESIZE | |
69 | #define CONFIG_BOOTP_BOOTPATH | |
70 | #define CONFIG_BOOTP_GATEWAY | |
71 | #define CONFIG_BOOTP_HOSTNAME | |
72 | ||
73 | ||
6c4f4da9 JL |
74 | /* |
75 | * Command line configuration. | |
76 | */ | |
77 | #include <config_cmd_default.h> | |
78 | ||
79 | #define CONFIG_CMD_DHCP | |
80 | #define CONFIG_CMD_IRQ | |
81 | #define CONFIG_CMD_ELF | |
82 | #define CONFIG_CMD_NAND | |
83 | #define CONFIG_CMD_I2C | |
84 | #define CONFIG_CMD_MII | |
85 | #define CONFIG_CMD_PING | |
86 | #define CONFIG_CMD_EEPROM | |
87 | ||
13fdf8a6 | 88 | |
c837dcb1 | 89 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
13fdf8a6 | 90 | |
c837dcb1 | 91 | #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ |
13fdf8a6 SR |
92 | |
93 | /* | |
94 | * Miscellaneous configurable options | |
95 | */ | |
6d0f6bcf JCPV |
96 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
97 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
13fdf8a6 | 98 | |
6d0f6bcf JCPV |
99 | #undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ |
100 | #ifdef CONFIG_SYS_HUSH_PARSER | |
101 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
13fdf8a6 SR |
102 | #endif |
103 | ||
6c4f4da9 | 104 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 105 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
13fdf8a6 | 106 | #else |
6d0f6bcf | 107 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
13fdf8a6 | 108 | #endif |
6d0f6bcf JCPV |
109 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
110 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
111 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
13fdf8a6 | 112 | |
6d0f6bcf | 113 | #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ |
13fdf8a6 | 114 | |
6d0f6bcf | 115 | #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ |
13fdf8a6 | 116 | |
6d0f6bcf JCPV |
117 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
118 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
13fdf8a6 | 119 | |
6d0f6bcf | 120 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ |
6d0f6bcf | 121 | #define CONFIG_SYS_BASE_BAUD 691200 |
c837dcb1 | 122 | #undef CONFIG_UART1_CONSOLE /* define for uart1 as console */ |
13fdf8a6 SR |
123 | |
124 | /* The following table includes the supported baudrates */ | |
6d0f6bcf | 125 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
13fdf8a6 SR |
126 | { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ |
127 | 57600, 115200, 230400, 460800, 921600 } | |
128 | ||
6d0f6bcf JCPV |
129 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
130 | #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
13fdf8a6 | 131 | |
6d0f6bcf | 132 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
13fdf8a6 SR |
133 | |
134 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ | |
135 | ||
c837dcb1 | 136 | #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ |
13fdf8a6 | 137 | |
6d0f6bcf | 138 | #define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ |
13fdf8a6 | 139 | |
a20b27a3 SR |
140 | /* Ethernet stuff */ |
141 | #define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */ | |
142 | #define CONFIG_ETHADDR 00:50:C2:1E:AF:FE | |
e2ffd59b | 143 | #define CONFIG_HAS_ETH1 |
a20b27a3 SR |
144 | #define CONFIG_ETH1ADDR 00:50:C2:1E:AF:FD |
145 | ||
13fdf8a6 SR |
146 | /*----------------------------------------------------------------------- |
147 | * NAND-FLASH stuff | |
148 | *----------------------------------------------------------------------- | |
149 | */ | |
6d0f6bcf | 150 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } |
6d0f6bcf | 151 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ |
bd84ee4c MF |
152 | #define NAND_BIG_DELAY_US 25 |
153 | ||
6d0f6bcf JCPV |
154 | #define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ |
155 | #define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ | |
156 | #define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ | |
157 | #define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ | |
13fdf8a6 | 158 | |
6d0f6bcf JCPV |
159 | #define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ |
160 | #define CONFIG_SYS_NAND_QUIET 1 | |
a20b27a3 | 161 | |
13fdf8a6 SR |
162 | /*----------------------------------------------------------------------- |
163 | * PCI stuff | |
164 | *----------------------------------------------------------------------- | |
165 | */ | |
c837dcb1 WD |
166 | #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ |
167 | #define PCI_HOST_FORCE 1 /* configure as pci host */ | |
168 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ | |
169 | ||
170 | #undef CONFIG_PCI /* include pci support */ | |
171 | #define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */ | |
172 | #undef CONFIG_PCI_PNP /* do pci plug-and-play */ | |
173 | /* resource configuration */ | |
174 | ||
175 | #undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ | |
176 | ||
6d0f6bcf JCPV |
177 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ |
178 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ | |
179 | #define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ | |
180 | #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ | |
181 | #define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ | |
182 | #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ | |
183 | #define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ | |
184 | #define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ | |
185 | #define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ | |
13fdf8a6 SR |
186 | |
187 | /*----------------------------------------------------------------------- | |
188 | * Start addresses for the final memory configuration | |
189 | * (Set up by the startup code) | |
6d0f6bcf | 190 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
13fdf8a6 | 191 | */ |
6d0f6bcf JCPV |
192 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
193 | #define CONFIG_SYS_FLASH_BASE 0xFFFC0000 | |
194 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
195 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ | |
196 | #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ | |
13fdf8a6 SR |
197 | |
198 | /* | |
199 | * For booting Linux, the board info and command line data | |
200 | * have to be in the first 8 MB of memory, since this is | |
201 | * the maximum mapped by the Linux kernel during initialization. | |
202 | */ | |
6d0f6bcf | 203 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
13fdf8a6 SR |
204 | /*----------------------------------------------------------------------- |
205 | * FLASH organization | |
206 | */ | |
6d0f6bcf JCPV |
207 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
208 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ | |
13fdf8a6 | 209 | |
6d0f6bcf JCPV |
210 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
211 | #define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ | |
13fdf8a6 | 212 | |
6d0f6bcf JCPV |
213 | #define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ |
214 | #define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ | |
215 | #define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ | |
13fdf8a6 SR |
216 | /* |
217 | * The following defines are added for buggy IOP480 byte interface. | |
218 | * All other boards should use the standard values (CPCI405 etc.) | |
219 | */ | |
6d0f6bcf JCPV |
220 | #define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ |
221 | #define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ | |
222 | #define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ | |
13fdf8a6 | 223 | |
6d0f6bcf | 224 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
13fdf8a6 SR |
225 | |
226 | #if 0 /* test-only */ | |
6d0f6bcf JCPV |
227 | #define CONFIG_SYS_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ |
228 | #define CONFIG_SYS_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ | |
13fdf8a6 SR |
229 | #endif |
230 | ||
231 | /*----------------------------------------------------------------------- | |
232 | * Environment Variable setup | |
233 | */ | |
bb1f8b4f | 234 | #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
0e8d1586 JCPV |
235 | #define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ |
236 | #define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ | |
13fdf8a6 SR |
237 | /* total size of a CAT24WC16 is 2048 bytes */ |
238 | ||
6d0f6bcf JCPV |
239 | #define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ |
240 | #define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */ | |
13fdf8a6 SR |
241 | |
242 | /*----------------------------------------------------------------------- | |
243 | * I2C EEPROM (CAT24WC16) for environment | |
244 | */ | |
245 | #define CONFIG_HARD_I2C /* I2c with hardware support */ | |
6d0f6bcf JCPV |
246 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
247 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
13fdf8a6 | 248 | |
6d0f6bcf JCPV |
249 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ |
250 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ | |
c837dcb1 | 251 | /* mask of address bits that overflow into the "EEPROM chip address" */ |
6d0f6bcf JCPV |
252 | #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 |
253 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ | |
13fdf8a6 | 254 | /* 16 byte page write mode using*/ |
c837dcb1 | 255 | /* last 4 bits of the address */ |
6d0f6bcf | 256 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
13fdf8a6 | 257 | |
13fdf8a6 SR |
258 | /* |
259 | * Init Memory Controller: | |
260 | * | |
261 | * BR0/1 and OR0/1 (FLASH) | |
262 | */ | |
263 | ||
264 | #define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ | |
265 | ||
266 | /*----------------------------------------------------------------------- | |
267 | * External Bus Controller (EBC) Setup | |
268 | */ | |
269 | ||
c837dcb1 | 270 | /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ |
6d0f6bcf JCPV |
271 | #define CONFIG_SYS_EBC_PB0AP 0x92015480 |
272 | /*#define CONFIG_SYS_EBC_PB0AP 0x08055880 /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */ | |
273 | #define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ | |
13fdf8a6 | 274 | |
c837dcb1 | 275 | /* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */ |
6d0f6bcf JCPV |
276 | #define CONFIG_SYS_EBC_PB1AP 0x92015480 |
277 | #define CONFIG_SYS_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */ | |
13fdf8a6 | 278 | |
c837dcb1 | 279 | /* Memory Bank 2 (8 Bit Peripheral: UART) initialization */ |
13fdf8a6 | 280 | #if 0 |
6d0f6bcf JCPV |
281 | #define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ |
282 | #define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ | |
13fdf8a6 | 283 | #else |
6d0f6bcf JCPV |
284 | #define CONFIG_SYS_EBC_PB2AP 0x92015480 |
285 | #define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ | |
13fdf8a6 SR |
286 | #endif |
287 | ||
c837dcb1 WD |
288 | #define DUART0_BA 0xF0000000 /* DUART Base Address */ |
289 | #define DUART1_BA 0xF0000008 /* DUART Base Address */ | |
290 | #define DUART2_BA 0xF0000010 /* DUART Base Address */ | |
291 | #define DUART3_BA 0xF0000018 /* DUART Base Address */ | |
6d0f6bcf | 292 | #define CONFIG_SYS_NAND_BASE 0xF4000000 |
13fdf8a6 SR |
293 | |
294 | /*----------------------------------------------------------------------- | |
295 | * FPGA stuff | |
296 | */ | |
6d0f6bcf JCPV |
297 | #define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ |
298 | #define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/ | |
13fdf8a6 SR |
299 | |
300 | /* FPGA program pin configuration */ | |
6d0f6bcf JCPV |
301 | #define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ |
302 | #define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ | |
303 | #define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ | |
304 | #define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ | |
305 | #define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ | |
13fdf8a6 SR |
306 | |
307 | /*----------------------------------------------------------------------- | |
308 | * Definitions for initial stack pointer and data area (in data cache) | |
309 | */ | |
310 | /* use on chip memory ( OCM ) for temperary stack until sdram is tested */ | |
6d0f6bcf | 311 | #define CONFIG_SYS_TEMP_STACK_OCM 1 |
13fdf8a6 SR |
312 | |
313 | /* On Chip Memory location */ | |
6d0f6bcf JCPV |
314 | #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 |
315 | #define CONFIG_SYS_OCM_DATA_SIZE 0x1000 | |
316 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ | |
317 | #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */ | |
13fdf8a6 | 318 | |
6d0f6bcf JCPV |
319 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
320 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
321 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
13fdf8a6 SR |
322 | |
323 | /*----------------------------------------------------------------------- | |
324 | * Definitions for GPIO setup (PPC405EP specific) | |
325 | * | |
c837dcb1 WD |
326 | * GPIO0[0] - External Bus Controller BLAST output |
327 | * GPIO0[1-9] - Instruction trace outputs -> GPIO | |
13fdf8a6 SR |
328 | * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs |
329 | * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO | |
330 | * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs | |
331 | * GPIO0[24-27] - UART0 control signal inputs/outputs | |
332 | * GPIO0[28-29] - UART1 data signal input/output | |
333 | * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs | |
334 | */ | |
6d0f6bcf JCPV |
335 | #define CONFIG_SYS_GPIO0_OSRH 0x40000550 |
336 | #define CONFIG_SYS_GPIO0_OSRL 0x00000110 | |
337 | #define CONFIG_SYS_GPIO0_ISR1H 0x00000000 | |
338 | #define CONFIG_SYS_GPIO0_ISR1L 0x15555445 | |
339 | #define CONFIG_SYS_GPIO0_TSRH 0x00000000 | |
340 | #define CONFIG_SYS_GPIO0_TSRL 0x00000000 | |
341 | #define CONFIG_SYS_GPIO0_TCR 0xF7FE0014 | |
342 | ||
343 | #define CONFIG_SYS_DUART_RST (0x80000000 >> 14) | |
344 | #define CONFIG_SYS_UART2_RS232 (0x80000000 >> 5) | |
345 | #define CONFIG_SYS_UART3_RS232 (0x80000000 >> 6) | |
346 | #define CONFIG_SYS_UART4_RS232 (0x80000000 >> 7) | |
347 | #define CONFIG_SYS_UART5_RS232 (0x80000000 >> 8) | |
13fdf8a6 SR |
348 | |
349 | /* | |
350 | * Internal Definitions | |
351 | * | |
352 | * Boot Flags | |
353 | */ | |
354 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
355 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
356 | ||
357 | /* | |
358 | * Default speed selection (cpu_plb_opb_ebc) in mhz. | |
359 | * This value will be set if iic boot eprom is disabled. | |
360 | */ | |
361 | #if 0 | |
c837dcb1 WD |
362 | #define PLLMR0_DEFAULT PLLMR0_266_133_66_33 |
363 | #define PLLMR1_DEFAULT PLLMR1_266_133_66_33 | |
13fdf8a6 SR |
364 | #endif |
365 | #if 0 | |
c837dcb1 WD |
366 | #define PLLMR0_DEFAULT PLLMR0_200_100_50_33 |
367 | #define PLLMR1_DEFAULT PLLMR1_200_100_50_33 | |
13fdf8a6 SR |
368 | #endif |
369 | #if 1 | |
c837dcb1 WD |
370 | #define PLLMR0_DEFAULT PLLMR0_133_66_66_33 |
371 | #define PLLMR1_DEFAULT PLLMR1_133_66_66_33 | |
13fdf8a6 SR |
372 | #endif |
373 | ||
374 | #endif /* __CONFIG_H */ |