[people/ms/u-boot.git] / include / configs / IDS8247.h

/*
 * (C) Copyright 2005
 * Heiko Schocher, DENX Software Engineering, <hs@denx.de>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC8260		1	/* This is a MPC8260 CPU		*/
#define CONFIG_MPC8272_FAMILY	1
#define CONFIG_IDS8247		1
#define CPU_ID_STR		"MPC8247"
#define CONFIG_CPM2		1	/* Has a CPM2 */

#define	CONFIG_SYS_TEXT_BASE	0xfff00000

#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/

#define	CONFIG_BOOTCOUNT_LIMIT

#define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"

#undef	CONFIG_BOOTARGS

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw "			\
	"console=ttyS0,115200\0"					\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"flash_nfs=run nfsargs addip;"					\
		"bootm ${kernel_addr}\0"				\
	"flash_self=run ramargs addip;"					\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
	"rootpath=/opt/eldk/ppc_82xx\0"					\
	"bootfile=/tftpboot/IDS8247/uImage\0"				\
	"kernel_addr=ff800000\0"					\
	"ramdisk_addr=ffa00000\0"					\
	""
#define CONFIG_BOOTCOMMAND	"run flash_self"

#define CONFIG_MISC_INIT_R	1

/* enable I2C and select the hardware/software driver */
#undef  CONFIG_HARD_I2C			/* I2C with hardware support	*/
#define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
#define CONFIG_SYS_I2C_SLAVE		0x7F

/*
 * Software (bit-bang) I2C driver configuration
 */

#define I2C_PORT	0		/* Port A=0, B=1, C=2, D=3 */
#define I2C_ACTIVE	(iop->pdir |=  0x00000080)
#define I2C_TRISTATE	(iop->pdir &= ~0x00000080)
#define I2C_READ	((iop->pdat & 0x00000080) != 0)
#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00000080; \
			else    iop->pdat &= ~0x00000080
#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00000100; \
			else    iop->pdat &= ~0x00000100
#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */

#if 0
#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */

#define CONFIG_I2C_X
#endif

/*
 * select serial console configuration
 * use the extern UART for the console
 */
#define	CONFIG_CONS_INDEX	1
#define CONFIG_BAUDRATE		115200
/*
 * NS16550 Configuration
 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL

#define CONFIG_SYS_NS16550_REG_SIZE    1

#define CONFIG_SYS_NS16550_CLK         14745600

#define	CONFIG_SYS_UART_BASE	0xE0000000
#define CONFIG_SYS_UART_SIZE	0x10000

#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_UART_BASE + 0x8000)


/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT	1
#define CONFIG_OF_BOARD_SETUP	1

#define OF_TBCLK	(bd->bi_busfreq / 4)
#define OF_STDOUT_PATH	"/soc@f0000000/serial8250@e0008000"


/*
 * select ethernet configuration
 *
 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
 * for FCC)
 *
 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
 */
#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC       */
#define	CONFIG_ETHER_ON_FCC		/* define if ether on FCC       */
#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
#define	CONFIG_ETHER_INDEX	1	/* which SCC/FCC channel for ethernet */
#define CONFIG_ETHER_ON_FCC1
#define FCC_ENET

/*
 * - Rx-CLK is CLK10
 * - Tx-CLK is CLK9
 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
 * - Enable Full Duplex in FSMR
 */
# define CONFIG_SYS_CMXFCR_MASK1	(CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
# define CONFIG_SYS_CMXFCR_VALUE1	(CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK9)
# define CONFIG_SYS_CPMFCR_RAMTYPE	0
# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)


/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
#define CONFIG_8260_CLKIN	66666666	/* in Hz */

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE

#define CONFIG_RTC_PCF8563
#define CONFIG_SYS_I2C_RTC_ADDR		0x51

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_DHCP
#define CONFIG_CMD_NFS
#define CONFIG_CMD_NAND
#define CONFIG_CMD_I2C
#define CONFIG_CMD_SNTP


/*
 * Miscellaneous configurable options
 */
#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END	0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define	CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address	*/

#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/

#define	CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC	/* "bad" address		*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */

#define CONFIG_SYS_FLASH_CFI				/* The flash is CFI compatible  */
#define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver        */
#define CONFIG_SYS_FLASH_BANKS_LIST	{ 0xFF800000 }
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks	      */
/* What should the base address of the main FLASH be and how big is
 * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/ids8247/config.mk
 * The main FLASH is whichever is connected to *CS0.
 */
#define CONFIG_SYS_FLASH0_BASE 0xFFF00000
#define CONFIG_SYS_FLASH0_SIZE 8

/* Flash bank size (for preliminary settings)
 */
#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */

#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */

/* Environment in flash */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE+0x60000)
#define CONFIG_ENV_SIZE		0x20000
#define CONFIG_ENV_SECT_SIZE	0x20000

/*-----------------------------------------------------------------------
 * NAND-FLASH stuff
 *-----------------------------------------------------------------------
 */
#if defined(CONFIG_CMD_NAND)

#define CONFIG_SYS_NAND0_BASE 0xE1000000
#define CONFIG_SYS_MAX_NAND_DEVICE     1       /* Max number of NAND devices           */

#endif /* CONFIG_CMD_NAND */

/*-----------------------------------------------------------------------
 * Hard Reset Configuration Words
 *
 * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
 * defines for the various registers affected by the HRCW e.g. changing
 * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
 */
#define CONFIG_SYS_HRCW_MASTER	(HRCW_BPS01 | HRCW_BMS | HRCW_ISB100 | HRCW_APPC10 | HRCW_MODCK_H1000)

/* no slaves so just fill with zeros */
#define CONFIG_SYS_HRCW_SLAVE1		0
#define CONFIG_SYS_HRCW_SLAVE2		0
#define CONFIG_SYS_HRCW_SLAVE3		0
#define CONFIG_SYS_HRCW_SLAVE4		0
#define CONFIG_SYS_HRCW_SLAVE5		0
#define CONFIG_SYS_HRCW_SLAVE6		0
#define CONFIG_SYS_HRCW_SLAVE7		0

/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CONFIG_SYS_IMMR		0xF0000000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
#define CONFIG_SYS_INIT_RAM_SIZE	0x2000  /* Size of used area in DPRAM    */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 *
 * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_FLASH0_BASE
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
#if defined(CONFIG_CMD_KGDB)
# define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

/*-----------------------------------------------------------------------
 * HIDx - Hardware Implementation-dependent Registers                    2-11
 *-----------------------------------------------------------------------
 * HID0 also contains cache control - initially enable both caches and
 * invalidate contents, then the final state leaves only the instruction
 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 * but Soft reset does not.
 *
 * HID1 has only read-only information - nothing to set.
 */

#define CONFIG_SYS_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI)
#define CONFIG_SYS_HID0_FINAL  0
#define CONFIG_SYS_HID2        0

/*-----------------------------------------------------------------------
 * RMR - Reset Mode Register                                     5-5
 *-----------------------------------------------------------------------
 * turn on Checkstop Reset Enable
 */
#define CONFIG_SYS_RMR         0

/*-----------------------------------------------------------------------
 * BCR - Bus Configuration                                       4-25
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_BCR		0

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration                             4-31
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_SIUMCR      (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_BCTLC01)

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control                             4-35
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 */
#if defined(CONFIG_WATCHDOG)
#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
#else
#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
			 SYPCR_SWRI|SYPCR_SWP)
#endif /* CONFIG_WATCHDOG */

/*-----------------------------------------------------------------------
 * TMCNTSC - Time Counter Status and Control                     4-40
 *-----------------------------------------------------------------------
 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 * and enable Time Counter
 */
#define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control                 4-42
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 * Periodic timer
 */
#define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)

/*-----------------------------------------------------------------------
 * SCCR - System Clock Control                                   9-8
 *-----------------------------------------------------------------------
 * Ensure DFBRG is Divide by 16
 */
#define CONFIG_SYS_SCCR        (0x00000028 | SCCR_DFBRG01)

/*-----------------------------------------------------------------------
 * RCCR - RISC Controller Configuration                         13-7
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_RCCR        0

/*
 * Init Memory Controller:
 *
 * Bank Bus     Machine PortSz  Device
 * ---- ---     ------- ------  ------
 *  0   60x     GPCM    16 bit  FLASH
 *  1   60x     GPCM     8 bit  NAND
 *  2   60x     SDRAM   32 bit  SDRAM
 *  3   60x     GPCM     8 bit  UART
 *
 */

#define SDRAM_MAX_SIZE	0x08000000	/* max. 128 MB		*/

/* Minimum mask to separate preliminary
 * address ranges for CS[0:2]
 */
#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT	(32<<20)	/* less than 32 MB */

#define CONFIG_SYS_MPTPR       0x6600

/*-----------------------------------------------------------------------------
 * Address for Mode Register Set (MRS) command
 *-----------------------------------------------------------------------------
 */
#define CONFIG_SYS_MRS_OFFS	0x00000110


/* Bank 0 - FLASH
 */
#define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)  |\
			 BRx_PS_8                       |\
			 BRx_MS_GPCM_P                  |\
			 BRx_V)

#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE)      |\
			 ORxG_SCY_6_CLK                 )

#if defined(CONFIG_CMD_NAND)
/* Bank 1 - NAND Flash
*/
#define	CONFIG_SYS_NAND_BASE		CONFIG_SYS_NAND0_BASE
#define	CONFIG_SYS_NAND_SIZE		0x8000

#define CONFIG_SYS_OR_TIMING_NAND	0x000036

#define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_NAND_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V  )
#define CONFIG_SYS_OR1_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_NAND_SIZE) | CONFIG_SYS_OR_TIMING_NAND )
#endif

/* Bank 2 - 60x bus SDRAM
 */
#define CONFIG_SYS_PSRT        0x20
#define CONFIG_SYS_LSRT        0x20

#define CONFIG_SYS_BR2_PRELIM  ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)  |\
			 BRx_PS_32                      |\
			 BRx_MS_SDRAM_P                 |\
			 BRx_V)

#define CONFIG_SYS_OR2_PRELIM	CONFIG_SYS_OR2


/* SDRAM initialization values
*/
#define CONFIG_SYS_OR2    ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
			 ORxS_BPD_4                     |\
			 ORxS_ROWST_PBI0_A9		|\
			 ORxS_NUMR_12)

#define CONFIG_SYS_PSDMR  (PSDMR_SDAM_A14_IS_A5 |\
			 PSDMR_BSMA_A15_A17           |\
			 PSDMR_SDA10_PBI0_A10		|\
			 PSDMR_RFRC_5_CLK               |\
			 PSDMR_PRETOACT_2W              |\
			 PSDMR_ACTTORW_2W               |\
			 PSDMR_BL                       |\
			 PSDMR_LDOTOPRE_2C              |\
			 PSDMR_WRC_3C                   |\
			 PSDMR_CL_3)

/* Bank 3 - UART
*/

#define CONFIG_SYS_BR3_PRELIM  ((CONFIG_SYS_UART_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V  )
#define CONFIG_SYS_OR3_PRELIM  (((-CONFIG_SYS_UART_SIZE) & ORxG_AM_MSK) | ORxG_CSNT | ORxG_SCY_1_CLK | ORxG_TRLX )

#endif	/* __CONFIG_H */
Commit	Line	Data
9dd41a7b WD	1	/*
	2	* (C) Copyright 2005
	3	* Heiko Schocher, DENX Software Engineering, <hs@denx.de>
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
9dd41a7b WD	6	*/
	7
	8	/*
	9	* board/config.h - configuration options, board specific
	10	*/
	11
	12	#ifndef __CONFIG_H
	13	#define __CONFIG_H
	14
	15	/*
	16	* High Level Configuration Options
	17	* (easy to change)
	18	*/
	19
	20	#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */
	21	#define CONFIG_MPC8272_FAMILY 1
	22	#define CONFIG_IDS8247 1
	23	#define CPU_ID_STR "MPC8247"
9c4c5ae3	24	#define CONFIG_CPM2 1 /* Has a CPM2 */
9dd41a7b	25
2ae18241 WD	26	#define CONFIG_SYS_TEXT_BASE 0xfff00000
2ae18241 WD	27
9dd41a7b WD	28	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	29
	30	#define CONFIG_BOOTCOUNT_LIMIT
	31
32bf3d14	32	#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
9dd41a7b WD	33
	34	#undef CONFIG_BOOTARGS
	35
	36	#define CONFIG_EXTRA_ENV_SETTINGS \
	37	"netdev=eth0\0" \
	38	"nfsargs=setenv bootargs root=/dev/nfs rw " \
fe126d8b	39	"nfsroot=${serverip}:${rootpath}\0" \
9dd41a7b WD	40	"ramargs=setenv bootargs root=/dev/ram rw " \
9dd41a7b WD	41	"console=ttyS0,115200\0" \
fe126d8b WD	42	"addip=setenv bootargs ${bootargs} " \
	43	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	44	":${hostname}:${netdev}:off panic=1\0" \
9dd41a7b	45	"flash_nfs=run nfsargs addip;" \
fe126d8b	46	"bootm ${kernel_addr}\0" \
9dd41a7b	47	"flash_self=run ramargs addip;" \
fe126d8b WD	48	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
fe126d8b WD	49	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
9dd41a7b WD	50	"rootpath=/opt/eldk/ppc_82xx\0" \
	51	"bootfile=/tftpboot/IDS8247/uImage\0" \
	52	"kernel_addr=ff800000\0" \
	53	"ramdisk_addr=ffa00000\0" \
	54	""
	55	#define CONFIG_BOOTCOMMAND "run flash_self"
	56
	57	#define CONFIG_MISC_INIT_R 1
	58
	59	/* enable I2C and select the hardware/software driver */
	60	#undef CONFIG_HARD_I2C /* I2C with hardware support */
	61	#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
6d0f6bcf JCPV	62	#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
6d0f6bcf JCPV	63	#define CONFIG_SYS_I2C_SLAVE 0x7F
9dd41a7b WD	64
	65	/*
	66	* Software (bit-bang) I2C driver configuration
	67	*/
	68
	69	#define I2C_PORT 0 /* Port A=0, B=1, C=2, D=3 */
	70	#define I2C_ACTIVE (iop->pdir \|= 0x00000080)
	71	#define I2C_TRISTATE (iop->pdir &= ~0x00000080)
	72	#define I2C_READ ((iop->pdat & 0x00000080) != 0)
	73	#define I2C_SDA(bit) if(bit) iop->pdat \|= 0x00000080; \
	74	else iop->pdat &= ~0x00000080
	75	#define I2C_SCL(bit) if(bit) iop->pdat \|= 0x00000100; \
	76	else iop->pdat &= ~0x00000100
	77	#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
	78
	79	#if 0
6d0f6bcf JCPV	80	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
	81	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
	82	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
	83	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
9dd41a7b WD	84
	85	#define CONFIG_I2C_X
	86	#endif
	87
	88	/*
	89	* select serial console configuration
	90	* use the extern UART for the console
	91	*/
	92	#define CONFIG_CONS_INDEX 1
	93	#define CONFIG_BAUDRATE 115200
	94	/*
	95	* NS16550 Configuration
	96	*/
6d0f6bcf JCPV	97	#define CONFIG_SYS_NS16550
6d0f6bcf JCPV	98	#define CONFIG_SYS_NS16550_SERIAL
9dd41a7b	99
6d0f6bcf	100	#define CONFIG_SYS_NS16550_REG_SIZE 1
9dd41a7b	101
6d0f6bcf	102	#define CONFIG_SYS_NS16550_CLK 14745600
9dd41a7b	103
6d0f6bcf JCPV	104	#define CONFIG_SYS_UART_BASE 0xE0000000
6d0f6bcf JCPV	105	#define CONFIG_SYS_UART_SIZE 0x10000
9dd41a7b	106
6d0f6bcf	107	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_UART_BASE + 0x8000)
9dd41a7b	108
6abd82e1 SS	109
	110	/* pass open firmware flat tree */
	111	#define CONFIG_OF_LIBFDT 1
	112	#define CONFIG_OF_BOARD_SETUP 1
	113
6abd82e1 SS	114	#define OF_TBCLK (bd->bi_busfreq / 4)
	115	#define OF_STDOUT_PATH "/soc@f0000000/serial8250@e0008000"
	116
	117
9dd41a7b WD	118	/*
	119	* select ethernet configuration
	120	*
	121	* if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
	122	* CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
	123	* for FCC)
	124	*
	125	* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
639221c7	126	* defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
9dd41a7b WD	127	*/
	128	#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
	129	#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
	130	#undef CONFIG_ETHER_NONE /* define if ether on something else */
6abd82e1 SS	131	#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
	132	#define CONFIG_ETHER_ON_FCC1
	133	#define FCC_ENET
9dd41a7b WD	134
9dd41a7b WD	135	/*
6abd82e1 SS	136	* - Rx-CLK is CLK10
6abd82e1 SS	137	* - Tx-CLK is CLK9
9dd41a7b WD	138	* - RAM for BD/Buffers is on the 60x Bus (see 28-13)
	139	* - Enable Full Duplex in FSMR
	140	*/
d4590da4 MF	141	# define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1\|CMXFCR_RF1CS_MSK\|CMXFCR_TF1CS_MSK)
d4590da4 MF	142	# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK10\|CMXFCR_TF1CS_CLK9)
6d0f6bcf JCPV	143	# define CONFIG_SYS_CPMFCR_RAMTYPE 0
6d0f6bcf JCPV	144	# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE\|FCC_PSMR_LPB)
9dd41a7b WD	145
	146
	147	/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
	148	#define CONFIG_8260_CLKIN 66666666 /* in Hz */
	149
	150	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	151	#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
9dd41a7b WD	152
	153	#undef CONFIG_WATCHDOG /* watchdog disabled */
	154
	155	#define CONFIG_TIMESTAMP /* Print image info with timestamp */
	156
7be044e4 JL	157	/*
	158	* BOOTP options
	159	*/
	160	#define CONFIG_BOOTP_SUBNETMASK
	161	#define CONFIG_BOOTP_GATEWAY
	162	#define CONFIG_BOOTP_HOSTNAME
	163	#define CONFIG_BOOTP_BOOTPATH
	164	#define CONFIG_BOOTP_BOOTFILESIZE
9dd41a7b	165
6abd82e1	166	#define CONFIG_RTC_PCF8563
6d0f6bcf	167	#define CONFIG_SYS_I2C_RTC_ADDR 0x51
9dd41a7b	168
348f258f JL	169	/*
	170	* Command line configuration.
	171	*/
	172	#include <config_cmd_default.h>
	173
	174	#define CONFIG_CMD_DHCP
	175	#define CONFIG_CMD_NFS
	176	#define CONFIG_CMD_NAND
	177	#define CONFIG_CMD_I2C
	178	#define CONFIG_CMD_SNTP
	179
9dd41a7b WD	180
	181	/*
	182	* Miscellaneous configurable options
	183	*/
6d0f6bcf JCPV	184	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	185	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
348f258f	186	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	187	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
9dd41a7b	188	#else
6d0f6bcf	189	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
9dd41a7b	190	#endif
6d0f6bcf JCPV	191	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	192	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	193	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
9dd41a7b	194
6d0f6bcf JCPV	195	#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
6d0f6bcf JCPV	196	#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
9dd41a7b	197
6d0f6bcf	198	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
9dd41a7b	199
6d0f6bcf	200	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
9dd41a7b	201
6d0f6bcf	202	#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
9dd41a7b WD	203
	204	/*
	205	* For booting Linux, the board info and command line data
	206	* have to be in the first 8 MB of memory, since this is
	207	* the maximum mapped by the Linux kernel during initialization.
	208	*/
6d0f6bcf	209	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
9dd41a7b	210
6d0f6bcf	211	#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
00b1883a	212	#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
6d0f6bcf	213	#define CONFIG_SYS_FLASH_BANKS_LIST { 0xFF800000 }
ca5def3f	214	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
9dd41a7b	215	/* What should the base address of the main FLASH be and how big is
14d0a02a	216	* it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/ids8247/config.mk
9dd41a7b WD	217	* The main FLASH is whichever is connected to *CS0.
9dd41a7b WD	218	*/
6d0f6bcf JCPV	219	#define CONFIG_SYS_FLASH0_BASE 0xFFF00000
6d0f6bcf JCPV	220	#define CONFIG_SYS_FLASH0_SIZE 8
9dd41a7b WD	221
	222	/* Flash bank size (for preliminary settings)
	223	*/
6d0f6bcf	224	#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
9dd41a7b WD	225
	226	/*-----------------------------------------------------------------------
	227	* FLASH organization
	228	*/
6d0f6bcf	229	#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
9dd41a7b	230
6d0f6bcf JCPV	231	#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
6d0f6bcf JCPV	232	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
9dd41a7b WD	233
9dd41a7b WD	234	/* Environment in flash */
5a1aceb0	235	#define CONFIG_ENV_IS_IN_FLASH 1
6d0f6bcf	236	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x60000)
0e8d1586 JCPV	237	#define CONFIG_ENV_SIZE 0x20000
0e8d1586 JCPV	238	#define CONFIG_ENV_SECT_SIZE 0x20000
9dd41a7b WD	239
	240	/*-----------------------------------------------------------------------
	241	* NAND-FLASH stuff
	242	*-----------------------------------------------------------------------
	243	*/
348f258f	244	#if defined(CONFIG_CMD_NAND)
9dd41a7b	245
6d0f6bcf	246	#define CONFIG_SYS_NAND0_BASE 0xE1000000
6d0f6bcf	247	#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
9dd41a7b	248
11799434	249	#endif /* CONFIG_CMD_NAND */
9dd41a7b WD	250
	251	/*-----------------------------------------------------------------------
	252	* Hard Reset Configuration Words
	253	*
6d0f6bcf	254	* if you change bits in the HRCW, you must also change the CONFIG_SYS_*
9dd41a7b	255	* defines for the various registers affected by the HRCW e.g. changing
6d0f6bcf	256	* HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
9dd41a7b	257	*/
6d0f6bcf	258	#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS01 \| HRCW_BMS \| HRCW_ISB100 \| HRCW_APPC10 \| HRCW_MODCK_H1000)
9dd41a7b WD	259
9dd41a7b WD	260	/* no slaves so just fill with zeros */
6d0f6bcf JCPV	261	#define CONFIG_SYS_HRCW_SLAVE1 0
	262	#define CONFIG_SYS_HRCW_SLAVE2 0
	263	#define CONFIG_SYS_HRCW_SLAVE3 0
	264	#define CONFIG_SYS_HRCW_SLAVE4 0
	265	#define CONFIG_SYS_HRCW_SLAVE5 0
	266	#define CONFIG_SYS_HRCW_SLAVE6 0
	267	#define CONFIG_SYS_HRCW_SLAVE7 0
9dd41a7b WD	268
	269	/*-----------------------------------------------------------------------
	270	* Internal Memory Mapped Register
	271	*/
6d0f6bcf	272	#define CONFIG_SYS_IMMR 0xF0000000
9dd41a7b WD	273
	274	/*-----------------------------------------------------------------------
	275	* Definitions for initial stack pointer and data area (in DPRAM)
	276	*/
6d0f6bcf	277	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
553f0982	278	#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */
25ddd1fb	279	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	280	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
9dd41a7b WD	281
	282	/*-----------------------------------------------------------------------
	283	* Start addresses for the final memory configuration
	284	* (Set up by the startup code)
6d0f6bcf	285	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
9dd41a7b	286	*
6d0f6bcf	287	* 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE
9dd41a7b	288	*/
6d0f6bcf JCPV	289	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	290	#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
14d0a02a	291	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf JCPV	292	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
6d0f6bcf JCPV	293	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
9dd41a7b	294
9dd41a7b WD	295	/*-----------------------------------------------------------------------
	296	* Cache Configuration
	297	*/
6d0f6bcf	298	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
348f258f	299	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	300	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
9dd41a7b WD	301	#endif
	302
	303	/*-----------------------------------------------------------------------
	304	* HIDx - Hardware Implementation-dependent Registers 2-11
	305	*-----------------------------------------------------------------------
	306	* HID0 also contains cache control - initially enable both caches and
	307	* invalidate contents, then the final state leaves only the instruction
	308	* cache enabled. Note that Power-On and Hard reset invalidate the caches,
	309	* but Soft reset does not.
	310	*
	311	* HID1 has only read-only information - nothing to set.
	312	*/
	313
6d0f6bcf JCPV	314	#define CONFIG_SYS_HID0_INIT (HID0_ICE\|HID0_DCE\|HID0_ICFI\|HID0_DCI)
	315	#define CONFIG_SYS_HID0_FINAL 0
	316	#define CONFIG_SYS_HID2 0
9dd41a7b WD	317
	318	/*-----------------------------------------------------------------------
	319	* RMR - Reset Mode Register 5-5
	320	*-----------------------------------------------------------------------
	321	* turn on Checkstop Reset Enable
	322	*/
6d0f6bcf	323	#define CONFIG_SYS_RMR 0
9dd41a7b WD	324
	325	/*-----------------------------------------------------------------------
	326	* BCR - Bus Configuration 4-25
	327	*-----------------------------------------------------------------------
	328	*/
6d0f6bcf	329	#define CONFIG_SYS_BCR 0
9dd41a7b WD	330
	331	/*-----------------------------------------------------------------------
	332	* SIUMCR - SIU Module Configuration 4-31
	333	*-----------------------------------------------------------------------
	334	*/
6d0f6bcf	335	#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00\|SIUMCR_APPC10\|SIUMCR_BCTLC01)
9dd41a7b WD	336
	337	/*-----------------------------------------------------------------------
	338	* SYPCR - System Protection Control 4-35
	339	* SYPCR can only be written once after reset!
	340	*-----------------------------------------------------------------------
	341	* Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
	342	*/
	343	#if defined(CONFIG_WATCHDOG)
6d0f6bcf	344	#define CONFIG_SYS_SYPCR (SYPCR_SWTC\|SYPCR_BMT\|SYPCR_PBME\|SYPCR_LBME\|\
9dd41a7b WD	345	SYPCR_SWRI\|SYPCR_SWP\|SYPCR_SWE)
9dd41a7b WD	346	#else
6d0f6bcf	347	#define CONFIG_SYS_SYPCR (SYPCR_SWTC\|SYPCR_BMT\|SYPCR_PBME\|SYPCR_LBME\|\
9dd41a7b WD	348	SYPCR_SWRI\|SYPCR_SWP)
	349	#endif /* CONFIG_WATCHDOG */
	350
	351	/*-----------------------------------------------------------------------
	352	* TMCNTSC - Time Counter Status and Control 4-40
	353	*-----------------------------------------------------------------------
	354	* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
	355	* and enable Time Counter
	356	*/
6d0f6bcf	357	#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC\|TMCNTSC_ALR\|TMCNTSC_TCF\|TMCNTSC_TCE)
9dd41a7b WD	358
	359	/*-----------------------------------------------------------------------
	360	* PISCR - Periodic Interrupt Status and Control 4-42
	361	*-----------------------------------------------------------------------
	362	* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
	363	* Periodic timer
	364	*/
6d0f6bcf	365	#define CONFIG_SYS_PISCR (PISCR_PS\|PISCR_PTF\|PISCR_PTE)
9dd41a7b WD	366
	367	/*-----------------------------------------------------------------------
	368	* SCCR - System Clock Control 9-8
	369	*-----------------------------------------------------------------------
	370	* Ensure DFBRG is Divide by 16
	371	*/
6d0f6bcf	372	#define CONFIG_SYS_SCCR (0x00000028 \| SCCR_DFBRG01)
9dd41a7b WD	373
	374	/*-----------------------------------------------------------------------
	375	* RCCR - RISC Controller Configuration 13-7
	376	*-----------------------------------------------------------------------
	377	*/
6d0f6bcf	378	#define CONFIG_SYS_RCCR 0
9dd41a7b WD	379
	380	/*
	381	* Init Memory Controller:
	382	*
	383	* Bank Bus Machine PortSz Device
	384	* ---- --- ------- ------ ------
	385	* 0 60x GPCM 16 bit FLASH
	386	* 1 60x GPCM 8 bit NAND
	387	* 2 60x SDRAM 32 bit SDRAM
	388	* 3 60x GPCM 8 bit UART
	389	*
	390	*/
	391
	392	#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
	393
	394	/* Minimum mask to separate preliminary
	395	* address ranges for CS[0:2]
	396	*/
6d0f6bcf	397	#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (32<<20) /* less than 32 MB */
9dd41a7b	398
6d0f6bcf	399	#define CONFIG_SYS_MPTPR 0x6600
9dd41a7b WD	400
	401	/*-----------------------------------------------------------------------------
	402	* Address for Mode Register Set (MRS) command
	403	*-----------------------------------------------------------------------------
	404	*/
6d0f6bcf	405	#define CONFIG_SYS_MRS_OFFS 0x00000110
9dd41a7b WD	406
	407
	408	/* Bank 0 - FLASH
	409	*/
6d0f6bcf	410	#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) \|\
9dd41a7b WD	411	BRx_PS_8 \|\
	412	BRx_MS_GPCM_P \|\
	413	BRx_V)
	414
6d0f6bcf	415	#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \|\
9dd41a7b WD	416	ORxG_SCY_6_CLK )
9dd41a7b WD	417
348f258f	418	#if defined(CONFIG_CMD_NAND)
9dd41a7b WD	419	/* Bank 1 - NAND Flash
9dd41a7b WD	420	*/
6d0f6bcf JCPV	421	#define CONFIG_SYS_NAND_BASE CONFIG_SYS_NAND0_BASE
6d0f6bcf JCPV	422	#define CONFIG_SYS_NAND_SIZE 0x8000
9dd41a7b	423
6d0f6bcf	424	#define CONFIG_SYS_OR_TIMING_NAND 0x000036
9dd41a7b	425
6d0f6bcf JCPV	426	#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_NAND_BASE & BRx_BA_MSK) \| BRx_PS_8 \| BRx_MS_GPCM_P \| BRx_V )
6d0f6bcf JCPV	427	#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_NAND_SIZE) \| CONFIG_SYS_OR_TIMING_NAND )
9dd41a7b WD	428	#endif
	429
	430	/* Bank 2 - 60x bus SDRAM
	431	*/
6d0f6bcf JCPV	432	#define CONFIG_SYS_PSRT 0x20
6d0f6bcf JCPV	433	#define CONFIG_SYS_LSRT 0x20
9dd41a7b	434
6d0f6bcf	435	#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) \|\
9dd41a7b WD	436	BRx_PS_32 \|\
	437	BRx_MS_SDRAM_P \|\
	438	BRx_V)
	439
6d0f6bcf	440	#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2
9dd41a7b WD	441
	442
	443	/* SDRAM initialization values
	444	*/
6d0f6bcf	445	#define CONFIG_SYS_OR2 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) \|\
9dd41a7b	446	ORxS_BPD_4 \|\
6abd82e1	447	ORxS_ROWST_PBI0_A9 \|\
9dd41a7b WD	448	ORxS_NUMR_12)
9dd41a7b WD	449
6d0f6bcf	450	#define CONFIG_SYS_PSDMR (PSDMR_SDAM_A14_IS_A5 \|\
9dd41a7b	451	PSDMR_BSMA_A15_A17 \|\
6abd82e1	452	PSDMR_SDA10_PBI0_A10 \|\
9dd41a7b WD	453	PSDMR_RFRC_5_CLK \|\
	454	PSDMR_PRETOACT_2W \|\
	455	PSDMR_ACTTORW_2W \|\
	456	PSDMR_BL \|\
	457	PSDMR_LDOTOPRE_2C \|\
	458	PSDMR_WRC_3C \|\
	459	PSDMR_CL_3)
	460
	461	/* Bank 3 - UART
	462	*/
	463
6d0f6bcf JCPV	464	#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_UART_BASE & BRx_BA_MSK) \| BRx_PS_8 \| BRx_MS_GPCM_P \| BRx_V )
6d0f6bcf JCPV	465	#define CONFIG_SYS_OR3_PRELIM (((-CONFIG_SYS_UART_SIZE) & ORxG_AM_MSK) \| ORxG_CSNT \| ORxG_SCY_1_CLK \| ORxG_TRLX )
9dd41a7b WD	466
9dd41a7b WD	467	#endif /* __CONFIG_H */