[people/ms/u-boot.git] / include / configs / IP860.h

/*
 * (C) Copyright 2000-2005
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC860		1	/* This is a MPC860 CPU		*/
#define CONFIG_IP860		1	/* ...on a IP860 board		*/

#define	CONFIG_SYS_TEXT_BASE	0x10000000

#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
#define CONFIG_RESET_PHY_R	1	/* Call reset_phy()		*/

#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
#define CONFIG_BAUDRATE		9600
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/

#define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" \
"\0load=tftp \"/tftpboot/u-boot.bin\"\0update=protect off 1:0;era 1:0;cp.b 100000 10000000 ${filesize}\0"

#undef	CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND							\
	"bootp; "								\
	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
	"bootm"

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/


/* enable I2C and select the hardware/software driver */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
#define CONFIG_SYS_I2C_SOFT_SPEED	50000
#define CONFIG_SYS_I2C_SOFT_SLAVE	0xFE
/*
 * Software (bit-bang) I2C driver configuration
 */
#define PB_SCL		0x00000020	/* PB 26 */
#define PB_SDA		0x00000010	/* PB 27 */

#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
			else    immr->im_cpm.cp_pbdat &= ~PB_SDA
#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
			else    immr->im_cpm.cp_pbdat &= ~PB_SCL
#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */

# define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM X24C16		*/
# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* bytes of address		*/
/* mask of address bits that overflow into the "EEPROM chip address"    */
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* takes up to 10 msec */

#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_BEDBUG
#define CONFIG_CMD_I2C
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH

/*
 * Miscellaneous configurable options
 */
#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#if defined(CONFIG_CMD_KGDB)
#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x00F00000	/* 1 ... 15MB in DRAM	*/

#define	CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address	*/

#define	CONFIG_SYS_PIO_MODE		0	/* IDE interface in PIO Mode 0	*/

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CONFIG_SYS_IMMR		0xF1000000	/* Non-standard value!!	*/

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define	CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		0x10000000
#ifdef	DEBUG
#define	CONFIG_SYS_MONITOR_LEN		(512 << 10)	/* Reserve 512 kB for Monitor	*/
#else
#if 0 /* need more space for I2C tests */
#define	CONFIG_SYS_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
#else
#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)
#endif
#endif
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	124	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#undef	CONFIG_ENV_IS_IN_FLASH
#undef	CONFIG_ENV_IS_IN_NVRAM
#undef  CONFIG_ENV_IS_IN_NVRAM
#undef	DEBUG_I2C
#define	CONFIG_ENV_IS_IN_EEPROM

#ifdef	CONFIG_ENV_IS_IN_NVRAM
#define CONFIG_ENV_ADDR		0x20000000	/* use SRAM	*/
#define CONFIG_ENV_SIZE		(16<<10)	/* use 16 kB	*/
#endif	/* CONFIG_ENV_IS_IN_NVRAM */

#ifdef	CONFIG_ENV_IS_IN_EEPROM
#define CONFIG_ENV_OFFSET		 512	/* Leave 512 bytes free for other data	*/
#define CONFIG_ENV_SIZE		1536	/* Use remaining space			*/
#endif	/* CONFIG_ENV_IS_IN_EEPROM */

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif
#define CONFIG_SYS_DELAYED_ICACHE	1	/* enable ICache not before
						 * running in RAM.
						 */

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 * +0x0004
 */
#if defined(CONFIG_WATCHDOG)
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
#else
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 * +0x0000 => 0x80600800
 */
#define CONFIG_SYS_SIUMCR	(SIUMCR_EARB   | SIUMCR_EARP0 | \
			 SIUMCR_DBGC11 | SIUMCR_MLRC10)

/*-----------------------------------------------------------------------
 * Clock Setting - get clock frequency from Board Revision Register
 *-----------------------------------------------------------------------
 */
#ifndef __ASSEMBLY__
extern  unsigned long           ip860_get_clk_freq (void);
#endif
#define	CONFIG_8xx_GCLK_FREQ	ip860_get_clk_freq()

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 * +0x0200 => 0x00C2
 */
#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 * +0x0240 => 0x0082
 */
#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer
 * interrupt status bit, set PLL multiplication factor !
 */
/* +0x0286 => was: 0x0000D000 */
#define CONFIG_SYS_PLPRCR							\
		(	PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST |	\
			/*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL |		\
			PLPRCR_CSR   | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/	\
		)

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	SCCR_EBDF11
#define CONFIG_SYS_SCCR	(SCCR_COM00	|   SCCR_TBS	  |	\
			 SCCR_RTDIV	|   SCCR_RTSEL	  |	\
			 /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/	\
			 SCCR_EBDF00	|   SCCR_DFSYNC00 |	\
			 SCCR_DFBRG00	|   SCCR_DFNL000  |	\
			 SCCR_DFNH000)

/*-----------------------------------------------------------------------
 * RTCSC - Real-Time Clock Status and Control Register		11-27
 *-----------------------------------------------------------------------
 */
/* +0x0220 => 0x00C3 */
#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)


/*-----------------------------------------------------------------------
 * RCCR - RISC Controller Configuration Register		19-4
 *-----------------------------------------------------------------------
 */
/* +0x09C4 => TIMEP=1 */
#define CONFIG_SYS_RCCR 0x0100

/*-----------------------------------------------------------------------
 * RMDS - RISC Microcode Development Support Control Register
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_RMDS 0

/*-----------------------------------------------------------------------
 * DER - Debug Event Register
 *-----------------------------------------------------------------------
 *
 */
#define CONFIG_SYS_DER	0

/*
 * Init Memory Controller:
 */

/*
 * MAMR settings for SDRAM	- 16-14
 * => 0xC3804114
 */

/* periodic timer for refresh */
#define CONFIG_SYS_MAMR_PTA	0xC3

#define CONFIG_SYS_MAMR	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
/*
 * BR1 and OR1 (FLASH)
 */
#define FLASH_BASE		0x10000000	/* FLASH bank #0	*/

/* used to re-map FLASH
 * restrict access enough to keep SRAM working (if any)
 * but not too much to meddle with FLASH accesses
 */
/* allow for max 8 MB of Flash */
#define CONFIG_SYS_REMAP_OR_AM		0xFF800000	/* OR addr mask */
#define CONFIG_SYS_PRELIM_OR_AM	0xFF800000	/* OR addr mask */

#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_6_CLK)

#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
/* 16 bit, bank valid */
#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE & BR_BA_MSK) | BR_PS_32 | BR_V )

#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
#define CONFIG_SYS_BR1_PRELIM	CONFIG_SYS_BR0_PRELIM

/*
 * BR2/OR2 - SDRAM
 */
#define SDRAM_BASE		0x00000000	/* SDRAM bank */
#define SDRAM_PRELIM_OR_AM	0xF8000000	/* map max. 128 MB */
#define SDRAM_TIMING		0x00000A00	/* SDRAM-Timing */

#define SDRAM_MAX_SIZE		0x04000000	/* max 64 MB SDRAM */

#define CONFIG_SYS_OR2		(SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
#define CONFIG_SYS_BR2		((SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V )

/*
 * BR3/OR3 - SRAM (16 bit)
 */
#define	SRAM_BASE	0x20000000
#define CONFIG_SYS_OR3		0xFFF00130		/* BI/SCY = 5/TRLX (internal) */
#define CONFIG_SYS_BR3		((SRAM_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
#define SRAM_SIZE	(1 + (~(CONFIG_SYS_OR3 & BR_BA_MSK)))
#define CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR3			/* Make sure to map early */
#define CONFIG_SYS_BR3_PRELIM	CONFIG_SYS_BR3			/* in case it's used for ENV */
#define	CONFIG_SYS_SRAM_BASE	SRAM_BASE
#define	CONFIG_SYS_SRAM_SIZE	SRAM_SIZE

/*
 * BR4/OR4 - Board Control & Status (8 bit)
 */
#define	BCSR_BASE	0xFC000000
#define CONFIG_SYS_OR4		0xFFFF0120		/* BI (internal) */
#define CONFIG_SYS_BR4		((BCSR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)

/*
 * BR5/OR5 - IP Slot A/B (16 bit)
 */
#define	IP_SLOT_BASE	0x40000000
#define CONFIG_SYS_OR5		0xFE00010C		/* SETA/TRLX/BI/ SCY=0 (external) */
#define CONFIG_SYS_BR5		((IP_SLOT_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)

/*
 * BR6/OR6 - VME STD  (16 bit)
 */
#define	VME_STD_BASE	0xFE000000
#define CONFIG_SYS_OR6		0xFF00010C		/* SETA/TRLX/BI/SCY=0  (external) */
#define CONFIG_SYS_BR6		((VME_STD_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)

/*
 * BR7/OR7 - SHORT I/O + RTC + IACK  (16 bit)
 */
#define VME_SHORT_BASE	0xFF000000
#define CONFIG_SYS_OR7		0xFF00010C		/* SETA/TRLX/BI/ SCY=0 (external) */
#define CONFIG_SYS_BR7		((VME_SHORT_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)

/*-----------------------------------------------------------------------
 * Board Control and Status Region:
 *-----------------------------------------------------------------------
 */
#ifndef __ASSEMBLY__
typedef	struct ip860_bcsr_s {
	unsigned char	shmem_addr;	/* +00 shared memory address register	*/
	unsigned char	reserved0;
	unsigned char	mbox_addr;	/* +02 mailbox address register		*/
	unsigned char	reserved1;
	unsigned char	vme_int_mask;	/* +04 VME Bus interrupt mask register	*/
	unsigned char	reserved2;
	unsigned char	vme_int_pend;	/* +06 VME interrupt pending register	*/
	unsigned char	reserved3;
	unsigned char	bd_int_mask;	/* +08 board interrupt mask register	*/
	unsigned char	reserved4;
	unsigned char	bd_int_pend;	/* +0A board interrupt pending register	*/
	unsigned char	reserved5;
	unsigned char	bd_ctrl;	/* +0C board control register		*/
	unsigned char	reserved6;
	unsigned char	bd_status;	/* +0E board status  register		*/
	unsigned char	reserved7;
	unsigned char	vme_irq;	/* +10 VME interrupt request register	*/
	unsigned char	reserved8;
	unsigned char	vme_ivec;	/* +12 VME interrupt vector register	*/
	unsigned char	reserved9;
	unsigned char	cli_mbox;	/* +14 clear mailbox irq		*/
	unsigned char	reservedA;
	unsigned char	rtc;		/* +16 RTC control register		*/
	unsigned char	reservedB;
	unsigned char	mbox_data;	/* +18 mailbox read/write register	*/
	unsigned char	reservedC;
	unsigned char	wd_trigger;	/* +1A Watchdog trigger register	*/
	unsigned char	reservedD;
	unsigned char	rmw_req;	/* +1C RMW request register		*/
	unsigned char	reservedE;
	unsigned char	bd_rev;		/* +1E Board Revision register		*/
} ip860_bcsr_t;
#endif	/* __ASSEMBLY__ */

/*-----------------------------------------------------------------------
 * Board Control Register: bd_ctrl (Offset 0x0C)
 *-----------------------------------------------------------------------
 */
#define BD_CTRL_IPLSE	0x80	/* IP Slot Long Select Enable		*/
#define BD_CTRL_WDOGE	0x40	/* Watchdog Enable			*/
#define BD_CTRL_FLWE	0x20	/* Flash Write Enable			*/
#define BD_CTRL_RWDN	0x10	/* VMEBus Requester Release When Done Enable */

#endif	/* __CONFIG_H */
Commit	Line	Data
e2211743	1	/*
414eec35	2	* (C) Copyright 2000-2005
e2211743 WD	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
e2211743 WD	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
e2211743 WD	6	*/
	7
	8	/*
	9	* board/config.h - configuration options, board specific
	10	*/
	11
	12	#ifndef __CONFIG_H
	13	#define __CONFIG_H
	14
	15	/*
	16	* High Level Configuration Options
	17	* (easy to change)
	18	*/
	19
	20	#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
	21	#define CONFIG_IP860 1 /* ...on a IP860 board */
2ae18241 WD	22
	23	#define CONFIG_SYS_TEXT_BASE 0x10000000
	24
c837dcb1	25	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
004eca0c	26	#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
e2211743 WD	27
	28	#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
	29	#define CONFIG_BAUDRATE 9600
	30	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	31
32bf3d14	32	#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" \
fe126d8b	33	"\0load=tftp \"/tftpboot/u-boot.bin\"\0update=protect off 1:0;era 1:0;cp.b 100000 10000000 ${filesize}\0"
e2211743	34
e2211743 WD	35	#undef CONFIG_BOOTARGS
	36	#define CONFIG_BOOTCOMMAND \
	37	"bootp; " \
fe126d8b WD	38	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
fe126d8b WD	39	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
e2211743 WD	40	"bootm"
	41
	42	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	43	#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
e2211743 WD	44
	45	#undef CONFIG_WATCHDOG /* watchdog disabled */
	46
	47
	48	/* enable I2C and select the hardware/software driver */
ea818dbb HS	49	#define CONFIG_SYS_I2C
	50	#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
	51	#define CONFIG_SYS_I2C_SOFT_SPEED 50000
	52	#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
e2211743 WD	53	/*
	54	* Software (bit-bang) I2C driver configuration
	55	*/
	56	#define PB_SCL 0x00000020 /* PB 26 */
	57	#define PB_SDA 0x00000010 /* PB 27 */
	58
	59	#define I2C_INIT (immr->im_cpm.cp_pbdir \|= PB_SCL)
	60	#define I2C_ACTIVE (immr->im_cpm.cp_pbdir \|= PB_SDA)
	61	#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
	62	#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
	63	#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat \|= PB_SDA; \
	64	else immr->im_cpm.cp_pbdat &= ~PB_SDA
	65	#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat \|= PB_SCL; \
	66	else immr->im_cpm.cp_pbdat &= ~PB_SCL
	67	#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
	68
6d0f6bcf JCPV	69	# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM X24C16 */
6d0f6bcf JCPV	70	# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
e2211743	71	/* mask of address bits that overflow into the "EEPROM chip address" */
6d0f6bcf JCPV	72	#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
	73	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
	74	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */
e2211743	75
414eec35 WD	76	#define CONFIG_TIMESTAMP /* Print image info with timestamp */
414eec35 WD	77
e2211743	78
348f258f JL	79	/*
	80	* Command line configuration.
	81	*/
	82	#include <config_cmd_default.h>
e2211743	83
348f258f JL	84	#define CONFIG_CMD_BEDBUG
	85	#define CONFIG_CMD_I2C
	86	#define CONFIG_CMD_EEPROM
	87	#define CONFIG_CMD_NFS
	88	#define CONFIG_CMD_SNTP
e2211743	89
7be044e4 JL	90	/*
	91	* BOOTP options
	92	*/
	93	#define CONFIG_BOOTP_SUBNETMASK
	94	#define CONFIG_BOOTP_GATEWAY
	95	#define CONFIG_BOOTP_HOSTNAME
	96	#define CONFIG_BOOTP_BOOTPATH
e2211743 WD	97
	98	/*
	99	* Miscellaneous configurable options
	100	*/
6d0f6bcf	101	#define CONFIG_SYS_LONGHELP /* undef to save memory */
348f258f	102	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	103	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
e2211743	104	#else
6d0f6bcf	105	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
e2211743	106	#endif
6d0f6bcf JCPV	107	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	108	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	109	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
e2211743	110
6d0f6bcf JCPV	111	#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
6d0f6bcf JCPV	112	#define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
e2211743	113
6d0f6bcf	114	#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
e2211743	115
6d0f6bcf	116	#define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
e2211743	117
e2211743 WD	118	/*
	119	* Low Level Configuration Settings
	120	* (address mappings, register initial values, etc.)
	121	* You should know what you are doing if you make changes here.
	122	*/
	123	/*-----------------------------------------------------------------------
	124	* Internal Memory Mapped Register
	125	*/
6d0f6bcf	126	#define CONFIG_SYS_IMMR 0xF1000000 /* Non-standard value!! */
e2211743 WD	127
	128	/*-----------------------------------------------------------------------
	129	* Definitions for initial stack pointer and data area (in DPRAM)
	130	*/
6d0f6bcf	131	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
553f0982	132	#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
25ddd1fb	133	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	134	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
e2211743 WD	135
	136	/*-----------------------------------------------------------------------
	137	* Start addresses for the final memory configuration
	138	* (Set up by the startup code)
6d0f6bcf	139	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
e2211743	140	*/
6d0f6bcf JCPV	141	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	142	#define CONFIG_SYS_FLASH_BASE 0x10000000
e2211743	143	#ifdef DEBUG
6d0f6bcf	144	#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
e2211743 WD	145	#else
e2211743 WD	146	#if 0 /* need more space for I2C tests */
6d0f6bcf	147	#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
e2211743	148	#else
6d0f6bcf	149	#define CONFIG_SYS_MONITOR_LEN (256 << 10)
e2211743 WD	150	#endif
e2211743 WD	151	#endif
6d0f6bcf JCPV	152	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
6d0f6bcf JCPV	153	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
e2211743 WD	154
	155	/*
	156	* For booting Linux, the board info and command line data
	157	* have to be in the first 8 MB of memory, since this is
	158	* the maximum mapped by the Linux kernel during initialization.
	159	*/
6d0f6bcf	160	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
e2211743 WD	161	/*-----------------------------------------------------------------------
	162	* FLASH organization
	163	*/
6d0f6bcf JCPV	164	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
6d0f6bcf JCPV	165	#define CONFIG_SYS_MAX_FLASH_SECT 124 /* max number of sectors on one chip */
e2211743	166
6d0f6bcf JCPV	167	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	168	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
e2211743	169
5a1aceb0	170	#undef CONFIG_ENV_IS_IN_FLASH
9314cee6 JCPV	171	#undef CONFIG_ENV_IS_IN_NVRAM
9314cee6 JCPV	172	#undef CONFIG_ENV_IS_IN_NVRAM
e2211743	173	#undef DEBUG_I2C
bb1f8b4f	174	#define CONFIG_ENV_IS_IN_EEPROM
e2211743	175
9314cee6	176	#ifdef CONFIG_ENV_IS_IN_NVRAM
0e8d1586 JCPV	177	#define CONFIG_ENV_ADDR 0x20000000 /* use SRAM */
0e8d1586 JCPV	178	#define CONFIG_ENV_SIZE (16<<10) /* use 16 kB */
9314cee6	179	#endif /* CONFIG_ENV_IS_IN_NVRAM */
e2211743	180
bb1f8b4f	181	#ifdef CONFIG_ENV_IS_IN_EEPROM
0e8d1586 JCPV	182	#define CONFIG_ENV_OFFSET 512 /* Leave 512 bytes free for other data */
0e8d1586 JCPV	183	#define CONFIG_ENV_SIZE 1536 /* Use remaining space */
bb1f8b4f	184	#endif /* CONFIG_ENV_IS_IN_EEPROM */
e2211743 WD	185
	186	/*-----------------------------------------------------------------------
	187	* Cache Configuration
	188	*/
6d0f6bcf	189	#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
348f258f	190	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	191	#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
e2211743	192	#endif
506f3918 HS	193	#define CONFIG_SYS_DELAYED_ICACHE 1 /* enable ICache not before
	194	* running in RAM.
	195	*/
e2211743 WD	196
	197	/*-----------------------------------------------------------------------
	198	* SYPCR - System Protection Control 11-9
	199	* SYPCR can only be written once after reset!
	200	*-----------------------------------------------------------------------
	201	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
	202	* +0x0004
	203	*/
	204	#if defined(CONFIG_WATCHDOG)
6d0f6bcf	205	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
e2211743 WD	206	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
e2211743 WD	207	#else
6d0f6bcf	208	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| SYPCR_SWP)
e2211743 WD	209	#endif
	210
	211	/*-----------------------------------------------------------------------
	212	* SIUMCR - SIU Module Configuration 11-6
	213	*-----------------------------------------------------------------------
	214	* +0x0000 => 0x80600800
	215	*/
6d0f6bcf	216	#define CONFIG_SYS_SIUMCR (SIUMCR_EARB \| SIUMCR_EARP0 \| \
e2211743 WD	217	SIUMCR_DBGC11 \| SIUMCR_MLRC10)
	218
	219	/*-----------------------------------------------------------------------
8bde7f77	220	* Clock Setting - get clock frequency from Board Revision Register
e2211743 WD	221	*-----------------------------------------------------------------------
e2211743 WD	222	*/
3bac3513 WD	223	#ifndef __ASSEMBLY__
	224	extern unsigned long ip860_get_clk_freq (void);
	225	#endif
	226	#define CONFIG_8xx_GCLK_FREQ ip860_get_clk_freq()
e2211743 WD	227
	228	/*-----------------------------------------------------------------------
	229	* TBSCR - Time Base Status and Control 11-26
	230	*-----------------------------------------------------------------------
	231	* Clear Reference Interrupt Status, Timebase freezing enabled
	232	* +0x0200 => 0x00C2
	233	*/
6d0f6bcf	234	#define CONFIG_SYS_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBF)
e2211743 WD	235
	236	/*-----------------------------------------------------------------------
	237	* PISCR - Periodic Interrupt Status and Control 11-31
	238	*-----------------------------------------------------------------------
	239	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	240	* +0x0240 => 0x0082
	241	*/
6d0f6bcf	242	#define CONFIG_SYS_PISCR (PISCR_PS \| PISCR_PITF)
e2211743 WD	243
	244	/*-----------------------------------------------------------------------
	245	* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
	246	*-----------------------------------------------------------------------
	247	* Reset PLL lock status sticky bit, timer expired status bit and timer
	248	* interrupt status bit, set PLL multiplication factor !
	249	*/
	250	/* +0x0286 => was: 0x0000D000 */
6d0f6bcf	251	#define CONFIG_SYS_PLPRCR \
e2211743 WD	252	( PLPRCR_SPLSS \| PLPRCR_TEXPS \| PLPRCR_TMIST \| \
	253	/PLPRCR_CSRC\|/ PLPRCR_LPM_NORMAL \| \
	254	PLPRCR_CSR \| PLPRCR_LOLRE /\|PLPRCR_FIOPD/ \
	255	)
	256
	257	/*-----------------------------------------------------------------------
	258	* SCCR - System Clock and reset Control Register 15-27
	259	*-----------------------------------------------------------------------
	260	* Set clock output, timebase and RTC source and divider,
	261	* power management and some other internal clocks
	262	*/
	263	#define SCCR_MASK SCCR_EBDF11
6d0f6bcf	264	#define CONFIG_SYS_SCCR (SCCR_COM00 \| SCCR_TBS \| \
e2211743 WD	265	SCCR_RTDIV \| SCCR_RTSEL \| \
	266	/SCCR_CRQEN\|/ /SCCR_PRQEN\|/ \
	267	SCCR_EBDF00 \| SCCR_DFSYNC00 \| \
	268	SCCR_DFBRG00 \| SCCR_DFNL000 \| \
	269	SCCR_DFNH000)
	270
	271	/*-----------------------------------------------------------------------
	272	* RTCSC - Real-Time Clock Status and Control Register 11-27
	273	*-----------------------------------------------------------------------
	274	*/
	275	/* +0x0220 => 0x00C3 */
6d0f6bcf	276	#define CONFIG_SYS_RTCSC (RTCSC_SEC \| RTCSC_ALR \| RTCSC_RTF\| RTCSC_RTE)
e2211743 WD	277
	278
	279	/*-----------------------------------------------------------------------
	280	* RCCR - RISC Controller Configuration Register 19-4
	281	*-----------------------------------------------------------------------
	282	*/
	283	/* +0x09C4 => TIMEP=1 */
6d0f6bcf	284	#define CONFIG_SYS_RCCR 0x0100
e2211743 WD	285
	286	/*-----------------------------------------------------------------------
	287	* RMDS - RISC Microcode Development Support Control Register
	288	*-----------------------------------------------------------------------
	289	*/
6d0f6bcf	290	#define CONFIG_SYS_RMDS 0
e2211743 WD	291
	292	/*-----------------------------------------------------------------------
	293	* DER - Debug Event Register
	294	*-----------------------------------------------------------------------
	295	*
	296	*/
6d0f6bcf	297	#define CONFIG_SYS_DER 0
e2211743 WD	298
	299	/*
	300	* Init Memory Controller:
	301	*/
	302
	303	/*
	304	* MAMR settings for SDRAM - 16-14
	305	* => 0xC3804114
	306	*/
	307
	308	/* periodic timer for refresh */
6d0f6bcf	309	#define CONFIG_SYS_MAMR_PTA 0xC3
e2211743	310
6d0f6bcf	311	#define CONFIG_SYS_MAMR ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
e2211743 WD	312	MAMR_AMA_TYPE_0 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A10 \| \
	313	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
	314	/*
	315	* BR1 and OR1 (FLASH)
	316	*/
	317	#define FLASH_BASE 0x10000000 /* FLASH bank #0 */
	318
	319	/* used to re-map FLASH
	320	* restrict access enough to keep SRAM working (if any)
	321	* but not too much to meddle with FLASH accesses
	322	*/
	323	/* allow for max 8 MB of Flash */
6d0f6bcf JCPV	324	#define CONFIG_SYS_REMAP_OR_AM 0xFF800000 /* OR addr mask */
6d0f6bcf JCPV	325	#define CONFIG_SYS_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
e2211743	326
6d0f6bcf	327	#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM \| OR_ACS_DIV2 \| OR_BI \| OR_SCY_6_CLK)
e2211743	328
6d0f6bcf JCPV	329	#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH)
6d0f6bcf JCPV	330	#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH)
e2211743	331	/* 16 bit, bank valid */
6d0f6bcf	332	#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE & BR_BA_MSK) \| BR_PS_32 \| BR_V )
e2211743	333
6d0f6bcf JCPV	334	#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
6d0f6bcf JCPV	335	#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_BR0_PRELIM
e2211743 WD	336
	337	/*
	338	* BR2/OR2 - SDRAM
	339	*/
	340	#define SDRAM_BASE 0x00000000 /* SDRAM bank */
	341	#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */
	342	#define SDRAM_TIMING 0x00000A00 /* SDRAM-Timing */
	343
	344	#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */
	345
6d0f6bcf JCPV	346	#define CONFIG_SYS_OR2 (SDRAM_PRELIM_OR_AM \| SDRAM_TIMING )
6d0f6bcf JCPV	347	#define CONFIG_SYS_BR2 ((SDRAM_BASE & BR_BA_MSK) \| BR_MS_UPMA \| BR_V )
e2211743 WD	348
	349	/*
	350	* BR3/OR3 - SRAM (16 bit)
	351	*/
	352	#define SRAM_BASE 0x20000000
6d0f6bcf JCPV	353	#define CONFIG_SYS_OR3 0xFFF00130 /* BI/SCY = 5/TRLX (internal) */
	354	#define CONFIG_SYS_BR3 ((SRAM_BASE & BR_BA_MSK) \| BR_PS_16 \| BR_V)
	355	#define SRAM_SIZE (1 + (~(CONFIG_SYS_OR3 & BR_BA_MSK)))
	356	#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR3 /* Make sure to map early */
	357	#define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_BR3 /* in case it's used for ENV */
36116650 WD	358	#define CONFIG_SYS_SRAM_BASE SRAM_BASE
36116650 WD	359	#define CONFIG_SYS_SRAM_SIZE SRAM_SIZE
e2211743 WD	360
	361	/*
	362	* BR4/OR4 - Board Control & Status (8 bit)
	363	*/
	364	#define BCSR_BASE 0xFC000000
6d0f6bcf JCPV	365	#define CONFIG_SYS_OR4 0xFFFF0120 /* BI (internal) */
6d0f6bcf JCPV	366	#define CONFIG_SYS_BR4 ((BCSR_BASE & BR_BA_MSK) \| BR_PS_8 \| BR_V)
e2211743 WD	367
	368	/*
	369	* BR5/OR5 - IP Slot A/B (16 bit)
	370	*/
	371	#define IP_SLOT_BASE 0x40000000
6d0f6bcf JCPV	372	#define CONFIG_SYS_OR5 0xFE00010C /* SETA/TRLX/BI/ SCY=0 (external) */
6d0f6bcf JCPV	373	#define CONFIG_SYS_BR5 ((IP_SLOT_BASE & BR_BA_MSK) \| BR_PS_16 \| BR_V)
e2211743 WD	374
	375	/*
	376	* BR6/OR6 - VME STD (16 bit)
	377	*/
	378	#define VME_STD_BASE 0xFE000000
6d0f6bcf JCPV	379	#define CONFIG_SYS_OR6 0xFF00010C /* SETA/TRLX/BI/SCY=0 (external) */
6d0f6bcf JCPV	380	#define CONFIG_SYS_BR6 ((VME_STD_BASE & BR_BA_MSK) \| BR_PS_16 \| BR_V)
e2211743 WD	381
	382	/*
	383	* BR7/OR7 - SHORT I/O + RTC + IACK (16 bit)
	384	*/
	385	#define VME_SHORT_BASE 0xFF000000
6d0f6bcf JCPV	386	#define CONFIG_SYS_OR7 0xFF00010C /* SETA/TRLX/BI/ SCY=0 (external) */
6d0f6bcf JCPV	387	#define CONFIG_SYS_BR7 ((VME_SHORT_BASE & BR_BA_MSK) \| BR_PS_16 \| BR_V)
e2211743 WD	388
	389	/*-----------------------------------------------------------------------
	390	* Board Control and Status Region:
	391	*-----------------------------------------------------------------------
	392	*/
	393	#ifndef __ASSEMBLY__
	394	typedef struct ip860_bcsr_s {
	395	unsigned char shmem_addr; /* +00 shared memory address register */
	396	unsigned char reserved0;
	397	unsigned char mbox_addr; /* +02 mailbox address register */
	398	unsigned char reserved1;
	399	unsigned char vme_int_mask; /* +04 VME Bus interrupt mask register */
	400	unsigned char reserved2;
	401	unsigned char vme_int_pend; /* +06 VME interrupt pending register */
	402	unsigned char reserved3;
	403	unsigned char bd_int_mask; /* +08 board interrupt mask register */
	404	unsigned char reserved4;
	405	unsigned char bd_int_pend; /* +0A board interrupt pending register */
	406	unsigned char reserved5;
	407	unsigned char bd_ctrl; /* +0C board control register */
	408	unsigned char reserved6;
	409	unsigned char bd_status; /* +0E board status register */
	410	unsigned char reserved7;
	411	unsigned char vme_irq; /* +10 VME interrupt request register */
	412	unsigned char reserved8;
	413	unsigned char vme_ivec; /* +12 VME interrupt vector register */
	414	unsigned char reserved9;
	415	unsigned char cli_mbox; /* +14 clear mailbox irq */
	416	unsigned char reservedA;
	417	unsigned char rtc; /* +16 RTC control register */
	418	unsigned char reservedB;
	419	unsigned char mbox_data; /* +18 mailbox read/write register */
	420	unsigned char reservedC;
	421	unsigned char wd_trigger; /* +1A Watchdog trigger register */
	422	unsigned char reservedD;
	423	unsigned char rmw_req; /* +1C RMW request register */
3bac3513 WD	424	unsigned char reservedE;
3bac3513 WD	425	unsigned char bd_rev; /* +1E Board Revision register */
e2211743 WD	426	} ip860_bcsr_t;
	427	#endif /* __ASSEMBLY__ */
	428
	429	/*-----------------------------------------------------------------------
	430	* Board Control Register: bd_ctrl (Offset 0x0C)
	431	*-----------------------------------------------------------------------
	432	*/
	433	#define BD_CTRL_IPLSE 0x80 /* IP Slot Long Select Enable */
	434	#define BD_CTRL_WDOGE 0x40 /* Watchdog Enable */
	435	#define BD_CTRL_FLWE 0x20 /* Flash Write Enable */
	436	#define BD_CTRL_RWDN 0x10 /* VMEBus Requester Release When Done Enable */
	437
e2211743	438	#endif /* __CONFIG_H */